TW201448126A - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package comprises a substrate, a chip and an under-fill. The substrate has a singulation path vertically penetrating the substrate and laterally extended from a periphery lateral surface of the substrate to another periphery lateral surface of the substrate along an upper surface of the substrate so as to form several sub-substrates separated from each other. The chip is disposed on the substrate. The under-fill is formed between the chip and the substrate.

Description

Semiconductor package and method of manufacturing same

The present invention relates to a semiconductor package and a method of fabricating the same, and more particularly to a semiconductor package capable of reducing the amount of warpage and a method of fabricating the same.

Conventional semiconductor substrates are becoming thinner and thinner, and the structures on both sides of the semiconductor substrate are asymmetrical, so warpage is likely to occur. When the amount of warpage of the semiconductor substrate is larger, problems such as poor bonding of the wafer and the substrate are likely to occur in a process in which the subsequent wafer is placed thereon.

The present invention relates to a semiconductor package and a method of fabricating the same that can reduce the amount of warpage of a semiconductor package.

According to an embodiment of the invention, a semiconductor package is proposed. The semiconductor package includes a substrate, a wafer, and a primer. The substrate has a dividing passage, the dividing passage vertically penetrates the substrate, and extends laterally from one edge side of the substrate to the other edge side of the substrate along the upper surface of the substrate, so that the substrate forms a plurality of sub-substrates separated from each other. The wafer is disposed on the substrate. A primer is formed between the wafer and the substrate.

According to an embodiment of the present invention, a method of fabricating a semiconductor package is provided. The manufacturing method includes the following steps. Providing a substrate on a carrier; forming a dividing passage through the substrate, and extending laterally from an edge side of the substrate to the other edge side of the substrate along the upper surface of the substrate, so that the substrate forms a plurality of separated sides a substrate; a wafer is disposed on the substrate; a primer is formed between the wafer and the substrate; and the carrier is removed.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

100,200‧‧‧ semiconductor package

10‧‧‧ Carrier Board

11‧‧‧Adhesive layer

12‧‧‧ patterned photoresist layer

12a, 1143a‧‧ hole

110‧‧‧Substrate

110r, 110r’, 110r” ‧ ‧ divided road

110s‧‧‧ edge side

110s1‧‧‧ first edge side

110s2‧‧‧Second edge side

111‧‧‧Sub Substrate

110b, 112b‧‧‧ lower surface

110u, 112u‧‧‧ upper surface

110a, 1131a‧‧ hole

112‧‧‧Substrate

113, 113’, 113”‧‧‧ conductive holes

Conductive mechanism within 1131‧‧

1132‧‧‧External dielectric layer

1133‧‧‧ conduction layer

114‧‧‧First line layer

1141; 1151‧‧‧ first dielectric layer

1142‧‧‧First redistributed circuit layer

1143, 1153‧‧‧ second dielectric layer

115‧‧‧Second circuit layer

1152‧‧‧Second redistribution circuit layer

116, 121‧‧‧ electrical contacts

120‧‧‧ wafer

130‧‧‧Bottom

D1‧‧‧ lateral

P‧‧‧ cutting road

W1‧‧‧Width

1A is a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention.

Fig. 1B is a plan view showing Fig. 1A.

2A is a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention.

Fig. 2B is a plan view showing Fig. 2A.

3A to 3F are views showing a manufacturing process of the semiconductor package of FIG. 1A.

FIG. 4 is a view showing another manufacturing process of the semiconductor package of FIG. 1B.

5A to 5B are views showing a manufacturing process of the semiconductor package of FIG. 2A.

Referring to FIG. 1A, a cross-sectional view of a semiconductor package in accordance with an embodiment of the present invention is shown. The semiconductor package 100 includes a substrate 110, a wafer 120, and a primer 130.

The substrate 110 is, for example, a wafer or an interposer substrate. The substrate 110 includes at least one sub-substrate 111, a substrate 112, a conductive via 113, a first wiring layer 114, a second wiring layer 115, at least one electrical contact 116, a dividing lane 110r, an upper surface 110u, and an edge side 110s (110s1) , 110s2).

The sub-substrate 111 is formed by separating the substrate 110 by the dividing lane 110r, and the dividing lane 110r extends from the upper surface 110u of the substrate 110 to the lower surface 110b of the substrate 110 to penetrate the substrate 110, and the dividing lane 110r is exposed from the lower surface 110b of the substrate 110.

The substrate 112 is, for example, a material formed of glass, silicon, metal, metal alloy, polymer, or another suitable structural material. The substrate 112 has a relatively upper surface 112u and a lower surface 112b.

The conductive hole 113 penetrates the substrate 112 from the upper surface 112u and is electrically connected to the first redistribution wiring layer 1142 and the second redistribution wiring layer 1152. In an embodiment, the conductive holes 113 may be exposed from the upper surface 112u and the lower surface 112b of the substrate 112. In another embodiment, the conductive holes 113 may protrude beyond the upper surface 112u and/or the lower surface of the substrate 112. 112b.

The substrate 110 further defines an opening 110a, and the conductive hole 113 is at least partially disposed in the opening 110a. The conductive via 113 may be a through silicon via (TSV). The conductive via 113 includes an inner conductive mechanism 1131 and an outer dielectric layer 1132. The inner conductive mechanism 1131 is exposed from the upper surface 112u and the lower surface 112b of the substrate 112, and the outer dielectric layer 1132 surrounds the inner conductive mechanism 1131. The outer dielectric layer 1132 can be disposed adjacent to the sidewall of the opening 110a. In this embodiment, the conductive mechanism 1131 in the outer dielectric layer 1132 can substantially fill the opening 110a.

In another embodiment, the conductive mechanism 1131 within the conductive via 113' can protrude beyond the upper surface 112u and the lower surface 112b of the substrate 112. In this embodiment, the outer dielectric layer 1132 can also protrude beyond the upper surface 112u and the lower surface 112b. A conductive layer 1133 can be disposed adjacent to the protruding portions of the inner conductive mechanism 1131 and the outer dielectric layer 1132. The conductive via 113' is electrically connected to the first redistribution wiring layer 1142 through the conductive layer 1133.

In other embodiments, the conductive via 113" includes an inner conductive mechanism 1131 and an outer dielectric layer 1132. The inner conductive mechanism 1131 is an annular plating layer. The inner conductive mechanism 1131 can define an opening 1131a. In addition, the inner conductive mechanism 1131 can be An inner dielectric layer (not shown) is filled.

In other embodiments, the conductive via 113 includes an internal conductive mechanism 1131. The inner conductive mechanism 1131 is disposed directly adjacent to the substrate 112. In this embodiment, the substrate 112 is made of a non-conductive material such as glass. The inner conductive mechanism 1131 can define an opening (not shown) similar to one of the openings 1131a.

The first wiring layer 114 is formed on the lower surface 112b of the substrate 112. The first circuit layer 114 includes a first dielectric layer 1141, a first redistribution wiring layer 1142, and a second dielectric layer 1143. The first dielectric layer 1141 is formed on the lower surface 112b of the substrate 112 and exposes the conductive holes 113 of the substrate 110. The first redistribution circuit layer 1142 is formed on the exposed conductive hole 113 to electrically connect the conductive holes 113. The second dielectric layer 1143 is formed on the first redistribution wiring layer 1142 and is exposed to a portion of the first redistribution wiring layer 1142. In this embodiment, since the dividing lane 110r bypasses the first redistribution wiring layer 1142 of the first wiring layer 114, the first redistribution wiring layer 1142 is not penetrated, so that any adjacent sub-substrate 111 is not transmitted through the first The circuit layer 1142 is redistributed and has a direct electrical connection relationship.

In addition, the material of the first dielectric layer 1141 is, for example, an organic protective layer, Tantalum nitride, yttria or a polymer. The material of the second dielectric layer 1143 may be the same as or different from the first dielectric layer 1141. The thickness of the first dielectric layer 1141 may be the same or different from the second dielectric layer 1143.

The second wiring layer 115 is formed on the upper surface 112u of the substrate 112. The second circuit layer 115 includes a first dielectric layer 1151, a second redistribution wiring layer 1152, and a second dielectric layer 1153. The first dielectric layer 1151 is formed on the upper surface 112u of the substrate 112 and exposes the conductive holes 113 of the substrate 110. The second redistribution wiring layer 1152 is formed on the exposed conductive hole 113 to electrically connect the conductive via 113. The second dielectric layer 1153 is formed on the second redistribution wiring layer 1152 and is exposed to a portion of the second redistribution wiring layer 1152, so that the wafer 120 can be electrically connected to the conductive via 113 through the exposed double wiring layer 1152. . In this embodiment, since the dividing lane 110r bypasses the second redistribution wiring layer 1152 of the second wiring layer 115, the second redistribution wiring layer 1152 is not penetrated, so that any adjacent sub-substrate 111 is not transmitted through the second. The circuit layer 1152 is redistributed and has a direct electrical connection relationship.

Further, the material of the first dielectric layer 1151 is, for example, an organic protective layer, tantalum nitride, hafnium oxide or a polymer. The material of the second dielectric layer 1153 may be the same as or different from the first dielectric layer 1151. The thickness of the first dielectric layer 1151 may be the same or different from the second dielectric layer 1153.

The materials and thicknesses of the first dielectric layer and the second dielectric layer on opposite sides of the substrate 112 may be the same or different. When the materials and/or thicknesses of the first dielectric layer and the second dielectric layer on the opposite sides of the substrate 112 are different, the asymmetry of the substrate 110 is increased, and even if so, through the embodiment of the present invention With the design of the dividing track 110r, the accumulated warpage amount of the semiconductor package 100 can still be controlled within a small range or a desired range.

Electrical contacts 116 are, for example, solder balls, conductive posts or bumps. Electrical contacts 116 are formed on the exposed first redistribution wiring layer 1142 to be electrically connected to the wafer 120.

The wafer 120 is disposed on the upper surface 110u of the substrate 110 with the active surface facing downward. The wafer 120 has at least one electrical contact 121 electrically connected to the conductive hole 113 of the substrate 110. Such a wafer 120 is referred to as a flip chip. The electrical contact 121 is, for example, a solder ball, Conductive post or bump. In another example, the wafer 120 is disposed on the upper surface 110u of the substrate 110 with the active surface facing upward, and is electrically connected to the substrate 110 by at least one bonding wire.

The primer 130 is formed between the wafer 120 and the substrate 110. The primer 130 covers the electrical contacts 121 to protect the electrical contacts 121 from or from the external environment. In addition, a portion of the primer 130 enters a portion of the dividing lane 110r to bond the separated sub-substrate 111, thereby enhancing the overall strength of the substrate 110. In another example, a portion of the primer 130 can enter the entire dividing lane 110r, so that the bonding between the separated two sub-substrates 111 is better improved.

The primer 130 may be formed of a molding material. The encapsulating material may include a novola-based resin, an epoxy-based resin, a silicone-based resin, or other suitable coating agents. The encapsulating material may also include a suitable filler, such as powdered cerium oxide. The encapsulating material may be a pre-impregnated (prepreg) material, such as a pre-impregnated dielectric material.

Please refer to FIG. 1B, which shows a top view of FIG. 1A. The dividing lanes 110r (110r', 110r") extend laterally from the edge side faces 110s (110s1, 110s2) of the substrate 110 to the other edge side faces 110s (110s1, 110s2) along the upper surface 110u. For example, the edge side faces 110s include opposite sides The first edge side 110s1 and the second edge side 110s2, the dividing lane 110r' extend laterally from the first edge side 110s1 to the second edge side 110s2 along the upper surface 110u. For another example, the edge side 110s includes the first adjacent one. The edge side 110s1 and the second edge side 110s3, the dividing lane 110r" extend laterally from the first edge side 110s1 to the second edge side 110s3 along the upper surface 110u. And the dividing track 110r (110r', 110r") penetrates the substrate 110, and the substrate 110 is formed into a plurality of sub-substrates 111 separated from each other. Since the substrate 110 is separated into a plurality of sub-substrates 111, the semiconductor package 100 can be reduced in the process or use process. In the case where the substrate 110 omits the dividing lane 110r (110r', 110r"), the area in which the substrate 110 continuously extends is large, so that the accumulated warpage amount when the substrate 110 is deformed is large. And internal stress increases. In contrast, in the embodiment, since the substrate 110 is separated into a plurality of small substrates 111 by the dividing lane 110r, the base is made. The amount of warpage when the plate 110 is deformed is cut by the dividing lane 110r (110r', 110r"), thereby reducing the overall amount of warpage. Therefore, under the design of the dividing lane 110r (110r', 110r") of the embodiment of the present invention Even if the double-sided structure of the semiconductor package 100 is asymmetrical and/or the substrate 110 is thinner, the accumulated warpage amount can be controlled within a small range or a desired range.

In one example, the dividing lane 110r (110r', 110r") has a width W1, for example, between 8 and 12 micrometers, the number of the sub-substrates 111 is between 4 and 10, and the area of the single sub-substrate 111 The embodiment of the present invention is not limited to the embodiment of the present invention. The width W of the dividing lanes 110r (110r', 110r"), the number of the sub-substrates 111, and the area of the single sub-substrate 111 may be visible to the substrate 110 and/or the wafer 120. Depending on the size and / or thickness. The divided tracks 110r (110r', 110r") may extend in the direction of a straight line, a curved line, or a combination thereof, to obtain the desired number of sub-substrates 111 and the area of the sub-substrate 111.

In the present embodiment, the divided tracks 110r (110r', 110r") extend laterally from one edge side 110s (110s1, 110s2) to the other edge side 110s (110s1, 110s2) along the upper surface 110u of the substrate 110, and The conductive hole 113 extends around the first redistribution circuit layer 1142 (not shown) and/or the second redistribution circuit layer 1152; that is, the extended path of the divided track 110r (110r', 110r") is, for example, a straight line. The curve, or a combination thereof, does not pass through the first redistribution circuit layer 1142 (not shown) and/or the second redistribution circuit layer 1152.

The wafer 120 is disposed on the upper surface 110u of the substrate 110 in an active surface downward direction and electrically connected to the conductive holes 113 of the substrate 110.

Referring to FIG. 2A, a cross-sectional view of a semiconductor package in accordance with another embodiment of the present invention is shown. The semiconductor package 200 includes a substrate 110, a wafer 120, and a primer 130. The 2A diagram is substantially similar to the 1A diagram and will not be described again. The difference is that the dividing track 110r does not bypass the first redistribution wiring layer 1142 and the second redistribution wiring layer 1152, so that any adjacent sub-substrate 111 can pass through the first redistribution wiring layer 1142 and the second. The circuit layer 1152 is redistributed and has a direct electrical connection relationship.

Please refer to FIG. 2B, which shows a top view of FIG. 2A. 2B is roughly similar In Figure 1B, we will not repeat them here. The difference is that the dividing track 110r passes through the second redistribution circuit layer 1152 laterally. Although the dividing track 110r passes laterally through the first redistribution circuit layer 1142 (not shown) and the second redistribution circuit layer 1152, the dividing track 110r only The first redistribution wiring layer 1142 (not shown) and the second redistribution wiring layer 1152 are not divided through the substrate 110, so that the first redistributed wiring layer 1142 (not shown) and/or the second redistributed wiring are retained. The layer 1152 can be exposed from the lower surface 110b of the substrate 110, and the first redistribution circuit layer 1142 and the second redistribution circuit layer 1152 can be directly electrically connected to each other.

Please refer to FIGS. 3A to 3F for a manufacturing process diagram of the semiconductor package 100 of FIG. 1A.

As shown in FIG. 3A, the substrate 110 may be disposed on the carrier 10 by, for example, surface mount technology (SMT). The substrate 110 includes at least one substrate 112, at least one conductive via 113, a first wiring layer 114, a second wiring layer 115, and at least one electrical contact 116. The first circuit layer 114 and the second circuit layer 115 are formed on the lower surface 112b and the upper surface 112u of the substrate 112, respectively. The carrier 10 includes an adhesive layer 11 . The electrical contacts 116 of the substrate 110 are embedded in the adhesive layer 11 to bond the substrate 110 to the carrier 10 .

As shown in FIG. 3B, a patterned photoresist layer 12 may be formed to cover the upper surface 110u of the substrate 110 by a photolithography technique (coating/exposure/etching/developing). The patterned photoresist layer 12 has at least one opening 12a defining a distribution pattern of the subsequently formed dividing lanes 110r (1A and 1B). In this example, the opening 12a laterally bypasses the conductive hole 113 of the substrate 110, the first redistribution wiring layer 1142, the second redistribution wiring layer 1152, and the electrical contact 116.

As shown in FIG. 3C, for example, a chemical etching, such as dry etching, is formed through the opening 12a to form at least one dividing track 110r extending laterally along the upper surface 110u and penetrating through the substrate 110 to form a plurality of sub-substrates separated from each other. 111. Since the electrical contacts 116 of the sub-substrate 111 are buried in the adhesive layer 11, the sub-substrate 111 is not separated from the carrier 10.

As shown in FIG. 3D, the patterned photoresist layer 12 is removed (FIG. 3C), The second redistribution wiring layer 1152 and the second dielectric layer 1153 are exposed.

As shown in FIG. 3E, at least one wafer 120 may be disposed on the substrate 110 using, for example, a surface pasting technique. The wafer 120 is disposed on the substrate 110 with the active surface facing downward, and is electrically connected to the substrate 110 through at least one electrical contact 121.

Then, a primer 130 is formed between the wafer 120 and the substrate 110 to cover the electrical contacts 121 of the wafer 120. Since the dividing lane 110r is exposed from the upper surface 110u of the substrate 110, the primer 130 partially flows into the dividing lane 110r; however, in another example, the entire dividing lane 110r may be filled with the primer 130, that is, the primer 130 may pass through the dividing lane. 110r contacts the adhesive layer 11.

As shown in FIG. 3F, at least one scribe line P may be formed through the second wiring layer 115, the substrate 112, and the first wiring layer 114 by using, for example, a laser or a cutter to form at least one as shown in FIG. 1A. Semiconductor package 100. The dicing street P passes through the partial adhesive layer 11 to completely cut the substrate 110. This cutting method is called full cut.

Please refer to FIG. 4, which illustrates another manufacturing process diagram of the semiconductor package 100 of FIG. 1B. The manufacturing method of this embodiment is substantially similar to the corresponding steps of the manufacturing method of the semiconductor package 100 of FIGS. 3A to 3F, and details are not described herein again. The difference is that before the patterned photoresist layer 12 is formed, at least one opening 1143a is formed in the second dielectric layer 1143 of the substrate 110, and the distribution pattern of the patterned photoresist layer 12 corresponds to the opening 1143a and the subsequently formed dividing channel 110r. The distribution pattern, that is, the distribution of the opening 1143a corresponds to the subsequently formed dividing lane 110r. Thus, when the etching liquid passes through the opening 12a of the patterned photoresist layer 12 to remove the material of the substrate 110, the dividing track 110r can be formed by extending from the opening 12a to the opening 1143a, thereby reducing the second dielectric layer 1143. The amount of material removed to save time required for etching.

In another example, the second dielectric layer 1153 can form an opening similar to the opening 1143a prior to forming the patterned photoresist layer 12 to achieve similar efficacy.

Please refer to FIGS. 5A-5B for a manufacturing process diagram of the semiconductor package 200 of FIG. 2A.

As shown in FIG. 5A, a patterned photoresist layer 12 may be formed to cover the upper surface 110u of the substrate 110 by using a lithography technique. The patterned photoresist layer 12 has at least one opening 12a that defines a distribution pattern of the dividing track 110r (Fig. 2A). In this example, the opening 12a laterally bypasses the conductive hole 113 and the electrical contact 116 of the substrate 110, but may pass through at least one of the first redistribution wiring layer 1142 and the second redistribution wiring layer 1152.

As shown in FIG. 5B, a plurality of sub-substrates 111 separated from each other may be formed by, for example, chemical etching, such as dry etching, forming at least one divided track 110r through the substrate 110 and extending laterally to the edge side of the substrate. In this embodiment, the etching gas that does not remove the metal wiring material is selected, so that the first redistribution wiring layer 1142 and the second redistribution wiring layer 1152 can be retained. In the embodiment, in the etching parameter control, the directionality of the etching gas is reduced, but the isotropic property of the etching gas is increased, so that the etching liquid can be removed from the material under the redistribution wiring layer to the side D1 to form a through-penetration. The dividing track 110r of the substrate 110. That is, by increasing the amount of undercut of the etch, the material underneath the redistribution layer can be removed.

The remaining steps of forming the semiconductor package 200 are similar to the corresponding steps of forming the semiconductor package 100, and thus will not be described again.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Semiconductor package

110‧‧‧Substrate

110a, 1131a‧‧ hole

110r‧‧‧ dividing road

110s1‧‧‧ first edge side

110s2‧‧‧Second edge side

111‧‧‧Sub Substrate

110u, 112u‧‧‧ upper surface

110b, 112b‧‧‧ lower surface

112‧‧‧Substrate

113, 113’, 113”‧‧‧ conductive holes

Conductive mechanism within 1131‧‧

1132‧‧‧External dielectric layer

1133‧‧‧ conduction layer

114‧‧‧First line layer

1141, 1151‧‧‧ first dielectric layer

1142‧‧‧First redistributed circuit layer

1143, 1153‧‧‧ second dielectric layer

115‧‧‧Second circuit layer

1152‧‧‧Second redistribution circuit layer

116, 121‧‧‧ electrical contacts

120‧‧‧ wafer

130‧‧‧Bottom

Claims (20)

A semiconductor package comprising: a substrate having a dividing passage, the dividing passage penetrating the substrate, and extending laterally to an edge side of the substrate, so that the substrate forms a plurality of sub-substrates separated from each other; On the substrate; and a primer formed between the wafer and the substrate. The semiconductor package of claim 1, wherein the substrate has a plurality of conductive holes, the wafer is electrically connected to the conductive holes, and the dividing track extends laterally around the conductive holes to extend to the side of the edge. . The semiconductor package of claim 1, wherein the substrate comprises: a redistribution circuit layer electrically connected to one of the conductive holes of the substrate; wherein the dividing track laterally bypasses the redistribution circuit layer Extend to the side of the edge. The semiconductor package of claim 1, wherein the substrate comprises: a redistribution circuit layer electrically connected to one of the conductive holes of the substrate; wherein the dividing track extends laterally through the redistribution circuit layer To the side of the edge, but the redistributed circuit layer is not divided. The semiconductor package of claim 4, wherein the redistribution wiring layer connects the adjacent sub-substrates. The semiconductor package of claim 1, wherein the substrate comprises: a substrate having an upper surface and a lower surface; a first dielectric layer is formed on the lower surface of the substrate and exposes one of the conductive holes of the substrate; a redistributed wiring layer is formed on the exposed conductive hole; and a second dielectric layer is formed on the substrate A portion of the redistributed circuit layer that is overlaid on the circuit layer and exposed. The semiconductor package of claim 6, wherein the substrate further comprises: a first dielectric layer formed on the upper surface of the substrate and exposing the conductive via of the substrate; Forming the exposed conductive hole; and a second dielectric layer formed on the redistributed wiring layer and exposing a portion of the redistributed wiring layer. The semiconductor package of claim 1, wherein the primer portion is formed on the plurality of divided tracks. The semiconductor package of claim 6, wherein the substrate can be glass, tantalum, metal, metal alloy or polymer. The semiconductor package of claim 1, wherein the substrate has a first edge side and a second edge side, the dividing track extending laterally from the first edge side to the second edge side . The semiconductor package of claim 1, wherein the substrate has an adjacent first edge side and a second edge side, the dividing track extending laterally from the first edge side to the second Edge side. A method of manufacturing a semiconductor package, comprising: disposing a substrate on a carrier; Forming a dividing passage penetrating the substrate and extending laterally to an edge side of the substrate, the substrate is formed into a plurality of sub-substrates separated from each other; a wafer is disposed on the substrate; and a primer is formed on the wafer and the substrate Between; and remove the carrier. The manufacturing method of claim 12, wherein the primer portion is formed on the plurality of divided tracks. The manufacturing method of claim 12, wherein in the step of disposing the substrate in the carrier, the substrate has a plurality of conductive holes; in the step of forming the dividing track, the dividing path is laterally bypassed The conductive holes are electrically connected to the conductive holes in the step of disposing the wafer on the substrate. The manufacturing method of claim 12, wherein a first dielectric layer is formed on a surface of the substrate and exposes one of the conductive holes of the substrate; and a redistributed wiring layer is formed on the exposed conductive hole; A second dielectric layer is formed on the redistribution wiring layer and exposes a portion of the redistribution wiring layer. The manufacturing method of claim 15, further comprising forming a patterned photoresist layer on the second dielectric layer, wherein the patterned pattern of the patterned photoresist layer corresponds to the subsequently formed segment . The manufacturing method of claim 15, wherein the dividing lane laterally bypasses the redistribution wiring layer in the step of forming the dividing lane. The manufacturing method according to claim 15, wherein in the step of forming the dividing lane, the dividing lane passes laterally through the redistribution wiring layer, but the redistribution wiring layer is not divided. The manufacturing method according to claim 18, wherein in the step of forming the dividing track, dry etching is used. The manufacturing method of claim 15, further comprising forming an opening on the second dielectric layer, and the distribution of the opening corresponds to the subsequently formed dividing track.