CN104241175A - Semiconductor device substrate loading device - Google Patents
Semiconductor device substrate loading device Download PDFInfo
- Publication number
- CN104241175A CN104241175A CN201310252006.3A CN201310252006A CN104241175A CN 104241175 A CN104241175 A CN 104241175A CN 201310252006 A CN201310252006 A CN 201310252006A CN 104241175 A CN104241175 A CN 104241175A
- Authority
- CN
- China
- Prior art keywords
- semiconductor device
- device substrates
- casket
- substrate
- backplate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
- H01L21/6735—Closed carriers
- H01L21/67373—Closed carriers characterised by locking systems
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
- H01L21/6735—Closed carriers
- H01L21/67356—Closed carriers specially adapted for containing chips, dies or ICs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
- H01L21/6735—Closed carriers
- H01L21/67386—Closed carriers characterised by the construction of the closed carrier
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The invention provides a semiconductor device substrate loading device. The semiconductor device substrate loading device comprises a semiconductor device substrate, a substrate box and a loading platform, wherein the semiconductor device substrate is provided with a surface to be processed and a surface not to be processed, the substrate box is used for bearing the semiconductor device substrate and provided with a front panel and a back panel opposite to the front panel, an in-box space is formed between the front panel and the back panel, and the loading platform is used for bearing the substrate box. The semiconductor device substrate loading device is characterized in that a substrate tray and springs are arranged in the in-box space, one end of each spring is connected with the substrate tray, the other end of each spring is connected with the back panel, and a magnetic force field is formed between the loading platform and the substrate tray.
Description
Technical field
The present invention relates to a kind of semiconductor device substrates loading attachment, be specifically related to a kind of for the semiconductor device substrates loading attachment at semiconductor device substrates surface electrochemistry plated metal.
Background technology
In recent years, along with chip size is more and more less, integrated level is more and more higher, and computer, communication, automotive electronics and other consumer products it is also proposed higher requirement to ic chip package technology.Chip package require than in the past less, thinner, possess high reliability, multi-functional, low energy consumption and low cost.Traditional Solder Bumps (solder bump) encapsulation technology cannot meet the requirement of Advanced Packaging, copper post bump technology (copper pillar) and silicon through hole technology (through silicon via, TSV) become the large focus of two in Advanced Packaging gradually.
The same with Solder Bumps, copper post projection is also be applied to technology chip package connecting chip and support plate.But compare with Solder Bumps, copper post projection has better performance and lower overall package cost.Can collapse to spherical different in solder reflow process from Solder Bumps, copper post projection can keep its shape, is applicable to less live width, meets the requirement of highly integrated chip encapsulation.And copper has the resistance less than leypewter and the thermal conductivity of Geng Gao, copper post projection has better conductivity and thermal conductivity than Solder Bumps, the heat produced when can reduce energy consumption and the work of chip.Cu electroplating is the appropriate process making copper post projection.Copper post producing lug process is: first deposit one deck inculating crystal layer, then on inculating crystal layer, smear one deck optical cement and form pattern on optical cement, then in pattern, utilizing electrochemical method plated metal copper post, finally removing unnecessary optical cement and obtain copper post projection.
Except traditional plane formula encapsulation technology, advanced laminated type three-dimensional packaging technology was also applied in recent years in IC manufacturing industry.Three-dimensional packaging technology makes in single package body can stacking multiple chip, and interconnect length significantly reduces, and Signal transmissions is faster, and cost is lower; Together chip-stacked by multiple difference in functionality, make single package body realize more function, and size and weight can reduce decades of times.Silicon through hole technology is one of core technology realizing three-dimension packaging.Silicon through hole technology has following potential advantage: 1) connecting length may be as little to the thickness of a chip, can be reduced the conductor length of logic module interconnection by the vertical stack of logic module instead of horizontal spreading greatly; 2) high density high depth becomes possibility than interconnection, and success is realized complicated multichip system on silicon chip, and its physical integration density will be much higher than present multi-chip module (MCM); 3) due to electrical connection nearer between the logic module in Different Plane, RC postpones to be improved greatly.The key process technology that three-dimensional chip heap superimposition interconnecting silicon through holes needs comprises: a) form through hole; B) isolation layer, the deposition of barrier layer and inculating crystal layer; C) copper is filled, and removes and RDL; D) wafer thinning; E) the location calibration of silicon chip/chip, line and cutting.In silicon through hole, deposited copper also needs electrochemical deposition method to realize.
Copper post bump technology has similar requirement with silicon through hole technology to electrochemical deposition equipment.First in copper post bump technology in the height of copper post and silicon through hole the degree of depth of deposited copper all at 30 to 150 microns, be far longer than the deposit thickness required in the copper wiring technique of chip rear end, therefore the deposition rate that electrochemical deposition equipment can reach higher is required, to realize larger productive rate.Usually be applied to copper post bump technology and silicon through hole technical requirement electrochemical deposition equipment to have and be not less than 40 silicon chip productive rate hourly.Next requires that electrochemical deposition equipment can realize good uniformity.For copper post bump technology, usually require that the copper post flatness that in silicon chip, plating is formed is less than 5%, to meet the requirement of subsequent encapsulating process step.And to silicon through hole technology, usually require that in silicon chip, electroplating evenness is less than 2%, to meet the requirement of subsequent planarization technique.And require that electrochemical deposition equipment has alap cost.In order to reduce costs, electrochemical deposition equipment electrochemical deposition cavity requires process multi-disc silicon chip simultaneously, thus reduces number and other corresponding hardware, such as power supplys of electrochemical deposition cavity.
The business-like electrochemical metal depositing device part for chip package is based on chip rear end copper-connection electrochemical deposition equipment development at present, electrochemical deposition cavity single treatment a slice silicon chip, in electrochemical deposition process, silicon chip face level to be dipped in downwards in electroplate liquid and to rotate with certain speed.This kind equipment can realize good uniformity usually, but in electroplate liquid, rotary speed can not be too high due to silicon chip, otherwise electroplate liquid can be caused to splash, and therefore deposition rate is usually lower, be about 1 micron per hour.In order to reach the requirement of productive rate, need the quantity of electrochemical deposition cavity in increase equipment, therefore this kind equipment also has higher cost usually.Separately have partial electro chemical metal depositing device to adopt silicon chip to be dipped vertically into the design of electroplate liquid, an electrochemical deposition cavity can process 2 silicon chips simultaneously, reduces cost.The present electrochemical metal depositing device for Solder Bumps, copper post bump technology and silicon through hole technology is substantially silicon chip and is dipped vertically into electroplate liquid.
This type of electrochemical metal depositing device mainly comprises general frame, manipulator, plating chamber, such cleaning chamber, the main modular such as liquid transfer system, silicon chip loading device and parts.Existing silicon chip loading device is two parts separation design.Part silicon chip loading device is that silicon chip is pressed in a wherein part for silicon chip loading device by the active force utilizing back air bag to produce, and forms electrical contact and sealing, in process treatment process, needs constantly to provide the gas of certain pressure to maintain sealing to air bag.Another part is that two parts of silicon chip loading device are fixed together by the active force directly utilizing mechanical movement to produce, described mechanical movement passes through cylinder usually, motor or other mechanical device realize, and need to mechanical device air feed or power to maintain sealing in process treatment process.Owing to needing extra external equipment air feed or power supply, existing silicon chip loading device all can only keep static in technical process, cannot move on a large scale, thus causes the uniformity of plated metal poor.And two parts separation design makes silicon chip loading device because the problem of artificial misoperation or hardware self is opened, silicon chip loading device may be made to be destroyed, reduce the stability of device in electroplating process.
Summary of the invention
The invention provides semiconductor device substrate loading attachment, described semiconductor device substrates loading attachment has: semiconductor device substrates, and described semiconductor device substrates has to be processed and non-to be processed; Substrate casket, described substrate casket is in order to carry described semiconductor device substrates, and described substrate casket has front plate and backplate, and described front plate is relative with backplate and put, and forms space in casket between described front plate and backplate; Loading stage, described loading stage is in order to carry described substrate casket.It is characterized in that: in described casket, space has the spring that substrate pallet is connected with described substrate pallet with one end; The described spring other end is connected with described backplate; Between described loading stage and described substrate pallet, there is field of magnetic forece.
Semiconductor device substrates loading attachment provided by the invention is in opening when utilizing magneticaction to make described substrate casket only on described loading stage, in the process that described semiconductor device substrates moves with PROCESS FOR TREATMENT, all remain on sealing state, improve the stability of device.And utilize spring to make described substrate box become sealing, do not need outside air feed or power supply, described substrate casket can be moved on a large scale in electroplating process, such as, rotate around anode, improve the uniformity of plating.
Accompanying drawing explanation
Fig. 1 is a schematic diagram of the substrate casket that semiconductor device substrates loading attachment provided by the invention has;
Fig. 2 is another schematic diagram of the substrate casket that semiconductor device substrates loading attachment provided by the invention has;
Fig. 3 is the profile of the substrate casket that semiconductor device substrates loading attachment provided by the invention has;
Fig. 4 a is the schematic diagram of the conductive unit that semiconductor device substrates loading attachment provided by the invention has;
Fig. 4 b is the partial schematic diagram of the conductive unit that semiconductor device substrates loading attachment provided by the invention has;
Fig. 5 is the schematic diagram of semiconductor device substrates loading attachment provided by the invention;
Fig. 6 is another schematic diagram of the substrate casket that semiconductor device substrates loading attachment provided by the invention has;
Fig. 7 is another schematic diagram of the substrate casket that semiconductor device substrates loading attachment provided by the invention has;
Fig. 8 is a kind of schematic diagram utilizing the method for semiconductor device substrates loading attachment provided by the invention.
Specific implementation method
Describe the present invention in detail below in conjunction with accompanying drawing and specific embodiment, be used for explaining the present invention in this illustrative examples of the present invention and explanation, but not as a limitation of the invention.
As depicted in figs. 1 and 2, semiconductor device substrates loading attachment provided by the invention has substrate casket 101, and described substrate casket is used for loading semiconductor device substrate 110, and described semiconductor device substrates 110 has to be processed and non-to be processed.To be processed of described semiconductor device substrates 110 have metal film coated, for forming electrical contact with external power in electroplating process.Described substrate casket 101 has front plate and backplate, and described front plate is relative with backplate and put, and forms space in casket between described front plate and backplate.Described front plate has with described backplate edge the vertical sidewall be connected, and described vertical sidewall has opening, and described opening size is greater than the size of described semiconductor device substrates 110.Described substrate casket 101 front plate there is a void region, exposes to be processed of described semiconductor device substrates 110.The material of described substrate casket is plastics or pottery.There is a substrate pallet 102 in space in described casket, in described substrate bracket tray bottom, there is the material 103 that contains iron.The material 103 of described iron content also can be positioned at the inside of described substrate pallet 102.In described casket, also there is in space at least one semiconductor device substrates strut 104.Described semiconductor device substrates strut 104 one end is fixed on described backplate, and described semiconductor device substrates strut 104 length is less than the difference of the thickness of spacing and described semiconductor device substrates 110 between described front plate and described and backplate.Described substrate pallet 102 has the hole unit corresponding to described semiconductor device substrates strut 104, passes for described semiconductor device substrates strut.In described casket, space also has at least one spring 105, and the drift of described spring 105 is greater than spacing sum between the thickness of described semiconductor device substrates 110 and described front plate and described and backplate.Described spring 105 is through described semiconductor device substrates strut 104, and one end is connected with described substrate pallet 102, and the other end is connected with the backplate of described substrate casket 101.
As shown in Figure 3, also have a hermetic unit 106 in described substrate casket 101 front plate, described hermetic unit 106 is for be processed of semiconductor device substrates described in hermetic unit 110.Inner at described hermetic unit 106, described substrate casket 101 front plate also has a conductive unit 107.Between described conductive unit 107 and described substrate casket 101 front plate, have a becket 108, described conductive unit 107 contacts with described becket 108 with to be processed of described semiconductor device substrates 110 simultaneously.Described becket 108 is connected with at least one electrode unit 109.Described electrode unit 109 one end is connected with described becket 108, and the other end is exposed to outside described substrate casket 101, is connected with the negative electrode of external power, makes to be processed of described semiconductor device substrates 110 and the conducting of described external power cathodic electricity.Described hermetic unit 106 is formed with described semiconductor device substrates 110 to be deposited EDGE CONTACT and seals, and prevents liquid and described semiconductor device substrates 110 rear-face contact.Described conductive unit 107 also contacts with to be deposited of described semiconductor device substrates 110 in described hermetic unit 106 simultaneously, and formation conducts.According to the shape of described semiconductor device substrates 110, the shape of the shape of described substrate casket 101 front plate void region and described hermetic unit 106, conductive unit 107 is the one in circular, square, rectangle.Described hermetic unit 106 is less than 3mm apart from described semiconductor device substrates 110 edge.Described hermetic unit 106 is the one in O type circle, double-deck O type circle, lip seal.
Fig. 4 a is the schematic diagram of the conductive unit 107 that described semiconductor device substrates loading attachment has, and Fig. 4 b is the partial schematic diagram of the conductive unit 107 that described semiconductor device substrates loading attachment has.Described conductive unit 107 has a ring-like polymer elastomer 401.Described macromolecular elastomer 401 forms flexible contact with to be deposited of described semiconductor device substrates 110, reduces the pressure that to be deposited of described semiconductor device substrates 110 is subject to, prevents described semiconductor device substrates 110 damaged.As shown in Figure 4 b, described macromolecular elastomer 401 is wound with conductive wire 402, described conductive wire is compliant conductive silk.Described conductive wire 402 contacts with described becket 108 with to be deposited of described semiconductor device substrates 110, and formation conducts.Described conductive wire 402 is the one in wire, carbon fiber, conductive polymer subbundle.
Fig. 5 is the schematic diagram of semiconductor device substrates loading attachment provided by the invention, and described semiconductor device substrates loading attachment also has loading stage 501.Described loading stage 501 is for carrying described substrate casket 101.Described loading stage 501 also has electromagnet 502 and a field of magnetic forece switch 503.When described field of magnetic forece switch 503 is opened, between the described iron-bearing materials 103 that described in described electromagnet 502 and described substrate casket 101, substrate pallet 102 has, produce attraction.Coupled described spring 105 oppressed by described substrate pallet 102, close to described back plate, described semiconductor device substrates strut 104 passes described hole unit, until described semiconductor device substrates strut 104 top is higher than described substrate pallet 102.Now described substrate pallet 102 arrives one from the position close to described backplate, and described substrate casket 101 is in transmission state.Described semiconductor device substrates 110 can be conveyed into described substrate casket 101 by manipulator, is positioned on described semiconductor device substrates strut 104, as described in Figure 6.When described field of magnetic forece switch 503 cuts out, attraction between the described iron-bearing materials 103 that described in described electromagnet 502 and described substrate casket 101, substrate pallet 102 has fades away, described spring 105 flicks, described substrate pallet 102 jack-up is risen, when described substrate pallet 102 is higher than described semiconductor device substrates strut 104 top, non-to be processed of described semiconductor device substrates 110 is separated with described semiconductor device substrates strut 104, non-to be processed of described semiconductor device substrates 110 contacts with described substrate pallet 102, described semiconductor device substrates 110 rises with described substrate pallet 102, until described semiconductor device substrates 110 generation machined surface and described hermetic unit 106 close contact.Now described substrate pallet 102 arrives one from the position close to described front plate, and described substrate casket 101 is in sealing state, as shown in Figure 7.
Utilize a method for semiconductor device substrates loading attachment provided by the invention, comprising:
Step one, is flat on described substrate casket 101 on described loading stage 501, states loading stage 501 described in the contact of its backplate;
Step 2, start described field of magnetic forece switch 503, described loading stage 501 attracts described substrate pallet 102, coupled described spring 105 oppressed by described substrate pallet 102, close to described back plate, described semiconductor device substrates strut 104 passes described hole unit, until described semiconductor device substrates strut 104 top is higher than described substrate pallet 102; Now described substrate pallet 102 arrives one from the position close to described backplate;
Step 3, by described opening, imports described semiconductor device substrates 110 in described casket space;
Step 4, places described semiconductor device substrates 110, makes described non-to be processed described semiconductor device substrates strut 104 top of contact;
Step 5, progressively close described field of magnetic forece switch 503, between described loading stage 501 and described substrate pallet 102, magnetic force progressively disappears, described spring 105 flicks, described substrate pallet 102 jack-up is risen, when described substrate pallet 102 is higher than described semiconductor device substrates strut 104 top, described non-to be processed is separated with described semiconductor device substrates strut 104, non-to be processed of described semiconductor device substrates 110 contacts with described substrate pallet 102, described semiconductor device substrates 110 rises with described substrate pallet 102, until to be processed of described semiconductor device substrates 110 and described hermetic unit 106 close contact.Now described substrate pallet 102 arrives one from the position close to described front plate;
Step 6, loading action completes, and is taken away by described substrate casket 101 from described loading stage 501.
Step 7, is flat on described substrate casket 101 on described loading stage 501, states loading stage 501 described in the contact of its backplate;
Step 8, start described field of magnetic forece switch 503, described loading stage 501 attracts described substrate pallet 102, coupled described spring 105 oppressed by described substrate pallet 102, close to described back plate, described semiconductor device substrates 110 declines with described substrate pallet 102, described semiconductor device substrates strut 104 is through described hole unit, when described strut 104 top is higher than described substrate pallet 102, non-to be processed of described semiconductor device substrates 110 is separated with described substrate pallet 102, described semiconductor device substrates 110 non-to be processed and described semiconductor device substrates strut 104 tip contact, now described substrate pallet 102 arrives one from the position close to described backplate,
Step 9, by described opening, spreads out of space in described casket by described semiconductor device substrates 110;
Step 10, uninstall action completes, and closes described magnetic field switching 503.
Semiconductor device substrates loading attachment provided by the invention not only can be applied to electrochemical deposition of metal technique.Semiconductor device substrates loading attachment provided by the invention may be used for loading semiconductor, solar energy, LED semiconductor device substrates, includes but not limited to silicon chip, sapphire semiconductor device substrates, sic semiconductor device substrate, gallium arsenide semiconductor device substrate.Semiconductor device substrates loading attachment provided by the invention also may be used for the wet processing in any semiconductor, solar energy, LED production, includes but not limited to plating, chemical plating, cleaning, wet etching and electropolishing.
The scheme provided the embodiment of the present invention has above carried out detailed explanation, applies specific case and set forth principle of the present invention and execution mode in the present invention, and above embodiment illustrates and is only applicable to the principle helping to understand the embodiment of the present invention.For one of ordinary skill in the art, according to the embodiment of the present invention, all can change to some extent in specific embodiments and applications, do not departing from the basis of present inventive concept, this description should not be construed as limitation of the present invention.
Claims (10)
1. semiconductor device substrate loading attachment, described semiconductor device substrates loading attachment has:
Semiconductor device substrates, described semiconductor device substrates has to be processed and non-to be processed;
Substrate casket, described substrate casket is in order to carry described semiconductor device substrates, and described substrate casket has front plate and backplate;
Described front plate is relative with backplate and put, and forms space in casket between described front plate and backplate;
Loading stage, described loading stage is in order to carry described substrate casket;
It is characterized in that:
In described casket, space has the spring that substrate pallet is connected with described substrate pallet with one end;
The described spring other end is connected with described backplate;
Between described loading stage and described substrate pallet, there is field of magnetic forece.
2. device according to claim 1, is characterized in that, described device also has field of magnetic forece switch, in order to open and close described field of magnetic forece.
3. device according to claim 1, is characterized in that, has electromagnet in described loading stage, and described substrate pallet has iron.
4. device according to claim 1, is characterized in that, described spring free length is greater than spacing sum between the thickness of described semiconductor device substrates and described front plate and described and backplate.
5. device according to claim 1, it is characterized in that, in described casket, space has semiconductor device substrates strut, described semiconductor device substrates strut one end is fixed on described backplate, and described strut length is less than the difference of the thickness of spacing and described semiconductor device substrates between described front plate and described and backplate; Described substrate pallet has the hole unit corresponding to described semiconductor device substrates strut, passes for described semiconductor device substrates strut.
6. device according to claim 1, is characterized in that, described front plate has an openwork part, described in described openwork part expose portion to be processed; Described front plate has hermetic unit, described in described hermetic unit hermetic unit to be processed.
7. device according to claim 6, it is characterized in that, described front plate also has a conductive unit, and described conductive unit has conductive wire and macromolecular elastomer, described conductive wire is wrapped on described macromolecular elastomer, described conductive wire and an external power conducting.
8. device according to claim 1, is characterized in that, described mask to be processed has metal film coated.
9. device according to claim 1, it is characterized in that, described front plate is parallel with described backplate, and described front plate has with described backplate edge the vertical sidewall be connected, described vertical sidewall has opening, and described opening size is greater than described semiconductor device substrates size.
10. the method utilizing the semiconductor device substrates loading attachment according to any one of claim 1 to 9 to load described semiconductor device substrates and unload, comprising:
Described substrate casket is flat on described loading stage, described in the contact of its backplate, states loading stage;
Start described field of magnetic forece switch, described loading stage attracts described substrate pallet, coupled described spring oppressed by described substrate pallet, close to described back plate, described semiconductor device substrates strut passes described hole unit, until described semiconductor device substrates strut top is higher than described substrate pallet; Now described substrate pallet arrives one from the position close to described backplate;
By described opening, import described semiconductor device substrates in described casket space;
Place described semiconductor device substrates, make described non-to be processed the described semiconductor device substrates strut top of contact;
Progressively close described field of magnetic forece switch, between described loading stage and described substrate pallet, magnetic force progressively disappears, described spring flicks, described substrate pallet jack-up is risen, when described substrate pallet is higher than described semiconductor device substrates strut top, described non-to be processed is separated with described semiconductor device substrates strut, described non-to be processed contacts with described substrate pallet, described semiconductor device substrates rises with described substrate pallet, until described machined surface and described hermetic unit close contact.Now described substrate pallet arrives one from the position close to described front plate;
Loading action completes, and is taken away by described substrate casket from described loading stage.
Described substrate casket is flat on described loading stage, described in the contact of its backplate, states loading stage;
Start described field of magnetic forece switch, described loading stage attracts described substrate pallet, coupled described spring oppressed by described substrate pallet, close to described back plate, described semiconductor device substrates declines with described substrate pallet, described semiconductor device substrates strut is through described hole unit, when described strut top is higher than described substrate pallet, described non-to be processed is separated with described substrate pallet, described non-to be processed and described semiconductor device substrates strut tip contact, now described substrate pallet arrives one from the position close to described backplate,
By described opening, described semiconductor device substrates is spread out of space in described casket;
Uninstall action completes, and closes described magnetic field switching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310252006.3A CN104241175A (en) | 2013-06-24 | 2013-06-24 | Semiconductor device substrate loading device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310252006.3A CN104241175A (en) | 2013-06-24 | 2013-06-24 | Semiconductor device substrate loading device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104241175A true CN104241175A (en) | 2014-12-24 |
Family
ID=52229017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310252006.3A Pending CN104241175A (en) | 2013-06-24 | 2013-06-24 | Semiconductor device substrate loading device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104241175A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117448927A (en) * | 2023-12-26 | 2024-01-26 | 苏州智程半导体科技股份有限公司 | Anti-fatigue electric ring for wafer electroplating |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0745168A (en) * | 1993-07-27 | 1995-02-14 | Nec Corp | Excessive input preventive circuit |
| US20030217694A1 (en) * | 2002-05-27 | 2003-11-27 | Canon Kabushiki Kaisha | Supporting apparatus having a plurality of magnets that generate a floating force and method, stage apparatus, and exposure apparatus |
| CN2758971Y (en) * | 2004-09-14 | 2006-02-15 | 微芯科技有限公司 | Wafer bearing device for wafer etching equipment |
| JP2006303138A (en) * | 2005-04-20 | 2006-11-02 | Seiko Epson Corp | Apparatus and method for manufacturing semiconductor device |
-
2013
- 2013-06-24 CN CN201310252006.3A patent/CN104241175A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0745168A (en) * | 1993-07-27 | 1995-02-14 | Nec Corp | Excessive input preventive circuit |
| US20030217694A1 (en) * | 2002-05-27 | 2003-11-27 | Canon Kabushiki Kaisha | Supporting apparatus having a plurality of magnets that generate a floating force and method, stage apparatus, and exposure apparatus |
| CN2758971Y (en) * | 2004-09-14 | 2006-02-15 | 微芯科技有限公司 | Wafer bearing device for wafer etching equipment |
| JP2006303138A (en) * | 2005-04-20 | 2006-11-02 | Seiko Epson Corp | Apparatus and method for manufacturing semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117448927A (en) * | 2023-12-26 | 2024-01-26 | 苏州智程半导体科技股份有限公司 | Anti-fatigue electric ring for wafer electroplating |
| CN117448927B (en) * | 2023-12-26 | 2024-03-15 | 苏州智程半导体科技股份有限公司 | Anti-fatigue electric ring for wafer electroplating |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101222755B1 (en) | Package on package using a bump-less build up layer(bbul) package | |
| US20140217593A1 (en) | Electrical Connecting Element and Method for Manufacturing the Same | |
| CN107924878A (en) | Structures and methods for low temperature engagement | |
| CN102237281A (en) | Semiconductor device and manufacturing method thereof | |
| JP2012074672A (en) | Chip stacked structure and method of fabricating the same | |
| CN102263192A (en) | Light-emitting diode submount, light-emitting diode package, and fabrication method thereof | |
| CN106298634A (en) | The method for filling through hole of a kind of oriented growth nano twin crystal copper and application thereof | |
| CN110323197A (en) | Structure and preparation method thereof for ultra high density chip FOSiP encapsulation | |
| CN103985695A (en) | Fan-out type packaging structure and manufacturing process thereof | |
| CN103474365A (en) | Method for packaging semiconductor | |
| CN102623444B (en) | Integrated circuit device and method for preparing the same | |
| Tian et al. | Copper pulse-reverse current electrodeposition to fill blind vias for 3-D TSV integration | |
| CN104241175A (en) | Semiconductor device substrate loading device | |
| CN112768364A (en) | Board-level three-dimensional chip packaging structure and preparation method thereof | |
| US10213986B2 (en) | Electric connection and method of manufacturing the same | |
| CN104233422A (en) | Device for depositing metal on substrate | |
| CN102760665A (en) | Semiconductor package structure and manufacturing method thereof | |
| Cao et al. | Silicon-based system in packaging for light emitting diodes | |
| WO2018098650A1 (en) | Integrated circuit packaging structure and method | |
| CN113948508A (en) | Chip module high-density interconnection method based on silicon carrier plate | |
| CN114743945A (en) | Advanced package structure with Si and organic interposer and method of making the same | |
| CN102651325B (en) | Package method of two-dimensionally distributed coreless adapter plate | |
| CN103474363B (en) | A kind of packaging technology based on organic substrate technology and encapsulating structure | |
| CN214588747U (en) | Board-level three-dimensional chip packaging structure | |
| US20200185331A1 (en) | Electronic system comprising a lower redistribution layer and method for manufacturing such an electronic system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20141224 |