CN104239632A - Method for reducing VGA (Video Graphics Array) wiring crosstalk influence - Google Patents
Method for reducing VGA (Video Graphics Array) wiring crosstalk influence Download PDFInfo
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- CN104239632A CN104239632A CN201410460392.XA CN201410460392A CN104239632A CN 104239632 A CN104239632 A CN 104239632A CN 201410460392 A CN201410460392 A CN 201410460392A CN 104239632 A CN104239632 A CN 104239632A
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Abstract
The invention provides a method for reducing VGA (Video Graphics Array) wiring crosstalk influences and belongs to the technical field of electronic information. The method is characterized in that VGA signal grounding treatment and VGA signal adjacent reference plane layer slot opening are simultaneously conducted on a mother board; GNDNET shielding lines are added among RGB three signal lines on the same layer on the mother board to reduce the influences of high-speed lines and self-coupling; a long-distance slot is formed on a GND plane adjacent to the RGB three signal lines to cut off a noise propagation path on the GND plane. By introducing the method in sever product design, according to board proofing testing and verification, the VGA signal quality is better improved, the noise energy is greatly reduced, the signal quality is effectively improved and the design quality and the market competitiveness of the product are improved.
Description
Technical field
The present invention relates to electronic information technical field, specifically a kind of method reducing VGA cabling cross talk effects signal.
Background technology
General, when crosstalk refers to that signal transmits in transmission channel, because of electromagnetic coupled on the impact that adjacent transmission lines produces.
The signal (as step signal) of change is propagated along transmission line by A to B, and transmission line C to D can produce coupled signal.When change signal recuperation to galvanic current at ordinary times, coupled signal is not also just present in.Therefore crosstalk occurs over just in the middle of the process of signal saltus step, and signal intensity must be faster, and the crosstalk of generation is also larger.Crosstalk can be divided into capacitive coupling crosstalk (due to the change in voltage of interference source, disturbed object causes induction current thus causes electromagnetic interference (EMI)) and inductive coupled crosstalk (due to the curent change of interference source, disturbed object causes induced voltage thus causes electromagnetic interference (EMI)).
In server product exploitation, for meeting multi-functional high configuration requirement, signal lead speed goes is fast, and Power consumes place also to be increased.Meanwhile, for reducing product development cost, when designing, if under the requirement of system signal cabling can be met, for reducing pcb board size as far as possible.Like this, the lifting of signal speed, increasing and the reduction reducing the signal lead space of bringing of PCB size of Power supply centre, will cause undesired signal energy significantly to promote.VGA cabling on mainboard is belonged to by the more sensitive simulating signal of signal disturbing, when signal is subject to noise, there will be water ripples on a display screen, have influence on signal display quality.
Summary of the invention
Technical assignment of the present invention solves the deficiencies in the prior art, provides a kind of method reducing VGA cabling cross talk effects signal.
Technical scheme of the present invention realizes in the following manner, the method for this kind of VGA of minimizing cabling cross talk effects signal: process on mainboard, with carrying out VGA signal bag simultaneously and slot to VGA signal neighboring reference plane layer slot.
Mainboard increases GND NET shielding line between RGB tri-signal wire in same aspect, reduces the impact of high-speed line and self coupling; And simultaneously with RGB tri-signal wire adjacent GND plane on be a long distance Slot and slot, the travel path of noise in cut-out GND plane.
Mainboard shields VGA tri-signal line GND NET with wrapping, the interference noise be used in splitter section GND plane, reduce other simultaneously and close on high-speed line or the signal wire of VGA own with the crosstalk between layer.
In GND reference planes adjacent with RGB tri-signal wire, do a long distance slot fluting, cut off PWM power supply signal to the noise transmission path that adjacent GND reference planes produce.
Pass through the Slot fluting in GND plane when PWM power unit plane, cause part interference noise path not cut off, then change Slot slotting position, guarantee that PWM power unit plane does not cross over Slot slotting position.
If PWM power plane has crossed slot fluting, signal noise inhibition has decreased; When PWM power plane does not cross slot fluting, namely slot as separation with this slot, VGA signal is what slot, and the PWM power plane on the corresponding upper strata of GND fluting plane, completely at the another side of groove, optimizes signal noise rejection ability more.
The beneficial effect that the present invention is compared with prior art produced is:
The method of this kind of VGA of minimizing cabling cross talk effects signal is the transmission quality promoting VGA signal, there is provided a kind of cabling design rule of the VGA of improvement signal quality: namely in same aspect, increase GND NET shielding line between RGB tri-signal wire, reduce the impact of high-speed line and self coupling, in adjacent GND reference planes, do a long distance slot fluting, cut off PWM power supply signal to after adjacent GND reference planes produce noise, the travel path of its noise.
Preferably: if PWM power plane has crossed slot fluting, that signal noise inhibition will decrease, as improved simulator and noise value for the first time for-9.9 mV ~+10.5 mV, slot fluting is not crossed when making PWM power plane, namely slot as separation with this, VGA signal is on one side of fluting, and the PWM power plane on the corresponding upper strata of GND fluting plane is completely at the another side of groove, and such design more can optimize the ability that signal noise suppresses.If above-mentioned Optimal improvements post-layout simulation results exhibit value is-0.5 mV ~ 0.5 mV, from emulated data, signal disturbing noise suppression effect has than non-Optimal improvements mode (with comprising signal bag with neighboring reference layer mode of grooving simultaneously) obviously to be improved preferably.
By importing in server product design, economy-combat board test is verified, VGA signal quality has good improvement.Therefore, this design will be used widely in subsequent product is designed and developed.
The method design of this kind of VGA of minimizing cabling cross talk effects signal is reasonable, structure is simple, safe and reliable, easy to use, be easy to safeguard, have good value for applications.
Embodiment
Below the method for a kind of VGA of minimizing cabling cross talk effects signal of the present invention is described in detail below.
The method of a kind of VGA of minimizing cabling cross talk effects signal of the present invention is: when server product development and testing VGA Presentation Function, find screen shows water ripples, signal elevating time is found by measuring VGA signal wire RGB net, by rgb signal line is forced to drag down, find that its signal wire net power source noise is comparatively large, therefore, the preliminary suspection signal wire rise time is excessively slow, be the interference due to power supply noise, what cause signal energy weakly causes.
Observe VGA signal layout figure, find the GND plane of VGA signal with reference to layer3, and side has PWM power supply to be positioned in Layer1 & 2 plane nearby, thus this PWM power supply is also with reference to layer3 GND plane.Like this, PWM power supply will produce high frequency noise in GND plane, and go to affect VGA signal quality by GND plane propagation.
Therefore, for above-mentioned situation, utilize the lower analysis verification of the progressive work of emulation, observe its simulation waveform, passable from waveform, the noise amplitude that PWM power supply produces on VGA signal wire is changed to-20.8mV ~ 20.9mV, and noise intensity is comparatively large, thus progressive to demonstrate the interference of PWM power supply noise be affect VGA signal quality principal element.
For above-mentioned situation, its settling mode mainly: cut off the undesired signal path of propagating in GND plane.First shield with wrapping VGA tri-signal line GND NET, this mode can not only interference noise in splitter section GND plane, can reduce other simultaneously and close on high-speed line or the signal wire of VGA own with the crosstalk between layer.Meanwhile, the GND plane of layer3 is done the Slot fluting that a distance is longer, cuts off the travel path of noise in GND plane.
By above-mentioned improved procedure, carry out simulation analysis, its simulation waveform: the noise voltage on VGA signal wire drops to-9.9mV ~+10.5mV, compared with original design, power supply noise range of decrease half.
Optimal improvements scheme:
By the analysis of above-mentioned improvement project, pass through the Slot fluting in layer3 GND plane because of PWM power unit plane, cause part interference noise path not cut off.Therefore, change Slot slotting position, guarantee that PWM plane does not cross over its position, shown in its prioritization scheme and simulation waveform: its emulation voltage noise value is-0.5 mV ~ 0.5 mV, and noise energy significantly reduces, and effectively improves signal quality.The method is imported correcting design, its actual measurement VGA signal waveform of drawing a design, signal elevating time has clear improvement shortening.
As a rule, process with carrying out separately VGA signal bag or all can be optimized VGA signal neighboring reference plane layer grooving slot.But the direction that the degree of signal quality improvement is present case mainly to be paid close attention to, this can improve board correcting success ratio further.Therefore, present case, in conjunction with above-mentioned improved procedure, summarizes following VGA signal later stage PCB design Optimal improvements rule by simulation analysis and the checking that re-packs, as follows:
During 1.PCB design, VGA is processed with wrapping and imports design with neighboring reference plane grooving scheme simultaneously, by the combination of two schemes, can improve and reduce PWM power supply signal to the interference of VGA simulating signal.As in above-mentioned first improvement project, signal simulation noise voltage is-9.9 mV ~+10.5 mV.
2. only consider signal bag ground and neighboring reference plane grooving process, may not necessarily the optimum ability improving signal suppressing noise.By finding in this routine Optimal improvements scheme, although neighboring reference plane carries out grooving process, if PWM power plane has crossed slot fluting, that signal noise inhibition will decrease, as improved simulator and noise value for the first time for-9.9 mV ~+10.5 mV, slot fluting is not crossed when making PWM power plane, namely slot as separation with this, VGA signal is on one side of fluting, the PWM power plane on the corresponding upper strata of GND fluting plane is completely at the another side of groove, and such design more can optimize the ability that signal noise suppresses.If above-mentioned Optimal improvements post-layout simulation results exhibit value is-0.5 mV ~ 0.5 mV, from emulated data, signal disturbing noise suppression effect has than non-Optimal improvements mode (with comprising signal bag with neighboring reference layer mode of grooving simultaneously) obviously to be improved preferably.
Conclusion: by simulating, verifying and the test that re-packs, finds that the technical program effectively improves the design of VGA signal quality, improves designing quality and the market competitiveness of product.
Claims (6)
1. reduce a method for VGA cabling cross talk effects signal, it is characterized in that: process on mainboard, with carrying out VGA signal bag simultaneously and VGA signal neighboring reference plane layer slot is slotted.
2. a kind of method reducing VGA cabling cross talk effects signal according to claim 1, is characterized in that: mainboard increases GND NET shielding line between RGB tri-signal wire in same aspect, reduces the impact of high-speed line and self coupling; And simultaneously with RGB tri-signal wire adjacent GND plane on be a long distance Slot and slot, the travel path of noise in cut-out GND plane.
3. a kind of method reducing VGA cabling cross talk effects signal according to claim 1, it is characterized in that mainboard shields VGA tri-signal line GND NET with wrapping, the interference noise be used in splitter section GND plane, reduces other simultaneously and closes on high-speed line or the signal wire of VGA own with the crosstalk between layer.
4. a kind of method reducing VGA cabling cross talk effects signal according to claim 1, it is characterized in that in GND reference planes adjacent with RGB tri-signal wire, do a long distance slot fluting, cut off PWM power supply signal to the noise transmission path that adjacent GND reference planes produce.
5. a kind of method reducing VGA cabling cross talk effects signal according to claim 4, it is characterized in that the Slot fluting passed through when PWM power unit plane in GND plane, part interference noise path is caused not cut off, then change Slot slotting position, guarantee that PWM power unit plane does not cross over Slot slotting position.
6. a kind of method reducing VGA cabling cross talk effects signal according to claim 4, if it is characterized in that, PWM power plane has crossed slot fluting, and signal noise inhibition decreases; When PWM power plane does not cross slot fluting, namely slot as separation with this slot, VGA signal is what slot, and the PWM power plane on the corresponding upper strata of GND fluting plane, completely at the another side of groove, optimizes signal noise rejection ability more.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107766634A (en) * | 2017-10-12 | 2018-03-06 | 郑州云海信息技术有限公司 | A kind of optimization BGA power distributions improve the method and chip of high speed signaling quality |
| CN111221492A (en) * | 2020-01-13 | 2020-06-02 | 山东超越数控电子股份有限公司 | Backboard bus type multi-unit server VGA display design device and design method |
| CN111953329A (en) * | 2020-07-28 | 2020-11-17 | 中科芯集成电路有限公司 | PCB Layout design method for reducing false triggering of touch spring key |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080019633A1 (en) * | 2003-09-24 | 2008-01-24 | Cohen Guy M | Apparatus and Methods for Integrally Packaging Optoelectronic Devices, IC Chips and Optical Transmission Lines |
| CN101398517A (en) * | 2008-09-12 | 2009-04-01 | 武汉电信器件有限公司 | Single fiber three-way photoelectric module electric cross talk restraining method and structure thereof |
-
2014
- 2014-09-11 CN CN201410460392.XA patent/CN104239632B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080019633A1 (en) * | 2003-09-24 | 2008-01-24 | Cohen Guy M | Apparatus and Methods for Integrally Packaging Optoelectronic Devices, IC Chips and Optical Transmission Lines |
| CN101398517A (en) * | 2008-09-12 | 2009-04-01 | 武汉电信器件有限公司 | Single fiber three-way photoelectric module electric cross talk restraining method and structure thereof |
Non-Patent Citations (2)
| Title |
|---|
| 李小荣: "高速数模混合电路信号完整性分析与PCB设计", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
| 潘宇倩: "电磁干扰的产生及PCB设计中的抑制方案", 《航天器工程》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107766634A (en) * | 2017-10-12 | 2018-03-06 | 郑州云海信息技术有限公司 | A kind of optimization BGA power distributions improve the method and chip of high speed signaling quality |
| CN111221492A (en) * | 2020-01-13 | 2020-06-02 | 山东超越数控电子股份有限公司 | Backboard bus type multi-unit server VGA display design device and design method |
| CN111953329A (en) * | 2020-07-28 | 2020-11-17 | 中科芯集成电路有限公司 | PCB Layout design method for reducing false triggering of touch spring key |
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