CN104217995A - Production method of array substrate and array substrate produced by production method - Google Patents
Production method of array substrate and array substrate produced by production method Download PDFInfo
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- CN104217995A CN104217995A CN201410464908.8A CN201410464908A CN104217995A CN 104217995 A CN104217995 A CN 104217995A CN 201410464908 A CN201410464908 A CN 201410464908A CN 104217995 A CN104217995 A CN 104217995A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Abstract
The invention discloses a production method of an array substrate and the array substrate produced by the production method, relates to technologies of display devices and solves the problems that liquid crystal control is disturbed and display effects are affected due to static electricity which is prone to occur when spacers adhere to the array substrates. The production method of the array substrate includes that (1) a gate electrode is formed on a substrate; (2) a gate insulation layer, an active layer, a source electrode and a drain electrode are sequentially formed on the gate electrode; (3) passivation layers are formed on the source electrode and the drain electrode, and via holes are formed in corresponding positions; (4) conductive material layers and first photoresist layers are sequentially formed on the passivation layers; (5) the first photoresist layers are subjected to exposure and developing, the spacers are formed in non-pixel areas, and meanwhile, first patterning photoresist layers are formed in pixel areas; (6) the conductive material layers are subjected to etching along the first patterning photoresist layers to form pixel electrodes; (7) the substrate is subjected to exposure and developing, and the first patterning photoresist layers are removed. The production method of the array substrate and the array substrate produced by the production method are mainly used for production of display devices.
Description
Technical field
The present invention relates to display device technology field, particularly relate to a kind of manufacture method of array base palte and apply its array base palte manufactured.
Background technology
TFT-LCD (Thin Film Transistor-Liquid Crystal Display, Thin Film Transistor-LCD) there is the advantages such as high-responsivity, high brightness and high-contrast, enjoy the favor of people, become the main product in display unit.
Wherein, TFT-LCD display mainly comprises liquid crystal cell, the lower glass substrate (array base palte) of this liquid crystal cell arranges TFT, top glass substrate (color membrane substrates) arranges colored filter, by electric field, the rotation direction of liquid crystal molecule is controlled to the change of signal on the effect of liquid crystal and TFT, thus reach the object of display.In prior art, color membrane substrates is provided with the chock insulator matter supporting liquid crystal cell, the techniques such as this chock insulator matter by applying photoresist on color membrane substrates, and exposes photoresist, development, thus forms chock insulator matter, to isolate the space injecting liquid crystal.
But, become in the process of liquid crystal cell with color membrane substrates to box-like at array base palte, because chock insulator matter needs to fit with array base palte surface, then there is friction, easily produce electrostatic, thus interference is caused to the control of liquid crystal, affect display effect, such as generation Bluepoint is bad.
Summary of the invention
The invention provides a kind of manufacture method of array base palte and apply its array base palte manufactured, solving when chock insulator matter and array base palte are fitted and easily produce electrostatic, thus interference is caused to the control of liquid crystal, affect the problem of display effect.
For achieving the above object, the present invention adopts following technical scheme:
A manufacture method for array base palte, comprising: step 1, and substrate forms grid; Step 2, on described grid, deposition forms gate insulator, described gate insulator is formed source, drain electrode and connects the active layer of described source, drain electrode; Step 3, the described substrate of completing steps 2 forms passivation layer, and on described passivation layer, relevant position forms via hole simultaneously; Step 4, the described substrate of completing steps 3 is formed conductive material layer and the first photoresist layer successively; Step 5, uses mask plate to expose described first photoresist layer, develop, and forms chock insulator matter in non-pixel areas, forms the first patterned photo glue-line in pixel region simultaneously; Step 6, etches along described first patterned photo glue-line described conductive material layer, forms pixel electrode; Step 7, uses mask plate to the described base board to explosure of completing steps 6, development, removes described first patterned photo glue-line.
Particularly, described step 1 specifically comprises: step 11, forms the first metal material layer on the substrate by metal sputtering processes, and described first metal material layer applies the second photoresist layer; Step 12, uses mask plate to expose described second photoresist layer, develop, forms the second patterned photo glue-line; Step 13, etches described first metal material layer along described second patterned photo glue-line, forms described grid, form grid line simultaneously; Step 14, peels off described second patterned photo glue-line.
Wherein, the etching technics in described step 13 is dry etching or wet etching.
Particularly, described step 2 specifically comprises: step 21, and described grid and grid line form described gate insulator by vapour deposition; Step 22, described gate insulator forms active material by vapour deposition, and described active material applies the 3rd photoresist layer; Step 23, uses mask plate to expose described 3rd photoresist layer, develop, forms the 3rd patterned photo glue-line, etch, be formed with active layer along described 3rd patterned photo glue-line to described active material; Step 24, peels off described 3rd patterned photo glue-line; Step 25, described active layer forms the second metal material layer by metal sputtering processes, and described second metal material layer applies the 4th photoresist layer; Step 26, uses mask plate to expose described 4th photoresist layer, develop, forms the 4th patterned photo glue-line; Along described 4th patterned photo glue-line, described second metal material layer is etched, form described source, drain electrode, and the data wire be connected with described source electrode; Step 27, peels off described 4th patterned photo glue-line.
Further, described step 3 specifically comprises: step 31, and the described substrate of completing steps 27 forms layer of passivation material by vapour deposition, and described layer of passivation material applies the 5th photoresist layer; Step 32, uses mask plate to expose described 5th photoresist layer, develop, forms the 5th patterned photo glue-line; Step 33, etches along described 5th patterned photo glue-line described layer of passivation material, forms passivation layer, and on described passivation layer, relevant position forms described via hole simultaneously; Step 34, peels off described 5th patterned photo glue-line.
Preferably, described passivation layer is silicon nitride material.
Wherein, described step 4 is specifically as follows: step 4, and the described substrate completing described step 204 forms conductive material layer by vapour deposition, and described conductive material layer applies described first photoresist layer.
Particularly, described conductive material layer is indium oxide tin film.
A kind of array base palte, uses the manufacture method manufacture of array base palte described above to form.
In the manufacture method of a kind of array base palte that the embodiment of the present invention provides, first, substrate forms grid, gate insulator, active layer successively, Yi Jiyuan, drain electrode and passivation layer, and relevant position forms via hole over the passivation layer; Then, conductive material layer and the first photoresist layer is formed successively over the passivation layer; Afterwards, use mask plate to expose the first photoresist layer, develop, to form chock insulator matter in non-pixel areas, meanwhile form the first patterned photo glue-line in pixel region; Finally, along the first patterned photo glue-line, conductive material layer is etched, to form pixel electrode, and use mask plate to base board to explosure, development, to remove the first patterned photo glue-line.Analyze known thus, in the manufacture method of a kind of array base palte that the embodiment of the present invention provides, in the process forming pixel electrode, by exposing the same photoresist layer of coating, develop, to form the patterned photo glue-line of chock insulator matter and conductive material layer simultaneously, and by the exposure again to the etching of conductive material layer and patterned photo glue-line, development, finally to form pixel electrode; Therefore, it is possible to chock insulator matter is fixedly installed on array base palte, thus become in the process of liquid crystal cell with color membrane substrates to box-like at array base palte, chock insulator matter is fixed on array base palte surface, there is not frictional static, then can not cause interference to the control of liquid crystal, to ensure display effect; And, in the manufacture method of a kind of array base palte that the embodiment of the present invention provides, by exposing the same photoresist layer of coating, develop, to form chock insulator matter simultaneously, namely the formation of chock insulator matter is the use of photoresist when forming pixel electrode, forms chock insulator matter compared to existing technology, can reduce the coating number of times of photoresist on color membrane substrates, thus the use amount of Other substrate materials can be reduced, reduce the manufacturing cost of display unit; The technological processes such as exposure, development, stripping can be reduced simultaneously, and then shorten the manufacturing cycle of display unit, improve production capacity.
Accompanying drawing explanation
The flow chart of the manufacture method of a kind of array base palte that Fig. 1 provides for the embodiment of the present invention;
The generalized section of structure corresponding to the flow process of the manufacture method of a kind of array base palte that Fig. 2-Fig. 8 provides for the embodiment of the present invention;
The flow chart of step 1 in the manufacture method of a kind of array base palte that Fig. 9 provides for the embodiment of the present invention;
In the manufacture method of a kind of array base palte that Figure 10 a to Figure 10 d provides for the embodiment of the present invention step 1 flow process corresponding to the generalized section of structure;
The flow chart of step 2 in the manufacture method of a kind of array base palte that Figure 11 provides for the embodiment of the present invention;
The flow chart of step 3 in the manufacture method of a kind of array base palte that Figure 12 provides for the embodiment of the present invention;
In the manufacture method of a kind of array base palte that Figure 13 a to Figure 13 d provides for the embodiment of the present invention step 3 flow process corresponding to the generalized section of structure.
In figure, 1 is substrate; 2 is the second patterned photo glue-line for grid, 21 be the first metal material layer, 22 is the second photoresist layer, 23; 3 is gate insulator; 4a is source electrode, 4b is drain electrode; 5 is active layer; 6 is conductive material layer; 7 is the first photoresist layer; A is non-pixel areas, B is pixel region; 8 is chock insulator matter; 9 is the first patterned photo glue-line; 10 is pixel electrode; 11 be passivation layer, 111 for layer of passivation material, 112 be the 5th photoresist layer, 113 be the 5th patterned photo glue-line.
Embodiment
Be described in detail below in conjunction with the manufacture method of accompanying drawing to a kind of array base palte of the embodiment of the present invention.
The embodiment of the present invention provides a kind of manufacture method of array base palte, as shown in figures 1-8, comprising: step 1, forms grid 2 on substrate 1; Step 2, on grid 2, deposition forms gate insulator 3, gate insulator 3 is formed source, drain electrode (4a, 4b) and connects the active layer 5 of source, drain electrode (4a, 4b); Step 3, the substrate of completing steps 2 forms passivation layer 11, and on passivation layer 11, relevant position forms via hole simultaneously; Step 4, the substrate 1 of completing steps 3 is formed conductive material layer 6 and the first photoresist layer 7 successively; Step 5, uses mask plate to expose the first photoresist layer 7, develop, and forms chock insulator matter 8 at non-pixel areas A, forms the first patterned photo glue-line 9 at pixel region B simultaneously; Step 6, etches along the first patterned photo glue-line 9 pairs of conductive material layers 6, forms pixel electrode 10; Step 7, uses mask plate to the base board to explosure of completing steps 6, development, removes the first patterned photo glue-line 9.
In the manufacture method of a kind of array base palte that the embodiment of the present invention provides, first, substrate forms grid, gate insulator, active layer successively, Yi Jiyuan, drain electrode and passivation layer, and relevant position forms via hole over the passivation layer; Then, conductive material layer and the first photoresist layer is formed successively over the passivation layer; Afterwards, use mask plate to expose the first photoresist layer, develop, to form chock insulator matter in non-pixel areas, meanwhile form the first patterned photo glue-line in pixel region; Finally, along the first patterned photo glue-line, conductive material layer is etched, to form pixel electrode, and use mask plate to base board to explosure, development, to remove the first patterned photo glue-line.Analyze known thus, in the manufacture method of a kind of array base palte that the embodiment of the present invention provides, in the process forming pixel electrode, by exposing the same photoresist layer of coating, develop, to form the patterned photo glue-line of chock insulator matter and conductive material layer simultaneously, and by the exposure again to the etching of conductive material layer and patterned photo glue-line, development, finally to form pixel electrode; Therefore, it is possible to chock insulator matter is fixedly installed on array base palte, thus become in the process of liquid crystal cell with color membrane substrates to box-like at array base palte, chock insulator matter is fixed on array base palte surface, there is not frictional static, then can not cause interference to the control of liquid crystal, to ensure display effect; And, in the manufacture method of a kind of array base palte that the embodiment of the present invention provides, by exposing the same photoresist layer of coating, develop, to form chock insulator matter simultaneously, namely the formation of chock insulator matter is the use of photoresist when forming pixel electrode, forms chock insulator matter compared to existing technology, can reduce the coating number of times of photoresist on color membrane substrates, thus the use amount of Other substrate materials can be reduced, reduce the manufacturing cost of display unit; The technological processes such as exposure, development, stripping can be reduced simultaneously, and then shorten the manufacturing cycle of display unit, improve production capacity.
It should be noted that herein, the manufacture method of a kind of array base palte that the embodiment of the present invention provides, goes for the display modes such as TN (stable twisted nematic panel), ADS (fringing field effect's profile plate) and VA (vertical loop is to array type panel).
Particularly, as shown in figs. 9-10, wherein, Figure 10 a-Figure 10 d is referred to as Figure 10, and above-mentioned steps 1 specifically can comprise: step 11, as shown in Figure 10 a, form the first metal material layer 21 by metal sputtering processes on substrate 1, the first metal material layer 21 applies the second photoresist layer 22.
Wherein, first metal material layer 21 can be the metal or alloy such as molybdenum, antimony, aluminium, copper, can preferably adopt metal sputtering processes to be formed on substrate 1, magnetron sputtering technique, thermal evaporation or other film build method can certainly be adopted to be formed on substrate 1, and this is not restricted.
Step 12, as shown in fig. lob, uses mask plate to expose the second photoresist layer 22, develop, forms the second patterned photo glue-line 23.
Particularly, the mask plate adopted when the second patterned photo glue-line 23 is formed can be the common mask plate comprising transparent area and alternatively non-transparent district, or has the gray level mask plate in transparent area, alternatively non-transparent district, semi-opaque region and partial light permeability district.
Step 13, as shown in figure l oc, etches the first metal material layer 21 along the second patterned photo glue-line 23, forms above-mentioned grid 2, form grid line simultaneously.
Further, etching technics in above-mentioned steps 13 can be dry etching or wet etching, wherein, dry etching is after gas being become electricity slurry by electric field, react with corresponding thin layer or metal level and reach etching object, wet etching reaches etching object by the corrosive effect of chemical liquids; Preferably wet etching can be adopted in the embodiment of the present invention.
Step 14, as shown in fig. 10d, peel off the second patterned photo glue-line 23.
Particularly, the stripping of the second patterned photo glue-line 23 can adopt medicament lift-off technology, also can adopt other rational lift-off technologies.
Wherein, as shown in figure 11, above-mentioned steps 2 specifically can comprise: step 21, and above-mentioned grid 2 and grid line form gate insulator 3 by vapour deposition.
Step 22, gate insulator 3 forms active material by vapour deposition, and active material applies the 3rd photoresist layer.
Step 23, uses mask plate to expose the 3rd photoresist layer, develop, forms the 3rd patterned photo glue-line, etch, be formed with active layer 5 along the 3rd patterned photo glue-line to active material.Wherein, mask plate can adopt common mask plate or gray level mask plate.
Step 24, peels off the 3rd patterned photo glue-line.Wherein, the stripping of the 3rd patterned photo glue-line can adopt medicament lift-off technology.
Step 25, above-mentioned active layer 5 forms the second metal material layer by metal sputtering processes, and the second metal material layer applies the 4th photoresist layer.
Particularly, the second metal material layer can be the metal or alloy such as molybdenum, antimony, aluminium, copper, metal sputtering processes preferably can be adopted to be formed on substrate 1, magnetron sputtering technique or thermal evaporation process can certainly be adopted to be formed on substrate 1.
Step 26, uses mask plate to expose the 4th photoresist layer, develop, forms the 4th patterned photo glue-line; Along the 4th patterned photo glue-line, the second metal material layer is etched, form above-mentioned source, drain electrode (4a, 4b), and the data wire be connected with source electrode 4a.
Wherein, mask plate can adopt common mask plate or gray level mask plate; Data wire also can not be formed with layer with source, drain electrode (4a, 4b), and this is not restricted.
Step 27, peels off the 4th patterned photo glue-line.The stripping of the 4th patterned photo glue-line can adopt medicament lift-off technology.
It should be noted that, the concrete steps of above-mentioned steps 2 are the conventional method of prior art, and its patterning processes is specifically as follows MASK patterning processes herein, and usual MASK patterning processes includes 4MASK, 5MASK or more times MASK.Its roughly process be: first on array base palte, deposit corresponding thin layer or metal level, one deck photoresist is applied afterwards at most last layer, photoresist is exposed by using specific mask plate, develops, make its patterning, and then on array base palte, form specific pattern by etching technics, remove finally by stripping technology the manufacture that photoresist can complete corresponding pattern.Wherein, in a MASK technique, also may need the stripping carrying out repeatedly photoresist.
Wherein, the active layer 5 in above-mentioned steps 2 and source, drain electrode (4a, 4b) can also be formed by a MASK technique, particularly, first on gate insulator 3, deposit active material and the second metal material layer; Apply the 3rd photoresist layer afterwards again, and by gray level mask plate, half exposure, development are carried out to the 3rd photoresist layer, form the 3rd patterned photo glue-line; Then along the 3rd patterned photo glue-line, relevant etching and ashing are carried out to active material and the second metal material layer, be formed with active layer 5 and source, drain electrode (4a, 4b); Finally peel off the 3rd patterned photo glue-line.
Further, as illustrated by figs. 12-13, wherein, Figure 13 a-Figure 13 d is referred to as Figure 13, above-mentioned steps 3 specifically can comprise: step 31, as depicted in fig. 13 a, the substrate 1 completing above-mentioned steps 27 forms layer of passivation material 111 by vapour deposition, layer of passivation material 111 applies the 5th photoresist layer 112.
Step 32, as illustrated in fig. 13b, uses mask plate to expose the 5th photoresist layer 112, develop, forms the 5th patterned photo glue-line 113.
Wherein, mask plate can adopt common mask plate or gray level mask plate, and certainly, also can adopt the mask plate of other Rational structure, this is not restricted.
Step 33, as shown in figure 13 c, etches along the 5th patterned photo glue-line 113 pairs of layer of passivation material 111, forms passivation layer 11, and on passivation layer 11, relevant position forms via hole simultaneously.
Preferably, above-mentioned passivation layer 11 can be silicon nitride material, can certainly select oxide, nitride or oxynitrides, or the organic insulating film that other reasonable material also can be adopted to make.
Step 34, as shown in figure 13d, peels off the 5th patterned photo glue-line 113.
Particularly, the stripping of the 5th patterned photo glue-line 113 can adopt medicament lift-off technology.
Wherein, above-mentioned steps 4 is specifically as follows: on the substrate 1 completing above-mentioned steps 34, form conductive material layer 6 by vapour deposition, conductive material layer 6 applies the first photoresist layer 7.
Preferably, above-mentioned conductive material layer 6 can be indium oxide tin film, can certainly be other rational electrode materials, such as aluminium alloy or copper alloy.
Particularly, the pixel electrode 10 that conductive material layer 6 is formed, can by the via hole of relevant position on passivation layer 11, the such as via hole of corresponding drain electrode 4b position, thus be connected with drain electrode 4b, and form horizontal component of electric field with public electrode, and then change the ordered state of liquid crystal molecule, to reach display object.
The embodiment of the present invention also provides a kind of array base palte, and particularly, this array base palte is formed by the manufacture method manufacture of the array base palte using above-described embodiment description.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, is anyly familiar with those skilled in the art in the technical scope that the present invention discloses; change can be expected easily or replace, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of described claim.
Claims (9)
1. a manufacture method for array base palte, is characterized in that, comprising:
Step 1, substrate forms grid;
Step 2, on described grid, deposition forms gate insulator, described gate insulator is formed source, drain electrode and connects the active layer of described source, drain electrode;
Step 3, the described substrate of completing steps 2 forms passivation layer, and on described passivation layer, relevant position forms via hole simultaneously;
Step 4, the described substrate of completing steps 3 is formed conductive material layer and the first photoresist layer successively;
Step 5, uses mask plate to expose described first photoresist layer, develop, and forms chock insulator matter in non-pixel areas, forms the first patterned photo glue-line in pixel region simultaneously;
Step 6, etches along described first patterned photo glue-line described conductive material layer, forms pixel electrode;
Step 7, uses mask plate to the described base board to explosure of completing steps 6, development, removes described first patterned photo glue-line.
2. the manufacture method of array base palte according to claim 1, is characterized in that, described step 1 specifically comprises:
Step 11, forms the first metal material layer by metal sputtering processes on the substrate, and described first metal material layer applies the second photoresist layer;
Step 12, uses mask plate to expose described second photoresist layer, develop, forms the second patterned photo glue-line;
Step 13, etches described first metal material layer along described second patterned photo glue-line, forms described grid, form grid line simultaneously;
Step 14, peels off described second patterned photo glue-line.
3. the manufacture method of array base palte according to claim 2, is characterized in that, the etching technics in described step 13 is dry etching or wet etching.
4. the manufacture method of array base palte according to claim 2, is characterized in that, described step 2 specifically comprises:
Step 21, described grid and grid line form described gate insulator by vapour deposition;
Step 22, described gate insulator forms active material by vapour deposition, and described active material applies the 3rd photoresist layer;
Step 23, uses mask plate to expose described 3rd photoresist layer, develop, forms the 3rd patterned photo glue-line, etch, be formed with active layer along described 3rd patterned photo glue-line to described active material;
Step 24, peels off described 3rd patterned photo glue-line;
Step 25, described active layer forms the second metal material layer by metal sputtering processes, and described second metal material layer applies the 4th photoresist layer;
Step 26, uses mask plate to expose described 4th photoresist layer, develop, forms the 4th patterned photo glue-line; Along described 4th patterned photo glue-line, described second metal material layer is etched, form described source, drain electrode, and the data wire be connected with described source electrode;
Step 27, peels off described 4th patterned photo glue-line.
5. the manufacture method of array base palte according to claim 4, is characterized in that, described step 3 specifically comprises:
Step 31, the described substrate of completing steps 27 forms layer of passivation material by vapour deposition, and described layer of passivation material applies the 5th photoresist layer;
Step 32, uses mask plate to expose described 5th photoresist layer, develop, forms the 5th patterned photo glue-line;
Step 33, etches along described 5th patterned photo glue-line described layer of passivation material, forms passivation layer, and on described passivation layer, relevant position forms described via hole simultaneously;
Step 34, peels off described 5th patterned photo glue-line.
6. the manufacture method of array base palte according to claim 5, is characterized in that, described passivation layer is silicon nitride material.
7. the manufacture method of array base palte according to claim 5, is characterized in that, described step 4 is specifically as follows:
Step 4, the described substrate completing described step 34 forms conductive material layer by vapour deposition, and described conductive material layer applies described first photoresist layer.
8. the manufacture method of the array base palte according to claim 1 or 7, is characterized in that, described conductive material layer is indium oxide tin film.
9. an array base palte, is characterized in that, uses the manufacture method manufacture of the arbitrary described array base palte of claim 1-8 to form.
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| CN112366180A (en) * | 2020-11-09 | 2021-02-12 | 浙江清华柔性电子技术研究院 | LED packaging method and LED packaging device |
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| CN112366180A (en) * | 2020-11-09 | 2021-02-12 | 浙江清华柔性电子技术研究院 | LED packaging method and LED packaging device |
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Application publication date: 20141217 |