CN104217947A - Semiconductor manufacturing method - Google Patents
Semiconductor manufacturing method Download PDFInfo
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- CN104217947A CN104217947A CN201310215646.7A CN201310215646A CN104217947A CN 104217947 A CN104217947 A CN 104217947A CN 201310215646 A CN201310215646 A CN 201310215646A CN 104217947 A CN104217947 A CN 104217947A
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- false grid
- grid layer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 238000000034 method Methods 0.000 claims abstract description 42
- 238000005530 etching Methods 0.000 claims abstract description 22
- 239000000758 substrate Substances 0.000 claims description 25
- 239000000463 material Substances 0.000 claims description 17
- 230000004888 barrier function Effects 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 238000005516 engineering process Methods 0.000 claims description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 238000010884 ion-beam technique Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 4
- 238000003801 milling Methods 0.000 claims description 3
- 238000001020 plasma etching Methods 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 230000005669 field effect Effects 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 92
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000000151 deposition Methods 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910003855 HfAlO Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005293 physical law Methods 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 150000002910 rare earth metals Chemical class 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a fin FET (field effect transistor) manufacturing method. After pseudo-gate layers having different top heights are formed, a dielectric layer fully covering the pseudo-gate layers is formed; the dielectric layer is etched back to expose parts, having higher tops, of the pseudo-gate layers; the parts of the pseudo-gate layers are subjected to dry anisotropic etching through the exposed tops. Etching rate of the dry anisotropic etching is easy to control, the tops of the parts of the pseudo-gate layers are decreased to be as high as the low-topped parts of the pseudo-gate layers, the pseudo-gate layers having flat surfaces can be obtained after removal of the dielectric layer, a following process is facilitated, and yield of the devices is guaranteed.
Description
Technical field
The present invention relates to method, semi-conductor device manufacturing method field, especially, relate to the semiconductor making method of the false grid flatening process of a kind of FinFET.
Background technology
Over nearly 30 years, semiconductor device is always according to Moore's Law scaled down, and the characteristic size of semiconductor integrated circuit constantly reduces, and integrated level improves constantly.Along with technology node enters deep-submicron field, such as, within 100nm, even within 45nm, conventional field effect transistor (FET), be also plane FET, start the restriction meeting with various basic physical law, the prospect of its scaled down is challenged.Therefore, the FET of numerous new structure is developed, and to tackle the demand of reality, and FinFET is exactly wherein a kind of new construction device very with scaled down potentiality.
FinFET, FinFET is a kind of multiple-grid semiconductor device.Due to structural exclusive feature, FinFET becomes the device that deep submicron integrated circuit field has development prospect.As its name suggests, FinFET comprises a Fin perpendicular to the substrate of body silicon, and Fin is called as fin or fin-shaped semiconductor column, and different FinFET is come by STI (shallow trench isolation from) segmentation of structures.Be different from conventional plane FET, the channel region of FinFET is positioned within Fin.Gate insulator and grid surround Fin in side and end face, thus form the grid at least two sides, are namely positioned at the grid on two sides of Fin; Meanwhile, by the thickness of control Fin, FinFET is made to have splendid characteristic: better short-channel effect rejection ability, better sub-threshold slope, lower off-state current, without floater effect, lower operating voltage, etc.
Existing FinFET structure and manufacture method thereof generally include: in body silicon substrate or SOI substrate, etching forms multiple parallel Fin along first direction extension and groove; Fill insulant forms shallow trench isolation from (STI) in the trench; Be generally the false grid insulating barrier of silica at Fin top and side wall deposition, on false grid insulating barrier, deposition is generally the false grid layer of polysilicon or amorphous silicon; Etching false grid layer and false grid insulating barrier, form the false grid storehouse extended along second direction, wherein second direction is preferably perpendicular to first direction; False grid storehouse along first direction both sides formed grid curb wall; The Fin along first direction both sides of etching grid side wall forms source and drain groove, and extension forms source-drain area in source and drain groove; Interlayer dielectric layer (ILD); Remove false grid storehouse, in ILD, form gate trench; The grid conducting layer of high k gate insulator and metal, metal alloy or metal nitride is deposited in gate trench.
Wherein, after the false grid layer (can with reference to the false grid layer 4 of accompanying drawing 2) forming polysilicon or amorphous silicon, need to carry out planarization to false grid layer, be beneficial to the carrying out of subsequent technique.But, in existing FinFET technique, planarization stops same media interior and lacks terminal triggering, and the planarization of false grid layer is difficult to precisely controlled, the uniformity of technique and repeatability are all poor, and this also brings bad impact to the structure of subsequent technique and whole FinFET.
Therefore, need to provide a kind of new FinFET manufacture method, improve the defect of existing false grid layer planarization, to obtain better process controllability and yield of devices.
Summary of the invention
For the unmanageable defect of false grid layer planarization in prior art, the present invention adopts the dielectric layer of extra formation and returns etching technics, and make the planarization of false grid layer have good controllability, uniformity and repeatability are obtained for guarantee.
According to an aspect of the present invention, the invention provides a kind of method, semi-conductor device manufacturing method, comprise the steps:
Substrate is provided, forms fin over the substrate;
Form false grid insulating barrier;
Comprehensive formation false grid layer, wherein, the described false grid layer be positioned at directly over described fin has the first end face, and the described false grid layer being positioned at the described types of flexure outside described fin has the second end face, and described first end face is higher than described second end face;
Form the dielectric layer covering described false grid layer completely;
Etching is carried out back to described dielectric layer, exposes described first end face of described false grid layer;
Described false grid layer is etched, until the end face of the described false grid layer be etched and described second either flush via described first end face exposed;
Remove described dielectric layer, thus obtain the described false grid layer with flat surfaces.
In the method for the invention, the material of described dielectric layer is oxide, is preferably silicon dioxide; The material of described false grid layer is polysilicon or amorphous silicon, is preferably P type polysilicon or amorphous silicon.
In the method for the invention, the concrete technology that described dielectric layer carries out back etching is comprised: reactive ion etching, ion beam milling, ion beam etching or wet etching.
In the method for the invention, be anisotropy dry etching via described first end face exposed to the concrete technology that described false grid layer etches.
In the method for the invention, between described fin, isolation structure is formed.
In the method for the invention, removal described dielectric layer, thus obtain there is the described false grid layer of flat surfaces after, also comprise:
Form grid curb wall;
Form source and drain areas;
Remove described false grid layer and described false grid insulating barrier;
Form high-K gate insulating barrier and metal gates.
The invention has the advantages that: after formation has the false grid layer of differing heights end face, form the dielectric layer covering false grid layer completely, by carrying out back etching to dielectric layer, expose the part false grid layer with higher end face, and by the end face exposed, anisotropy dry etching is carried out to this part false grid layer, because the etch rate of anisotropic dry etching easily controls, the end face of this part false grid layer can be made to drop to the part false grid layer level with lower end face, thus the false grid layer with flat surfaces can be obtained after removing dielectric layer, be conducive to the carrying out of subsequent technique and ensure that yield of devices.
Accompanying drawing explanation
Fig. 1-8 method, semi-conductor device manufacturing method flow process of the present invention and structural representation thereof.
Embodiment
Below, by the specific embodiment shown in accompanying drawing, the present invention is described.But should be appreciated that, these describe just exemplary, and do not really want to limit the scope of the invention.In addition, in the following description, the description to known features and technology is eliminated, to avoid unnecessarily obscuring concept of the present invention.
The invention provides a kind of method, semi-conductor device manufacturing method, the extra dielectric layer formed is utilized to improve the controllability of false grid layer flatening process, its manufacturing process is see accompanying drawing 1-8, wherein, (a) figure in every width figure is the cross-sectional view (also namely hereinafter along the cross-sectional view of second direction) perpendicular to fin bearing of trend, and (b) figure is along the cross-sectional view (also namely hereinafter along the cross-sectional view of first direction) in the fin of fin bearing of trend.
First, see accompanying drawing 1, provide substrate 1, form fin 11 on substrate 1.Substrate 1 can need and choose reasonable according to device application, include but not limited to body silicon substrate, SOI substrate, germanium substrate, germanium silicon (SiGe) substrate, compound semiconductor materials, such as gallium nitride (GaN), GaAs (GaAs), indium phosphide (InP) etc.For the consideration with traditional cmos process compatibility, the substrate 1 in the present embodiment preferably have employed body silicon substrate.
Form the concrete mode of fin 11 on substrate 1 to comprise: photoetching etched substrate 1, in substrate 1, form the multiple fin 11 and the groove that extend distribution along first direction.In groove between adjacent fin 11, be formed with isolation structure 2, specifically comprise process deposits dielectric materials such as adopting PECVD, HDP-CVD, RTO (rapid thermal oxidation), such as silica, silicon oxynitride etc., thus constitute the electric isolation between the device that is formed on each fin 11.It should be noted that the dotted line in accompanying drawing between substrate 1 and fin 11 represents the fin 11 of homogeneity and the boundary of substrate 1, do not represent them for different materials.
Then, see accompanying drawing 2, first, false grid insulating barrier 3 is formed.The material of false grid insulating barrier 3 is generally silica, and its formation process includes, but are not limited to LPCVD, PECVD etc., and its thickness is 1-5nm, preferably at 1-3nm.In accompanying drawing 2 (a), false grid insulating barrier 3 encloses the end face and two sides that fin 11 exposes.
Next, comprehensive formation false grid layer 4, wherein, the false grid layer 4 be positioned at directly over fin 11 has the first end face, and the false grid layer 4 be positioned at above the substrate 1 outside fin 11 has the second end face, and the first end face is higher, and the second end face is lower, namely the first end face is higher than the second end face.Reason is: substrate 1 has rugged fin 11 and isolation structure 2, the end face of false grid layer 4 is also uneven, namely the end face being positioned at the false grid layer 4 directly over fin 11 is higher, and the end face being positioned at the false grid layer 4 above the substrate 1 outside fin 11 is lower.The material of false grid layer 4 is polysilicon or amorphous silicon, is preferably P type polysilicon or amorphous silicon.The thickness of false grid layer 4 does not do particular determination, it needs to arrange according to the yardstick of fin 11, because false grid layer 4 needs to cover fin 11 completely, the minimum end face of false grid layer 4 is preferably higher than the end face of fin 11, is also the end face of the second end face higher than fin 11.Like this, false grid layer 4 and false grid insulating barrier 3 define false grid storehouse.
Then, see accompanying drawing 3, form the dielectric layer 5 covering false grid layer 4 completely, and etching is carried out back to dielectric layer 5, expose the first end face of false grid layer 4.The material of dielectric layer 5 is different from false grid layer 4, and their etch rate has bigger difference.In the present embodiment, the material of dielectric layer 5 is oxide, is preferably silicon dioxide, and its depositing operation adopts the technique that fillibility is good, such as PECVD, HDP-CVD etc.The thickness of dielectric layer 5 is also not specifically limited, but, need to cover false grid layer 4 completely.In the present embodiment, the concrete technology that dielectric layer 5 carries out back etching is comprised: reactive ion etching, ion beam milling, ion beam etching or wet etching.Usually, by return etching technics, the end face of dielectric layer 5 by the first either flush in exposed false grid layer 4, as shown in Figure 3; In addition, returning etching technics can over etching, thus makes the end face of dielectric layer 5 lower than the first end face, but dielectric layer 5 will be avoided to etch completely.
Then, see accompanying drawing 4, via the first end face exposed, false grid layer 4 is etched, until the end face of the false grid layer 4 be etched and the second lower either flush.In the present embodiment, be anisotropy dry etching via the first end face to the concrete technology that false grid layer 4 etches.Because the speed of anisotropy dry etching can be accurately controlled, therefore, it is possible to control the etch amount of false grid layer 4 exactly, thus make the end face of the false grid layer 4 be etched accurately can keep concordant with the second lower end face.Avoiding problems the problem lacking terminal triggering when adopting cmp planarization false grid layer 4, therefore, the planarization of false grid layer 4 is able to accurate control, uniformity and the repeatability of technique are all better than prior art, avoid the structure of cmp planarization on subsequent technique and whole FinFET and bring bad impact.
Then, see accompanying drawing 5, remove dielectric layer 5, thus obtain the false grid layer 4 with flat surfaces.Usually, wet etching can be adopted to remove dielectric layer 5.
Then, see accompanying drawing 6, after acquisition has the false grid layer 4 of flat surfaces, carry out the manufacture of device miscellaneous part, comprise and form source and drain areas 6 and grid curb wall 7.First will define the pattern of grid lines, it extends along the second direction perpendicular to first direction usually, etches away unnecessary false grid layer 4.Then, deposited overall grid curb wall material, and carry out back etching, thus form grid curb wall 7.In addition, form source and drain areas 6 and specifically comprise: the pattern defining source and drain areas, etches fin 11, form source and drain areas groove; Then, in source and drain areas groove, extension forms source and drain areas 6.Wherein, the material of source and drain areas 6 includes, but are not limited to Si, GeSi etc.
Next, see accompanying drawing 7 and Fig. 8, carry out rear grid technique.First, form the interlayer dielectric layer (ILD) 8 of bottom, cover on source and drain areas 6, usually, interlayer dielectric layer is low-K material or silica; Then, remove false grid layer 4 and false grid insulating barrier 3, thus form gate recess 9; Among gate recess 9, successively form high-K gate insulating barrier 13 and metal gates 14.Wherein, the material of high-K gate insulating barrier 13 is selected from one or more layers of following material one or a combination set of formation: A1
2o
3, HfO
2, comprise HfSiO
x, HfSiON, HfAlO
x, HfTaO
x, HfLaO
x, HfAlSiO
xand HfLaSiO
xone of at least at interior hafnium base high K dielectric material, comprise ZrO
2, La
2o
3, LaAlO
3, TiO
2, or Y
2o
3one of at least at interior rare earth based high K dielectric material; The material of metal gates 14 is metal, alloy or metallic compound, such as TiN, TaN, W etc.
So far, method of the present invention is detailed according to above-mentioned embodiment.In the method for the invention, owing to substrate having rugged structure, the false grid layer of formation has differing heights end face, afterwards, by forming the dielectric layer covering false grid layer completely, and etching being carried out back to dielectric layer, exposing the part false grid layer with higher end face; Then, by the end face exposed, anisotropy dry etching is carried out to this part false grid layer, because the etch rate of anisotropic dry etching is easily precisely controlled, the higher end face of false grid layer can be made to drop to and lower end face level, thus the false grid layer with flat surfaces can be obtained after removing dielectric layer, be conducive to the carrying out of subsequent technique and ensure that yield of devices.
With reference to embodiments of the invention, explanation is given to the present invention above.But these embodiments are only used to the object illustrated, and are not intended to limit the scope of the invention.Scope of the present invention is by claims and equivalents thereof.Do not depart from the scope of the present invention, those skilled in the art can make a variety of substitutions and modifications, and these substitutions and modifications all should fall within the scope of the present invention.
Claims (9)
1. a method, semi-conductor device manufacturing method, for the manufacture of FinFET, wherein, comprises the steps:
Substrate is provided, forms fin over the substrate;
Form false grid insulating barrier;
Comprehensive formation false grid layer, wherein, the described false grid layer be positioned at directly over described fin has the first end face, and the described false grid layer being positioned at the described types of flexure outside described fin has the second end face, and described first end face is higher than described second end face;
Form the dielectric layer covering described false grid layer completely;
Etching is carried out back to described dielectric layer, exposes described first end face of described false grid layer;
Described false grid layer is etched, until the end face of the described false grid layer be etched and described second either flush via described first end face exposed;
Remove described dielectric layer, thus obtain the described false grid layer with flat surfaces.
2. method according to claim 1, is characterized in that, the material of described dielectric layer is oxide.
3. method according to claim 2, is characterized in that, described dielectric layer is silicon dioxide.
4. method according to claim 1, is characterized in that, the material of described false grid layer is polysilicon or amorphous silicon.
5. method according to claim 4, is characterized in that, the material of described false grid layer is P type polysilicon or amorphous silicon.
6. method according to claim 1, is characterized in that, comprises: reactive ion etching, ion beam milling, ion beam etching or wet etching to the concrete technology that described dielectric layer carries out back etching.
7. method according to claim 1, is characterized in that, is anisotropy dry etching via described first end face exposed to the concrete technology that described false grid layer etches.
8. method according to claim 1, is characterized in that, between described fin, form isolation structure.
9. method according to claim 1, is characterized in that, removal described dielectric layer, thus obtain there is the described false grid layer of flat surfaces after, also comprise:
Form grid curb wall;
Form source and drain areas;
Remove described false grid layer and described false grid insulating barrier; Form high-K gate insulating barrier and metal gates.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201310215646.7A CN104217947B (en) | 2013-05-31 | 2013-05-31 | Semiconductor making method |
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| CN201310215646.7A CN104217947B (en) | 2013-05-31 | 2013-05-31 | Semiconductor making method |
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| CN104217947B CN104217947B (en) | 2018-11-06 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2018182104A (en) * | 2017-04-14 | 2018-11-15 | 東京エレクトロン株式会社 | Film deposition method |
| CN109427889A (en) * | 2017-08-31 | 2019-03-05 | 台湾积体电路制造股份有限公司 | Fin formula field effect transistor device and method |
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| US20120083125A1 (en) * | 2010-10-04 | 2012-04-05 | Jsr Corporation | Chemical Mechanical Planarization With Overburden Mask |
| US20120196410A1 (en) * | 2011-01-31 | 2012-08-02 | United Microelectronics Corp | Method for fabricating fin field effect transistor |
| CN103839820A (en) * | 2012-11-25 | 2014-06-04 | 中国科学院微电子研究所 | Method for manufacturing semiconductor device |
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2013
- 2013-05-31 CN CN201310215646.7A patent/CN104217947B/en active Active
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| CN1858900A (en) * | 2005-05-02 | 2006-11-08 | 海力士半导体有限公司 | Method of fabricating a transistor having a triple channel in a memory device |
| US20120083125A1 (en) * | 2010-10-04 | 2012-04-05 | Jsr Corporation | Chemical Mechanical Planarization With Overburden Mask |
| US20120196410A1 (en) * | 2011-01-31 | 2012-08-02 | United Microelectronics Corp | Method for fabricating fin field effect transistor |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2018182104A (en) * | 2017-04-14 | 2018-11-15 | 東京エレクトロン株式会社 | Film deposition method |
| CN109427889A (en) * | 2017-08-31 | 2019-03-05 | 台湾积体电路制造股份有限公司 | Fin formula field effect transistor device and method |
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| Publication number | Publication date |
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| CN104217947B (en) | 2018-11-06 |
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