CN104124159B - Method, semi-conductor device manufacturing method - Google Patents
Method, semi-conductor device manufacturing method Download PDFInfo
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- CN104124159B CN104124159B CN201310143349.6A CN201310143349A CN104124159B CN 104124159 B CN104124159 B CN 104124159B CN 201310143349 A CN201310143349 A CN 201310143349A CN 104124159 B CN104124159 B CN 104124159B
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- side wall
- gate electrode
- dummy gate
- dielectric layer
- electrode storehouse
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 239000010410 layer Substances 0.000 claims abstract description 37
- 239000011229 interlayer Substances 0.000 claims abstract description 22
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 12
- 238000002955 isolation Methods 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 5
- 239000003989 dielectric material Substances 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 238000000407 epitaxy Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 abstract description 6
- 238000005530 etching Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910002244 LaAlO3 Inorganic materials 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910000765 intermetallic Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 238000005293 physical law Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Abstract
The invention provides a kind of FinFET transistor fabrication process, using isotropic deposition and technique is etched back to, can form side wall of the width less than lithographic feature size on the two sides of dummy gate electrode；Then, after filling interlayer dielectric layer, the side wall is removed, the gate recess with Asia F sizes can be formed, and then the grid lines with Asia F sizes can be formed in gate recess.The present invention is in the case of less demanding to lithographic accuracy, you can realize the formation of Asia F size grid lines, meanwhile, relative to existing sub- F sizes line strip into technique, technological process of the invention is simple, and reliability and controllability are high.
Description
Technical field
The present invention relates to method, semi-conductor device manufacturing method field, especially, it is related to a kind of FinFET semiconductor devices manufacture
Method.
Background technology
Over nearly 30 years, semiconductor devices is always according to Moore's Law scaled down, the feature chi of semiconductor integrated circuit
Very little continuous diminution, integrated level is improved constantly.As technology node enters within deep-submicron field, such as 100nm, or even 45nm
Within, conventional field effect transistor (FET), namely plane FET, start to meet with the limitation of various basic physical laws, make its etc.
The prospect of scale smaller is challenged.The FET of numerous new structures is developed, to tackle the demand of reality, wherein,
FinFET is exactly a kind of new construction device for having very much a scaled down potentiality.
FinFET, FinFET is a kind of many gate semiconductor devices.Due to the exclusive feature in structure,
FinFET turns into the device of deep submicron integrated circuit field very with prospects.As its name suggests, FinFET includes one vertically
In the Fin of the substrate of body silicon, Fin is referred to as fin or fin-shaped semiconductor column, and different FinFET is separated by sti structure.
It is located at different from conventional plane FET, FinFET channel region within Fin.Gate insulator and grid are in side and top surface bag
Fin is enclosed, so as to form the grid at least two sides, i.e. the grid on Fin two sides；Meanwhile, by the thickness for controlling Fin
Degree so that FinFET has splendid characteristic：More preferable short-channel effect rejection ability, more preferable sub-threshold slope is relatively low
Off-state current, eliminates floater effect, and lower operating voltage is more beneficial for scaled.Generally, FinFET grid is
Using the high K/ metal gates (HKMG) of rear grid technique formation, to improve FinFET performance.
In order to continue Moore's Law, the characteristic size of device constantly reduces, but routine 193nm photoetching reaches substantially
To the limit, the other technologies such as EUV, electron beam also have a segment distance from business application., it is necessary to be formed with small chi in FinFET
Very little grid lines, in particular, it is desirable to the grid lines that line size is less than lithographic feature size are formed, namely with sub- special
Levy size (sub- F) grid lines.In existing process, the complex process of Asia F size grid lines is formed, will to lithographic accuracy
Ask also higher.Accordingly, it is desirable to provide a kind of new small size grid line strip can form FinFET sub- F chis into method
Very little grid lines.
The content of the invention
The problem of for current small size grid line strip into technique, the present invention proposes a kind of semiconductor making method,
There is provided the FinFET with sub- F sizes grid lines.
The present invention provides a kind of method, semi-conductor device manufacturing method, wherein, comprise the following steps：
Substrate is provided, fin, and the isolation structure between the adjacent fin is formed over the substrate；
Form dummy gate electrode storehouse；
The first side wall is formed on the side of the dummy gate electrode storehouse；
Remove the dummy gate electrode storehouse；
Form FinFET source and drain areas；
First side wall is completely covered in comprehensive interlayer dielectric layer, the interlayer dielectric layer；
The interlayer dielectric layer is planarized, the top surface of first side wall is exposed；
First side wall is removed, gate recess is formed；
Stack is formed in the gate recess.
In the method for the invention, the dummy gate electrode storehouse includes dummy gate electrode, dummy gate electrode insulating barrier；Dummy gate electrode
For polysilicon or non-crystalline silicon, dummy gate electrode insulating barrier is silica.
In the method for the invention, the first side wall is formed on the side of the dummy gate electrode storehouse to specifically include：Deposition
The first spacer material layer of predetermined thickness, its side for covering the dummy gate electrode storehouse and top surface；Technique is etched back, is made
The first spacer material layer is only remained on the side of the dummy gate electrode storehouse, so as to form first side wall.
In the method for the invention, in the step of removing first side wall, using wet etching or dry etching
First side wall is removed, also, the etch rate and the ratio between the etch rate of the interlayer dielectric layer of first side wall are big
In 5: 1, preferably more than 10: 1；The material of first side wall is silica, silicon nitride, high-k dielectrics, polysilicon, amorphous
Silicon.
In the method for the invention, the line size of first side wall is less than lithographic feature size.
In the method for the invention, formed on the side of the dummy gate electrode storehouse after the first side wall, described
The second side wall is formed on the side of one side wall.
In the method for the invention, using ion implanting or the epitaxy technique formation FinFET source and drain areas.
In the method for the invention, before the interlayer dielectric layer is formed, etching stop layer is formed.
In the method for the invention, the stack includes high-K gate insulating barrier and metal gates.
The advantage of the invention is that：, can be in the two sides of dummy gate electrode using isotropic deposition and technique is etched back to
It is upper to form the side wall that width is less than lithographic feature size；Then, after filling interlayer dielectric layer, the side wall is removed, can be with shape
Into the gate recess with sub- F sizes, and then the grid lines with Asia F sizes can be formed in gate recess.The present invention
In the case of less demanding to lithographic accuracy, you can realize the formation of Asia F size grid lines, meanwhile, relative to existing
Sub- F sizes line strip is into technique, and technological process of the invention is simple, and reliability and controllability are high.
Brief description of the drawings
The method, semi-conductor device manufacturing method flow and its structural representation of Fig. 1-7 present invention.
Embodiment
Hereinafter, the present invention is described by the specific embodiment shown in accompanying drawing.However, it should be understood that these descriptions are
Exemplary, and it is not intended to limit the scope of the present invention.In addition, in the following description, eliminate to known features and technology
Description, to avoid unnecessarily obscuring idea of the invention.
The present invention provides a kind of FinFET method, semi-conductor device manufacturing methods, uses deposition and etching technics formation small size side
Wall, and then the grid lines of small size are formed, specifically include below step：
Substrate is provided, fin, and the isolation structure between adjacent fin are formed on substrate；Form dummy gate electrode
Storehouse；The first side wall is formed on the side of dummy gate electrode storehouse；Remove dummy gate electrode storehouse；Form FinFET source-drain area
Domain；The first side wall is completely covered in comprehensive interlayer dielectric layer, interlayer dielectric layer；Interlayer dielectric layer is planarized, the is exposed
The top surface of one side wall；The first side wall is removed, gate recess is formed；Stack is formed in gate recess.
Below, the main points of manufacture method of the present invention are illustrated according to the embodiment of the present invention, its manufacturing process ginseng
See accompanying drawing 1-7, wherein, accompanying drawing 1-7 is top view.
First, fin 2 is formed on substrate 1 there is provided substrate 1 referring to accompanying drawing 1.Substrate 1 in the present invention is preferably body silicon
Substrate, in addition, other optional semi-conducting materials, such as GaN, GaAs, SiGe etc..FinFET is based on fin 2 and formed.Wherein,
The generation type of fin 2 is specially：Using patterned mask layer (not shown), anisotropic etching is carried out to substrate 1, half is formed
Conductor fin.
Then, referring to accompanying drawing 2, isolation structure 3 is formed between adjacent fin 2.Wherein, isolation structure 3 will be adjacent
Fin is kept apart, also i.e. by adjacent FinFET transistor isolations.Isolation structure 3 is, for example, STI (shallow trench isolation) structure, its
Material is the dielectrics such as silica.
Then, referring to accompanying drawing 3, dummy gate electrode storehouse 4 is formed.Wherein, dummy gate electrode storehouse 4 includes dummy gate electrode and illusory
Gate insulator, the material of dummy gate electrode is polysilicon or non-crystalline silicon, and the material of dummy gate electrode insulating barrier is silica.It is preferred that
Ground, the lines bearing of trend of dummy gate electrode storehouse 4 is vertical with the lines bearing of trend of fin 2.The formation of dummy gate electrode storehouse 4
Journey is specifically included：Successively deposition dummy gate electrode insulating barrier and the material of dummy gate electrode, using patterned mask layer as mask, etch shape
Nothing but an empty shell stack.Due to being limited by lithographic feature size F, the width W of dummy gate electrode storehouse1More than or equal to F, if with
Grid technique after being carried out based on this, will be unable to obtain the grid lines of sub- F sizes.Below, the present invention will form sub- F using side wall
The grid lines of size.
Referring to accompanying drawing 4, the first side wall 5 is formed on the side of dummy gate electrode storehouse 4.Form the specific work of the first side wall 5
Skill includes：The first spacer material layer of predetermined thickness is isotropically deposited, dummy gate electrode storehouse 4 can be completely covered in its thickness
Side and top surface；Progress is anisotropic to be etched back to technique, the first spacer material layer is only remained in dummy gate electrode storehouse 4
On side, so as to form the first side wall 5.As a result of deposition with being etched back to technique, and unconventional photoetching and etching technics,
The width W of the first side wall 5 formed2Lithographic feature size F can be less than, that is, by this step, sub- F chis can be obtained
The first very little side wall 5.Alternatively, after the first side wall 5 is formed, on the side of the first side wall 5 forming the second side wall (does not scheme
Show), there is certain offset in source and drain areas and transistor channel region for making to be subsequently formed, can improve device performance.
Then, referring to accompanying drawing 5, dummy gate electrode storehouse 4 is removed, and form FinFET source and drain areas.Dummy gate electrode storehouse 4
Wet etching selective removal can be used.The formation of FinFET source and drain areas can use ion implantation technology, can also
Formed using epitaxy technique, for example, being initially formed source and drain areas groove, then carry out source and drain areas extension and form source-drain area
Domain, or, do not form source and drain areas and directly by being epitaxially formed source and drain areas.
Then, referring to accompanying drawing 6, comprehensive interlayer dielectric layer 6, the first side wall 5 is completely covered in interlayer dielectric layer 6, this
Afterwards, interlayer dielectric layer 6 is planarized, the top surface of the first side wall 5 is exposed.Wherein, before interlayer dielectric layer 6, alternatively,
One layer of etching stop layer (CESL) (not shown) is deposited, CESL material is, for example, TEOS, and silica, silicon nitride, high K electricity is situated between
Matter, polysilicon, non-crystalline silicon etc..The material of interlayer dielectric layer 6 is preferably low-K material.
Afterwards, referring to accompanying drawing 7, the first side wall 5 is removed, gate recess 7 is formed.Alternatively, using wet etching or dry method
The first side wall 5 is removed, so as to form gate recess 7 Etch selectivity.Wherein, the material of the first side wall 5 is relative to layer
Between dielectric layer 6 have high etching selection ratio material, specifically, this step remove the first side wall technique in, the first side
The ratio between the etch rate of the material of wall 5 and the etch rate of interlayer dielectric layer 6 are more than 5: 1, it is preferable that more than 10: 1.Generally,
The material of one side wall 5 is silica, silicon nitride, high-k dielectrics, polysilicon, preferably non-crystalline silicon etc., tensile stress silicon nitride.By
Lithographic feature size can be less than in the width of the first side wall 5, therefore, the size of the gate recess 7 obtained will also be less than light
Carve characteristic size.Then, stack (not shown) is formed in gate recess 7, so as to obtain the FinFET of sub- F sizes
Grid lines.Wherein, stack include grid and gate insulator, grid be metal or metallic compound grid, for example such as
TiN, TaN, W etc., gate insulator are SiO2Or high K gate insulations, such as ZrO2, La2O3, LaAlO3, TiO2, HfO2Deng.
So far, the manufacturing process of the FinFET with Asia F size grid lines is completed.In the present invention, using it is each to
The same sex is deposited and is etched back to technique, and the side wall that width is less than lithographic feature size can be formed on the two sides of dummy gate electrode；
Then, after filling interlayer dielectric layer, the side wall is removed, the gate recess with Asia F sizes can be formed, and then can be
The grid lines with Asia F sizes are formed in gate recess.The present invention is in the case of less demanding to lithographic accuracy, you can real
The formation of existing Asia F size grid lines, meanwhile, relative to existing sub- F sizes line strip into technique, technological process of the invention
Simply, reliability and controllability are high.
The present invention is described above by reference to embodiments of the invention.But, these embodiments are used for the purpose of saying
Bright purpose, and be not intended to limit the scope of the present invention.The scope of the present invention is limited by appended claims and its equivalent.
The scope of the present invention is not departed from, those skilled in the art can make a variety of substitutions and modifications, and these substitutions and modifications should all fall
Within the scope of the present invention.
Claims (11)
1. a kind of method, semi-conductor device manufacturing method, for manufacturing FinFET, it is characterised in that comprise the following steps：
Substrate is provided, fin, and the isolation structure between the adjacent fin is formed over the substrate；
Form dummy gate electrode storehouse；
The first side wall is formed on the side of the dummy gate electrode storehouse；
Remove the dummy gate electrode storehouse；
Form FinFET source and drain areas；
First side wall is completely covered in comprehensive interlayer dielectric layer, the interlayer dielectric layer；
The interlayer dielectric layer is planarized, the top surface of first side wall is exposed；
First side wall is removed, gate recess is formed；
Stack is formed in the gate recess.
2. according to the method described in claim 1, it is characterised in that the dummy gate electrode storehouse includes dummy gate electrode, illusory grid
Pole insulating barrier.
3. according to the method described in claim 1, it is characterised in that form the first side on the side of the dummy gate electrode storehouse
The step of wall, specifically includes：
Deposit the first spacer material layer of predetermined thickness, its side for covering the dummy gate electrode storehouse and top surface；
Technique is etched back, the first spacer material layer is only remained on the side of the dummy gate electrode storehouse, so that
Form first side wall.
4. the method according to claim 1 or 3, it is characterised in that in the step of removing first side wall, using wet
Method is etched or dry etching removes first side wall, also, the etch rate and the inter-level dielectric of first side wall
The ratio between etch rate of layer is more than 5:1.
5. the method according to claim 1 or 3, it is characterised in that the etch rate of first side wall and the interlayer
The ratio between etch rate of dielectric layer is more than 10:1.
6. the method according to claim 1 or 3, it is characterised in that the material of first side wall is silica, nitridation
Silicon, high-k dielectrics, polysilicon, non-crystalline silicon.
7. according to the method described in claim 1, it is characterised in that the line size of first side wall is less than lithographic features chi
It is very little.
8. according to the method described in claim 1, it is characterised in that form the first side on the side of the dummy gate electrode storehouse
After wall, the second side wall is formed on the side of first side wall.
9. according to the method described in claim 1, it is characterised in that using ion implanting or epitaxy technique formation FinFET institute
State source and drain areas.
10. according to the method described in claim 1, it is characterised in that before the interlayer dielectric layer is formed, form etch-stop
Only layer.
11. according to the method described in claim 1, it is characterised in that the stack includes high-K gate insulating barrier and metal
Grid.
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| CN104124159B true CN104124159B (en) | 2017-11-03 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102646599A (en) * | 2012-04-09 | 2012-08-22 | 北京大学 | Preparation method of FinFET (Fin Field Effect Transistor) in large-scale integration circuit |
| CN102820230A (en) * | 2011-06-10 | 2012-12-12 | 国际商业机器公司 | Fin-last replacement metal gate FinFET |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100585178B1 (en) * | 2005-02-05 | 2006-05-30 | 삼성전자주식회사 | Semiconductor device comprising finfet having metal gate electrode and fabricating method thereof |
| JP2008066562A (en) * | 2006-09-08 | 2008-03-21 | Toshiba Corp | Semiconductor device and its manufacturing method |
| KR20100069954A (en) * | 2008-12-17 | 2010-06-25 | 삼성전자주식회사 | Method of forming a small pattern and method of manufacturing a transistor using the same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102820230A (en) * | 2011-06-10 | 2012-12-12 | 国际商业机器公司 | Fin-last replacement metal gate FinFET |
| CN102646599A (en) * | 2012-04-09 | 2012-08-22 | 北京大学 | Preparation method of FinFET (Fin Field Effect Transistor) in large-scale integration circuit |
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