CN104217667A - Test method and test system for implementing COMMAND-mode MIPI (mobile industry processor interface) modules - Google Patents
Test method and test system for implementing COMMAND-mode MIPI (mobile industry processor interface) modules Download PDFInfo
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Abstract
The invention discloses a test method and a test system for implementing COMMAND-mode MIPI (mobile industry processor interface) modules and used for configuration testing of the COMMAND-mode MIPI modules before delivery. The test method mainly includes the steps that a PG (program guidance) image generator sets register configuration parameters and image data according to types of the COMMAND-mode MIPI modules, transmits the register configuration parameters to an MCU (microprogrammed control unit), and transmits the image data to an FPGA (field programmable gate array) through an LVDS (low voltage differential signaling) data bus interface; the MCU generates DCS (data communication system) instructions according to the register configuration parameters and transmits the DCS instructions to the FPGA; the FPGA receives image data signals through the LVDS data bus interface and has the DCS instructions and the image data packaged and transmitted to a bridge chip; the bridge chip transmits the DCS instructions for configuration of the MIPI modules and converts the image data to the MIPI signals which are transmitted to the MIPI modules, and the MIPI modules display the image data according to the MIPI signals to complete testing.
Description
Technical field
The invention belongs to display field and the technical field of measurement and test of liquid crystal module, refer to a kind of the MIPI module testing method and the test macro that realize COMMAND pattern particularly.
Background technology
The display screen with MIPI interface is widely used in the modern electronic equipment such as smart mobile phone, flat board.Show in the large-scale production run of module at MIPI, configuration testing before MIPI module dispatches from the factory is a very important link, need to use the technology reading and arrange MIPI module internal register, carried out the production procedures such as some screen test, Vcom adjustment, MTP burning.The signal of input is sent to the MIPI module displays of VIDEO pattern or COMMAND pattern by inner changing the mechanism by bridging chip under VIDEO pattern or COMMAND pattern.VIDEO pattern refers to that Host Transfer arrives liquid crystal module and adopts real-time pixel stream, and is the pattern with high-speed signal transmission, and COMMAND pattern refers to adopt and sends order and data to the pattern of signal transmission of controller with display buffer.
Present stage MIPI module group test system is only applicable to the MIPI module of VIDEO pattern, the scheme be configured bridging chip adopts SPI passage and RGB data passage two autonomous channels transformation parameter configuration data and view data respectively, but, when bridging chip works in COMMAND pattern, it is in closed condition for the SPI interface transmitting configuration parameter, and therefore current MIPI module group test system can not carry out the some screen test of COMMAND pattern MIPI module.
Summary of the invention
For defect of the prior art, the present invention proposes the some screen test that can complete COMMAND pattern MIPI module, and MIPI module testing method and the test macro of the COMMAND pattern that realizes of the functions such as Vcom adjustment, module ID setting, the burning of MTP information can be carried out.
For achieving the above object, a kind of MIPI module testing method realizing COMMAND pattern designed by the present invention, its special character is, comprises the steps:
1) PG pictcure generator arranges register configuration parameter and view data according to the type of MIPI module, and register configuration parameter is sent to MCU, and view data is sent to FPGA by LVDS data bus interface;
2) described MCU produces DCS instruction according to register configuration parameter and is sent to FPGA;
3) described FPGA receives viewdata signal by LVDS data bus interface, then is sent to bridging chip after DCS instruction and view data being packed;
4) described bridging chip sends DCS instruction configuration MIPI module, and is sent to MIPI module after view data is converted into MIPI signal, and described MIPI module is according to MIPI Signal aspects view data, and test completes.
Preferably, described step 4) also comprise Vcom adjustment testing procedure afterwards: described MCU forwards to bridging chip the Vcom register parameters that DCS instruction regulates MIPI module by FPGA, makes screen flicker degree minimum.
Preferably, described step 4) also comprise MTP burning step afterwards: module ID, Gamma parameter of MIPI module, Vcom parameter and Power parameter are converted into DCS instruction and are sent to bridging chip by FPGA by described MCU, received module ID, Gamma parameter, Vcom parameter and Power parameter are sent to MIPI module according to DCS instruction by described bridging chip, and are burned onto the OTP region of MIPI module by module burning flow process.
Preferably, also comprise after described MTP burning step and read module ID step: described MCU forwards module ID, Gamma parameter in the OTP region of DCS instruction fetch MIPI module, Vcom parameter with Power parameter and one by one compared with setting value to bridging chip by FPGA, if identical, test terminates; If different, repeat MTP burning step.
A kind of for the above-mentioned test macro realizing the MIPI module testing method of COMMAND pattern, its special character is, comprise PG pictcure generator, MCU and FPGA, described PG pictcure generator is connected with MCU and FPGA respectively, described MCU and FPGA is connected by EBI interface, described FPGA is connected with MIPI module by bridging chip, and described PG pictcure generator is used for arranging register configuration parameter and view data; Described MCU is used for that the register configuration parameter received from PG pictcure generator is converted into DCS instruction and is sent to FPGA; Described FPGA is sent to bridging chip after the view data received from PG pictcure generator and DCS instruction being packed.
Further, described FPGA comprises EBI module, data processing module and sequential interface circuit, the DCS instruction received from MCU is sent to sequential interface circuit by described EBI module, the view data received from PG pictcure generator is sent to sequential interface circuit by described data processing module, and described sequential interface circuit is sent to bridging chip after DCS instruction and view data being packed.
Principle of work of the present invention is: the view data that the picture signal that PG pictcure generator sends can read through FPGA decoding generation bridging chip, MCU obtains the internal register configuration information of MIPI module from upper layer software (applications), and after configuration information is converted into DCS instruction, FPGA is sent to bridging chip in the mode forwarded after DCS instruction and view data being packed, and is finally completed the transmission of configuration parameter by the MIPI D0 passage of bridging chip.
Compared with prior art, beneficial effect of the present invention comprises:
(1) the some screen test of COMMAND pattern MIPI module can be realized;
(2) native system is by FPGA image data generating, and MCU forwards the register configuration parameter of MIPI module by FPGA, can realize register configuration parameter and view data sends at same passage;
(3) record can be carried out to the parameter arranged, the parameter that each module is arranged can be inquired easily;
(4) multi-functional: except basic some screen test function, the technical program provides the multiple test functions such as Vcom adjustment, module ID reading and preservation, MTP data edition and burning, has adapted to the multiple demand in MIPI production run.
(5) by providing comparing function, the effective guarantee accuracy of programming parameters data.
Accompanying drawing explanation
Fig. 1 is the structural representation that the present invention realizes the MIPI module group test system of COMMAND pattern.
Fig. 2 is the sequential chart that the interface signal of bridging chip and FPGA carries out write operation.
Fig. 3 is the sequential chart that the interface signal of bridging chip and FPGA carries out read operation.
In figure: 1.PG pictcure generator, 2.MCU, 3.FPGA, 3-1.EBI module, 3-2. data conversion module, 3-3. sequential interface circuit, 4. bridging chip, 5.MIPI module.
Embodiment
Below in conjunction with the drawings and specific embodiments, the present invention is described in further detail.
As shown in Figure 1, a kind of MIPI module group test system realizing COMMAND pattern of the present invention, comprise PG pictcure generator 1, MCU2 and FPGA3, PG pictcure generator 1 is connected with MCU2 and FPGA3 respectively, MCU2 and FPGA3 is connected by EBI interface, FPGA3 is connected with MIPI module 5 by bridging chip 4
PG pictcure generator 1 is for arranging register configuration parameter and view data;
MCU2 is used for that the register configuration parameter received from PG pictcure generator 1 is converted into DCS instruction and is sent to FPGA3;
FPGA3 is sent to bridging chip 4 after the view data received from PG pictcure generator 1 and DCS instruction being packed.FPGA3 comprises EBI module 3-1, data processing module 3-2 and sequential interface circuit 3-3.The DCS instruction of the EBI interface from MCU2 is sent to sequential interface circuit 3-2 by EBI module 3-1, the view data of the LVDS interface from PG pictcure generator 1 is sent to sequential interface circuit 3-3 by data processing module 3-2, and sequential interface circuit 3-3 is sent to bridging chip 4 after DCS instruction and view data being packed.Bridging chip 4 completes to configure and show view data according to DCS instruction and realizes some screen.
Image signal transmission, data-signal and power supply is connected by cable between signal source and the PG pictcure generator 1 of this test macro.PG pictcure generator 1 is sent to FPGA3 after receiving picture signal, image signal decoding is the view data that bridging chip 4 can identify by FPGA3, MCU2 obtains the internal register configuration information of MIPI module 5 from upper layer software (applications) by PG pictcure generator 1, and configuration information is converted into DCS instruction, FPGA3 is packed at DCS instruction and view data and the mode forwarded is transferred to bridging chip 4, the final transmission being completed configuration parameter by the MIPI D0 passage of bridging chip 4, MIPI module 5 shows view data.
The concrete steps utilizing above-mentioned test macro to realize the MIPI module testing method of COMMAND pattern comprise:
1) PG pictcure generator 1 arranges register configuration parameter and view data according to the type of MIPI module 5, and register configuration parameter is sent to MCU2 by 485 interfaces, and view data is sent to FPGA 3 by LVDS data bus interface;
2) MCU2 produces DCS instruction according to register configuration parameter and is sent to FPGA3;
3) FPGA3 receives picture signal from the LVDS data bus interface of PG pictcure generator 1, picture signal is converted into the view data that bridging chip 4 can identify, then is sent to bridging chip 4 after DCS instruction and view data being packed;
4) bridging chip 4 sends DCS instruction configuration MIPI module 5, and is sent to the view data that MIPI module 5, MIPI module 5 shows MIPI signal after view data is converted into MIPI signal, and the test of some screen completes.
Vcom regulates testing procedure: MCU2 to forward to bridging chip 4 the Vcom register parameters that DCS instruction regulates MIPI module 5 by FPGA3, makes screen flicker degree minimum.Vcom register belongs to the internal register of MIPI module 5, is used for the film flicker effect of MIPI module 5, can first read Vcom parameter, regulate Vcom numerical value, make the flicker level of picture minimum at upper layer software (applications) by +/-by reading order.
Module ID, Gamma parameter of MIPI module 5, Vcom parameter and Power parameter are converted into DCS instruction and are sent to bridging chip 4 by FPGA3 by MTP burning step: MCU2, received module ID, Gamma parameter, Vcom parameter and Power parameter are sent to MIPI module 5 according to DCS instruction by bridging chip 4, and are burned onto the OTP region of MIPI module 5 by module burning flow process.MIPI module 5 provides one piece of OTP region and can be used for preserving module ID, Gamma parameter, Vcom parameter, Power parameter, by arranging corresponding parameter at upper layer software (applications), and be issued to MIPI module 5, then module register is set by specific order, parameter can be burnt to OTP region, after power-down rebooting, corresponding parameter can read the corresponding registers of MIPI module 5 automatically from OTP region.
Read module ID step: MCU2 forwarded to bridging chip 4 by FPGA3 the OTP region of DCS instruction fetch MIPI module 5 module ID, Gamma parameter, Vcom parameter is with Power parameter and one by one compared with setting value, if identical, test terminates; If different, repeat MTP burning step.At host computer by DCS instruction fetch module ID, the keeping records of every block MIPI module 5 programming parameters can be realized, be convenient to analytic statistics module information.There is provided comparing window at host computer, MCU2 turns back to upper strata after the inner parameter reading MIPI module 5, guarantees desired parameters correctly burning, avoids occurring this burning and not burning, and detects the situation of burning mistake in time.
Bridging chip 4 comprises Data, rwx, dcx, e and csx with the interface signal of FPGA3, that this test macro adopts is Type A, Clocked E Mode, Fig. 2 is that bridging chip 4 carries out the sequential chart of write operation with the interface signal of FPGA3, and Fig. 3 is that bridging chip 4 carries out the sequential chart of read operation with the interface signal of FPGA3:
In Fig. 2 and Fig. 3: rwx is that 1 expression is operating as read operation, rwx is that 0 expression is operating as write operation.
E is clock signal.
Data is data signal bus.
Dcx is that 1 expression bus is data, and dcx is that 0 expression bus is order.
Csx is chip selection signal, is 0 during whole operation always.
What Command sent is the address of bridging chip 4 command register, the data of write corresponding registers that what Data sent is.
The read-write operation of MIPI module 5 register is realized by the form of DCS instruction, and conventional DCS instruction has following five kinds:
DCS?Short?WRITE?with?no?parameter
DCS?Short?WRITE?with?1parameter
Generic?Short?WRITE?with?2parameter
Generic?Long?WRITE
DCS?Long?WRITE
Such as, need the data configuring MIPI module 5 register 0xBB to be 0x1A, 0x2B, 0x3C, 0x4D, 0x5E, the register that can operate bridging chip 4 as follows according to the service manual of bridging chip 4 completes:
The operation of reading MIPI module 5 register is also realize with the form of DCS instruction, and conventional reading command has following three kinds:
DCS?Read?with?no?parameter
Generic?READ?with?1parameter
Generic?READ?with?2parameter
Such as, need the data of 5 bytes reading MIPI module 5 register 0xBB, the register that can operate bridging chip 4 as follows completes:
The numerical response that MIPIREAD 0XC6 reads BTA returns bag accepting state, numerical response that MIPIREAD 0XC2 reads BTA returns the byte number of handbag containing data, 0XFF register is the entry address of a FIFO Buffer, all returns byte by constantly reading to obtain.
MCU can realize the read-write operation to MIPI module 5 register by above-mentioned flow process, to complete some screen operation, Vcom regulates and burning, ID and Gamma burning is set.
The above is only the preferred embodiment of the present invention, it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention, can also design some improvement, and these improvement also should be considered as protection scope of the present invention.
Claims (6)
1. realize a MIPI module testing method for COMMAND pattern, it is characterized in that, comprise the steps:
1) PG pictcure generator (1) arranges register configuration parameter and view data according to the type of MIPI module (5), and register configuration parameter is sent to MCU (2), view data is sent to FPGA (3) by LVDS data bus interface;
2) described MCU (2) produces DCS instruction according to register configuration parameter and is sent to FPGA (3);
3) described FPGA (3) receives view data by LVDS data bus interface, then is sent to bridging chip (4) after DCS instruction and view data being packed;
4) described bridging chip (4) sends DCS instruction configuration MIPI module (5), and after view data is converted into MIPI signal, be sent to MIPI module (5), described MIPI module (5) is according to MIPI Signal aspects view data, and test completes.
2. the MIPI module testing method realizing COMMAND pattern according to claim 1, it is characterized in that: described step 4) also comprise Vcom adjustment testing procedure: described MCU (2) forwards DCS instruction adjustment MIPI module (5) to bridging chip (4) Vcom register parameters by FPGA (3) afterwards, make screen flicker degree minimum.
3. the MIPI module testing method realizing COMMAND pattern according to claim 1, it is characterized in that: described step 4) also comprise MTP burning step afterwards: described MCU (2) is by the module ID of MIPI module (5), Gamma parameter, Vcom parameter and Power parameter are converted into DCS instruction and are sent to bridging chip (4) by FPGA (3), described bridging chip (4) according to DCS instruction by received module ID, Gamma parameter, Vcom parameter and Power parameter are sent to MIPI module (5), and the OTP region of MIPI module (5) is burned onto by module burning flow process.
4. the MIPI module testing method realizing COMMAND pattern according to claim 3, it is characterized in that: also comprise after described MTP burning step and read module ID step: described MCU (2) forwards module ID, Gamma parameter in the OTP region of DCS instruction fetch MIPI module (5), Vcom parameter with Power parameter and one by one compared with setting value to bridging chip (4) by FPGA (3), if identical, test terminates; If different, repeat MTP burning step.
5. one kind for the above-mentioned test macro realizing the MIPI module testing method of COMMAND pattern, it is characterized in that: comprise PG pictcure generator (1), MCU (2) and FPGA (3), described PG pictcure generator (1) is connected with MCU (2) and FPGA (3) respectively, described MCU (2) is connected by EBI interface with FPGA (3), described FPGA (3) is connected with MIPI module (5) by bridging chip (4)
Described PG pictcure generator (1) is for arranging register configuration parameter and view data;
Described MCU (2) is sent to FPGA (3) for the register configuration parameter received from PG pictcure generator (1) is converted into DCS instruction;
Described FPGA (3) is sent to bridging chip (4) after the view data received from PG pictcure generator (1) and DCS instruction being packed.
6. the MIPI module group test system realizing COMMAND pattern according to claim 5, it is characterized in that: described FPGA (3) comprises EBI module (3-1), data processing module (3-2) and sequential interface circuit (3-3), the DCS instruction received from MCU (2) is sent to sequential interface circuit (3-2) by described EBI module (3-1), the view data received from PG pictcure generator (1) is sent to sequential interface circuit (3-3) by described data processing module (3-2), described sequential interface circuit (3-3) is sent to bridging chip (4) after DCS instruction and view data being packed.
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Address after: 430070 Hubei City, Hongshan Province, South Lake Road, No. 53, Hongshan Venture Center, building on the 4 floor, No. Patentee after: Wuhan fine test electronics group Limited by Share Ltd Address before: 430070 Hubei City, Hongshan Province, South Lake Road, No. 53, Hongshan Venture Center, building on the 4 floor, No. Patentee before: Wuhan Jingce Electronic Technology Co., Ltd. |