CN104216847A - Data acquisition method and data acquisition system - Google Patents
Data acquisition method and data acquisition system Download PDFInfo
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- CN104216847A CN104216847A CN201410447191.6A CN201410447191A CN104216847A CN 104216847 A CN104216847 A CN 104216847A CN 201410447191 A CN201410447191 A CN 201410447191A CN 104216847 A CN104216847 A CN 104216847A
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Abstract
The invention discloses a data acquisition method. Respectively independent chip selection signals of all analog-to-digital conversion chips are not needed any more, and read control signals are counted, so that the analog-to-digital conversion chips are subjected to chip selection according to a counting result, and equivalently, the multiple conventional chip selection signals and a conventional RD signal are combined to form a new read control signal; therefore transmission signals of a system are greatly reduced, so that system connection wires and IO (input/output) interfaces are reduced; during cascading of multiple plate cards, the advantage is particularly outstanding. The invention also discloses a data acquisition system.
Description
Technical field
The present invention relates to data collecting field, particularly relate to a kind of collecting method and data acquisition system (DAS).
Background technology
Some equipment of common electric system; such as industrial rank radio transmission apparatus (Data Transfer unit; DTU), protective relaying device and fault oscillograph etc., all need data acquisition board, AD sampling plate is wherein the most frequently used one.Traditional AD sampling plate, every block board has 3 A/D chip (analog-digital chip) usually.The signal of every block board has synchronous sampling signal SMP, is used for sampling time of synchronous each chip; Read control signal RD (comprising pulse signal), be used for controlling the digital independent of every block board; CS0, CS1, CS2 be totally 3 chip selection signals for A/D chip.Wherein, SMP and RD is the signal that all boards all share, and CS0, CS1, CS2 are that every block board has independently signal.In addition, the signal of output has: export data, the signal DATA that the output data of all boards are synthesized by data bus; BUSY signal is every block board independently signal; Board inserts detection signal ON, is every block board independently signal.Amount to the signal that every block board independently uses and have 5, the signal that all boards share has 2, and the total data bus of all boards is 1 group.
Above-mentioned traditional AD sampling plate, control device (source) and the AD method of sampling, there is following shortcoming: (1) uses an independently chip selection signal due to each A/D chip, the signal transmission of system is more thus cause line more, also require that A/D chip and control device have more I/O interface, make manufacturing cost, installation cost and handling cost higher, also easily cause the crosstalk between line.When the cascade of polylith board, this shortcoming is particularly outstanding, and such as control device needs the number of the board connected to be n block, and tentation data bus is 16, then the I/O interface quantity that control device needs altogether is 5*n+2+16=5*n+18.(2) control signal (SMP and RD) shared owing to being receive 1 more, and load (board) is more, and the reflection of different loads to signal is different, easily produces ring.Time particularly frequency is higher, the impact of ringing is just larger.The frequency of such as 10K, ring time is 50ns, then only account for 0.5% of the whole clock period; And the frequency of 10M, ring time, 50ns, then just account for 50% of the whole clock period ring time.When ring, control device sends a pulse, and board just likely receives 2 or multiple pulse.Because be the load of multiple branch, when carrying out designing impedance matching, the position that build-out resistor is placed cannot reach the optimal properties of each branch, and the distance of each branch distance control device is different, intensity and the reflection interval of reflection are different, further increase the difficulty of coupling.(3) whether ON signal can only detect board and insert, and function singleness, does not effectively utilize the line of system.
Summary of the invention
Based on this, be necessary that providing a kind of reduces the signal transmission of system thus the collecting method of minimizing system line and I/O interface.Secondly, a kind of data acquisition system (DAS) is also disclosed.
A kind of collecting method, based on data acquisition system (DAS), described data acquisition system (DAS) comprises the harvester and control device that intercom mutually, and described harvester comprises the modulus conversion chip of plural M passage, comprises step:
Described control device sends synchronous sampling signal to harvester and reads control signal; Described reading control signal synchronous sampling signal trigger sampling after, time delay preset duration output pulse signal;
First pulse signal rear panel that described harvester is receiving described reading control signal selects first modulus conversion chip, described harvester also counts described pulse signal, when count value is the N times of port number M of modulus conversion chip, then sheet selects N+1 modulus conversion chip, and wherein N is positive integer; Often read a described pulse signal, the image data of the passage collected by the current modulus conversion chip chosen is sent to control device.
Wherein in an embodiment, described control device sends synchronous sampling signal to multiple harvester simultaneously and reads control signal.
Wherein in an embodiment, described preset duration is greater than the maximum transfer delay of described modulus conversion chip.
A kind of data acquisition system (DAS), comprising:
Control device, for sending synchronous sampling signal and reading control signal; Described reading control signal synchronous sampling signal trigger sampling after, time delay preset duration output pulse signal;
Harvester, comprises the described modulus conversion chip of two or more M passage; First pulse signal rear panel that described harvester receives described reading control signal selects first modulus conversion chip, described harvester also counts described pulse signal, when count value is the N times of port number M of modulus conversion chip, then sheet selects N+1 modulus conversion chip, and wherein N is positive integer; Often read a described pulse signal, the image data of the passage collected by the current modulus conversion chip chosen is sent to control device.
Wherein in an embodiment, described harvester also comprises counter and decoder;
The reading of described modulus conversion chip controls receiving port and receives described reading control signal;
The reset terminal of described counter receives described synchronous sampling signal, and the pulse input end of described counter receives described reading control signal, and the high M position output terminal of described counter connects the input end of described code translator; Wherein, M is positive integer;
The output terminal of described code translator connects the sheet choosing end of corresponding described modulus conversion chip.
Wherein in an embodiment, comprise harvester described in a described control device and two or more, described control device comprises the reading control output end mouth corresponding with harvester quantity, the corresponding described harvester of each reading control output end mouth, described reading control output end mouth connects corresponding described harvester respectively.
Wherein in an embodiment, each described harvester correspondence configuration one group of build-out resistor.
Wherein in an embodiment, described harvester also comprises testing circuit and serial data transtation mission circuit; Described testing circuit is for gathering the device information of described harvester, and described device information sends to described control device by described serial data transtation mission circuit; Described device information comprises at least one in the BUSY signal of described modulus conversion chip, harvester version number, harvester type, harvester error message, temperature information, humidity information.
Wherein in an embodiment, described serial data transtation mission circuit uses the asynchronous communication method presetting baud rate to send described device information.
Wherein in an embodiment, the model of described modulus conversion chip is AD7606 or ADS8568, and described preset duration is greater than 4 microseconds.
Above-mentioned collecting method and data acquisition system (DAS), no longer need each modulus conversion chip chip selection signal independently, but from by reading control signal count, then carry out sheet according to count results and select each modulus conversion chip, this is equivalent to traditional multiple chip selection signal and traditional RD signal to merge into a new reading control signal, drastically reduce the area the signal transmission of system thus reduce system line and I/O interface, when the cascade of polylith board, this advantage is particularly outstanding.
Accompanying drawing explanation
Fig. 1 is the collecting method process flow diagram of an embodiment;
Fig. 2 is the data acquisition system (DAS) schematic diagram of an embodiment;
Fig. 3 is the signal timing diagram of an embodiment;
Fig. 4 is the data acquisition system (DAS) module map of an embodiment.
Embodiment
For the ease of understanding the present invention, below with reference to relevant drawings, the present invention is described more fully.Preferred embodiment of the present invention is given in accompanying drawing.But the present invention can realize in many different forms, is not limited to embodiment described herein.On the contrary, provide the object of these embodiments be make the understanding of disclosure of the present invention more comprehensively thorough.
Unless otherwise defined, all technology used herein and scientific terminology are identical with belonging to the implication that those skilled in the art of the present invention understand usually.The object of term used in the description of the invention herein just in order to describe specific embodiment, is not intended to limit the present invention.Term as used herein "and/or" comprises arbitrary and all combinations of one or more relevant Listed Items.
A kind of collecting method, based on data acquisition system (DAS), data acquisition system (DAS) comprises the harvester and control device that intercom mutually, and harvester comprises the modulus conversion chip of plural M passage, comprises step:
Control device sends synchronous sampling signal to harvester and reads control signal; Read control signal after synchronous sampling signal triggers sampling, time delay preset duration output pulse signal.
First pulse signal rear panel that harvester is receiving reading control signal selects first modulus conversion chip, harvester also pulse signals counts, when count value is the N times of port number M of modulus conversion chip, then sheet selects N+1 modulus conversion chip, and wherein N is positive integer; Often read a pulse signal, the image data of the passage collected by the current modulus conversion chip chosen is sent to control device.
Above-mentioned collecting method, no longer need each modulus conversion chip chip selection signal independently, but from by reading control signal count, then carry out sheet according to count results and select each modulus conversion chip, this is equivalent to traditional multiple chip selection signal and traditional RD signal to merge into a new reading control signal, drastically reduce the area the signal transmission of system thus reduce system line and I/O interface, when the cascade of polylith board, this advantage is particularly outstanding.
Fig. 1 is the collecting method process flow diagram of an embodiment, and Fig. 2 is the data acquisition system (DAS) module map of an embodiment, and Fig. 3 is the signal timing diagram of an embodiment.Incorporated by reference to Fig. 1, Fig. 2 and Fig. 3.
A kind of collecting method, based on data acquisition system (DAS), data acquisition system (DAS) comprises the harvester 200 and control device 100 that intercom mutually, harvester 200 comprises the modulus conversion chip (AD1 of the M passage of K (two or more), AD2, AD3), comprise step:
Step S100: control device 100 sends synchronous sampling signal SMP and reads control signal RDC.Read control signal RDC after synchronous sampling signal SMP triggers sampling, time delay preset duration output pulse signal.
Synchronous sampling signal SMP comprises a trigger pip, and trigger pip is rising edge or negative edge (being negative edge in the present embodiment).Read control signal RDC and be divided into signal front part RDC+ and signal aft section RDC-, RDC+ part in signal front is level signal (being high level signal in the present embodiment), and signal aft section RDC-is pulse signal.From the moment that trigger pip occurs, in preset duration T, read the part that control signal RDC is signal front part RDC+.
At the negative edge of SMP signal, each modulus conversion chip (AD1, AD2, AD3) of harvester 200 all imports the data sampled (A1, A2, A3) into sampling holder (not shown).Import the data sampled (A1, A2, A3) into sampling holder and need the regular hour, so need transfer delay.Arrange preset duration according to modulus conversion chip type, the maximum transfer delay of such as AD7606 probably needs 4 μ s, and ADS8365 probably needs 3.2 μ s.So in the present embodiment, preset duration T is greater than 4 μ s, is preferably greater than and equals 4.5 μ s.
Step S200: first pulse signal rear panel that harvester 200 is receiving reading control signal RDC selects first modulus conversion chip AD1, harvester 200 also pulse signals counts.At the present embodiment for reading a rising edge, count a pulse.
Step S300: judge to count whether to the port number M of modulus conversion chip N doubly, if then perform step S400.M is the sampling channel number of modulus conversion chip, have 8 sampling channels then M be just 8.
Step S400: when counting up to the N times of M, then sheet selects N+1 modulus conversion chip, and wherein N is positive integer.Often read a pulse signal (at the present embodiment for reading a rising edge, count a pulse), the image data of one of them passage that N+1 the modulus conversion chip just sending sheet choosing collects, the image data DATA of each passage collected by N+1 modulus conversion chip is successively sent to control device 100.Harvester 200 comprises K (two or more) modulus conversion chip AD1 ~ ADk, and wherein K is positive integer, is 3 in the present embodiment.Time system is incipient, acquiescence sheet selects first modulus conversion chip AD1.
Just there is the sampled data of a passage to export control device 100 (source) to from data bus when reading control signal RDC rising edge, thus when negative edge, sampled data must be put into data bus.
When counting up to the N times of M, show all selected transmission of the sampled data DATA of all sampling channels of N number of modulus conversion chip, now need sheet to select next modulus conversion chip, namely sheet selects N+1 modulus conversion chip.
Suppose that each modulus conversion chip can gather 8 passages, then detailed process is as follows: control device sends SMP signal, then judges whether the board of certain position inserts.Detect and produce trigger pip and trigger T=4.5 μ s after inserting, time delay terminates RDC signal and starts to become pulse signal from level signal, counting pulse signal.At the negative edge of pulse signal, the sampled data of first modulus conversion chip AD1 passage is put into data bus, export this sampled data DATA to control device 100 from data bus at the rising edge of pulse signal.After reading the sampled data of first whole 8 passage of modulus conversion chip AD1, count pulse is also 1 times of 8, thus sheet selects second modulus conversion chip AD2, the pulse signal continuing through RDC signal reads the sampled data of second modulus conversion chip AD2, reads the sampled data of the 3rd modulus conversion chip AD3 by that analogy again.After running through, continue detect and read next harvester.
Fig. 4 is the data acquisition system (DAS) module map of an embodiment.In the present embodiment, comprise a control device 100 and L (L is integer) harvester (201,202 ... 20L), each harvester correspondence configuration one group of build-out resistor (R1, R2 ... RL), control device 100 comprises L and reads control output end mouth (RDC1, RDC2 ... RDCL), the corresponding harvester of each reading control output end mouth, reads control output end mouth and exports reading control signal respectively to corresponding harvester.Because RDC signal is each harvester independently signal, namely control device 100 (source) is man-to-man relation to harvester (terminal), more easily carries out terminal impedance coupling, thus eliminates the impact of reflection on system.
The present invention also discloses a kind of data acquisition system (DAS).
Refer to Fig. 2, a kind of data acquisition system (DAS), comprise control device 100 and harvester 200.Harvester 200 comprises K (two or more) modulus conversion chip (AD1, AD2, AD3), and wherein K is positive integer, is 3 in the present embodiment.The model of modulus conversion chip is AD7606 or ADS8568.
Harvester 200 also comprises counter and decoder.The reading of modulus conversion chip controls receiving port RD and receives reading control signal RDC, the reset terminal RST of the synchronized sampling port SMP sum counter of modulus conversion chip receives synchronous sampling signal SMP, the pulse input end CK of counter receives reading control signal RDC, high M=2 position output terminal B3 with B4 of counter and is connected input end C1 and C2 of code translator.Wherein, M is positive integer, meets K≤2
m, M=2 in the present embodiment.All the other output terminals (B0, B1 and B2) of counter are unsettled.
Code translator is 2-4 code translator, and the output terminal (S1, S2, S3) of code translator connects the sheet choosing end of corresponding modulus conversion chip respectively, and unnecessary output terminal S4 is unsettled.
Control device 100 sends synchronous sampling signal SMP and reads control signal RDC.Read control signal RDC after synchronous sampling signal SMP triggers sampling, time delay preset duration output pulse signal.
Refer to Fig. 3, synchronous sampling signal SMP comprises a trigger pip, and trigger pip is rising edge or negative edge (being negative edge in the present embodiment).Read control signal RDC and be divided into signal front part RDC+ and signal aft section RDC-, RDC+ part in signal front is level signal (being high level signal in the present embodiment), and signal aft section RDC-is pulse signal.From the moment that trigger pip occurs, in preset duration T, read the part that control signal RDC is signal front part RDC1.
At the negative edge of SMP signal, each modulus conversion chip (AD1, AD2, AD3) of harvester 200 all imports the data sampled (A1, A2, A3) into sampling holder (not shown).Import the data sampled (A1, A2, A3) into sampling holder and need the regular hour, so need transfer delay.Arrange preset duration according to modulus conversion chip type, the maximum transfer delay of such as AD7606 probably needs 4 μ s, and ADS8365 probably needs 3.2 μ s.So in the present embodiment, preset duration T is greater than 4 μ s, is preferably greater than and equals 4.5 μ s.
Harvester 200 receives and reads control signal RDC, and pulse signals counts.At the present embodiment for reading a rising edge, count a pulse.Judge to count whether to M N doubly, if then perform step S400.M is the sampling channel number of modulus conversion chip, have 8 sampling channels then M be just 8.When counting up to the N times of M, then sheet selects N+1 modulus conversion chip, and wherein N is positive integer.Often read a pulse signal (at the present embodiment for reading a rising edge, count a pulse), the image data of one of them passage that N+1 the modulus conversion chip just sending sheet choosing collects, the image data DATA of each passage collected by N+1 modulus conversion chip is successively sent to control device 100.System is incipient time, and acquiescence sheet selects first modulus conversion chip AD1.
Just there is the sampled data of a passage to export control device 100 (source) to from data bus when reading control signal RDC rising edge, thus when negative edge, sampled data must be put into data bus.
When counting up to the N times of M, show all selected transmission of the sampled data DATA of all sampling channels of N number of modulus conversion chip, now need sheet to select next modulus conversion chip, namely sheet selects N+1 modulus conversion chip.
Suppose that each modulus conversion chip can gather 8 passages, then detailed process is as follows: control device sends SMP signal, then judges whether the board of certain position inserts.Detect and produce trigger pip and trigger T=4.5 μ s after inserting, time delay terminates RDC signal and starts to become pulse signal from level signal, counting pulse signal.At the negative edge of pulse signal, the sampled data of first modulus conversion chip AD1 passage is put into data bus, export this sampled data DATA to control device 100 from data bus at the rising edge of pulse signal.After reading the sampled data of first whole 8 passage of modulus conversion chip AD1, count pulse is also 1 times of 8, thus sheet selects second modulus conversion chip AD2, the pulse signal continuing through RDC signal reads the sampled data of second modulus conversion chip AD2, reads the sampled data of the 3rd modulus conversion chip AD3 by that analogy again.After running through, continue detect and read next harvester.
Compared with traditional each modulus conversion chip of reading successively, be here by harvester 200 integrally device read data in order.Such as harvester has 3 modulus conversion chips, and each 8 sampling channels, then send the pulse signal of 24 RDC signals.Be 0 when counter is initial, select first modulus conversion chip AD1.Count at the rising edge of pulse signal, count value 0-7 selects first modulus conversion chip AD1, and count value 8-15 second chip AD2, count value 16-23 select the 3rd chip AD3.According to the count value of the counter shown in table 1, select the 1st modulus conversion chip AD1 when B4 and B3 is 00, when being 01, select second modulus conversion chip AD2, need when being 10 to select the 3rd modulus conversion chip AD3.Can find out according to the truth table of the 2-4 code translator shown in table 2, the value of C1 and C2 is 00 when sheet selects first modulus conversion chip AD1, time sheet selects second modulus conversion chip DA2, value is 01, when sheet selects the 3rd chip AD3, value is 10, so only need B3 with C1 to be connected, B4 with C2 is connected.
| Count value | B4 | B3 | B2-B0 | Modulus conversion chip |
| 0-7 | 0 | 0 | 000-111 | AD1 |
| 8-15 | 0 | 1 | 000-111 | AD2 |
| 16-23 | 1 | 0 | 000-111 | AD3 |
Table 1
| C2 | C1 | S4 | S3 | S2 | S1 |
| 0 | 0 | 1 | 1 | 1 | 0 |
| 0 | 1 | 1 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 1 | 1 | 1 |
Table 2
In the present embodiment, harvester 200 also comprises testing circuit and serial data transtation mission circuit.Testing circuit is for gathering the device information INFO of this harvester 200, and device information INFO sends to control device 100 by serial data transtation mission circuit.Device information INFO comprises at least one in the BUSY signal of K modulus conversion chip, harvester version number, harvester type, harvester error message, temperature information, humidity information.Serial data transtation mission circuit uses the asynchronous communication method dispensing device information INFO presetting baud rate, such as relevant to the UART interface means of communication.Preset baud rate and use conventional baud rate, such as 9600bps, 115200bps etc.The device information INFO function newly increased, convenient management, debugging and after sale service.Alarm can be sent to the up-set condition of harvester, and the information such as the version of harvester and the position of insertion can be inquired whether meet system requirements etc.Even can provide long-range failure message statistics, the work of convenient management and after sale service.
Harvester 200, receiving synchronous sampling signal SMP and needing to carry out buffered to it after reading control signal RDC, also needs buffered before device information INFO and sampled data DATA sends.
Refer to Fig. 4.In the present embodiment, data acquisition system (DAS) comprises a control device 100 and L harvester (201,202 ... 20L), each harvester correspondence configuration one group of build-out resistor (R1, R2 ... RL), control device 100 comprises L and reads control output end mouth (RDC1, RDC2 ... RDCL), the corresponding harvester of each reading control output end mouth, read control output end mouth and export reading control signal respectively to corresponding harvester, read control output end mouth and connect corresponding harvester respectively.Because RDC signal is each harvester independently signal, namely control device (source) is man-to-man relation to harvester (terminal), more easily carries out terminal impedance coupling, thus eliminates the impact of reflection on system.As Fig. 4, build-out resistor can be placed in harvester, more convenient.One-to-many bus is at a high speed converted into the man-to-man interface of high speed, makes system cloud gray model more stable.
Above-mentioned collecting method and data acquisition system (DAS), no longer need each modulus conversion chip chip selection signal independently, but from by reading control signal count, then carry out sheet according to count results and select each modulus conversion chip, this is equivalent to traditional multiple chip selection signal and traditional RD signal to merge into a new reading control signal, drastically reduce the area the signal transmission of system thus reduce system line and I/O interface, when the cascade of polylith board, this advantage is particularly outstanding, such as control device needs the number of the board connected to be n block, tentation data bus is 16, the I/O interface quantity that then control device needs altogether is 2*n+17, significantly be less than traditional 5*n+18, considerably reduce manufacturing cost, installation cost and handling cost, reduce the crosstalk between line.
The above embodiment only have expressed several embodiment of the present invention, and it describes comparatively concrete and detailed, but therefore can not be interpreted as the restriction to the scope of the claims of the present invention.It should be pointed out that for the person of ordinary skill of the art, without departing from the inventive concept of the premise, can also make some distortion and improvement, these all belong to protection scope of the present invention.Therefore, the protection domain of patent of the present invention should be as the criterion with claims.
Claims (10)
1. a collecting method, based on data acquisition system (DAS), described data acquisition system (DAS) comprises the harvester and control device that intercom mutually, and described harvester comprises the modulus conversion chip of plural M passage, it is characterized in that, comprises step:
Described control device sends synchronous sampling signal to harvester and reads control signal; Described reading control signal synchronous sampling signal trigger sampling after, time delay preset duration output pulse signal;
First pulse signal rear panel that described harvester is receiving described reading control signal selects first modulus conversion chip, described harvester also counts described pulse signal, when count value is the N times of port number M of modulus conversion chip, then sheet selects N+1 modulus conversion chip, and wherein N is positive integer; Often read a described pulse signal, the image data of the passage collected by the current modulus conversion chip chosen is sent to control device.
2. collecting method according to claim 1, is characterized in that: described control device sends synchronous sampling signal to multiple harvester simultaneously and reads control signal.
3. collecting method according to claim 1, is characterized in that, described preset duration is greater than the maximum transfer delay of described modulus conversion chip.
4. a data acquisition system (DAS), is characterized in that, comprising:
Control device, for sending synchronous sampling signal and reading control signal; Described reading control signal synchronous sampling signal trigger sampling after, time delay preset duration output pulse signal;
Harvester, comprises the described modulus conversion chip of two or more M passage; First pulse signal rear panel that described harvester receives described reading control signal selects first modulus conversion chip, described harvester also counts described pulse signal, when count value is the N times of port number M of modulus conversion chip, then sheet selects N+1 modulus conversion chip, and wherein N is positive integer; Often read a described pulse signal, the image data of the passage collected by the current modulus conversion chip chosen is sent to control device.
5. data acquisition system (DAS) according to claim 4, is characterized in that, described harvester also comprises counter and decoder;
The reading of described modulus conversion chip controls receiving port and receives described reading control signal;
The reset terminal of described counter receives described synchronous sampling signal, and the pulse input end of described counter receives described reading control signal, and the high M position output terminal of described counter connects the input end of described code translator; Wherein, M is positive integer;
The output terminal of described code translator connects the sheet choosing end of corresponding described modulus conversion chip.
6. data acquisition system (DAS) according to claim 4, it is characterized in that, comprise harvester described in a described control device and two or more, described control device comprises the reading control output end mouth corresponding with harvester quantity, the corresponding described harvester of each reading control output end mouth, described reading control output end mouth connects corresponding described harvester respectively.
7. data acquisition system (DAS) according to claim 6, is characterized in that, each described harvester correspondence configuration one group of build-out resistor.
8. data acquisition system (DAS) according to claim 4, is characterized in that, described harvester also comprises testing circuit and serial data transtation mission circuit; Described testing circuit is for gathering the device information of described harvester, and described device information sends to described control device by described serial data transtation mission circuit; Described device information comprises at least one in the BUSY signal of described modulus conversion chip, harvester version number, harvester type, harvester error message, temperature information, humidity information.
9. data acquisition system (DAS) according to claim 8, is characterized in that, described serial data transtation mission circuit uses the asynchronous communication method presetting baud rate to send described device information.
10. the data acquisition system (DAS) according to any one of claim 4 ~ 9, is characterized in that, the model of described modulus conversion chip is AD7606 or ADS8568, and described preset duration is greater than 4 microseconds.
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Application publication date: 20141217 |