CN104201877B - The time-delay method of a kind of input undervoltage protection circuit and circuit - Google Patents

Abstract

It is an object of the invention to provide the delay circuit of a kind of input undervoltage protection circuit; module and pulse output control module is set up including sampled voltage; described sampled voltage is set up module and is followed soft start terminal voltage Vss by output voltage feedback end voltage VFB, to set up sampled voltage Vp；Described pulse output control module receives sampled voltage Vp, and after comparing sampled voltage Vp and setting value, output signal controls the shutoff/opening of GATE end.The invention has the beneficial effects as follows before soft start terminates, after UVP signal is come, GATE end does not have output, and the output voltage moment of power supply also would not be made to have a rising, thus avoids the impact that late-class circuit causes by false triggering.

Description

The time-delay method of a kind of input undervoltage protection circuit and circuit

Technical field

The present invention relates to integrated circuit, particularly to the control chip of a kind of tape input under-voltage protecting circuit.

Background technology

The Chinese invention patent application of Publication No. CN103986320 disclosed in 13 days Augusts in 2014 discloses a kind of Switching Power Supply Remote control circuit, this circuit has under-voltage protection function, as it is shown in figure 1, include switching power source control circuit 1, voltage sample electricity Road 2 and remote control port circuit 3.Wherein switching power source control circuit 1 comprises control IC, this control IC is a existing switch electricity Source control chip, can have under-voltage according to the State-output certain frequency of circuit, the driving pulse of certain dutycycle, this chip Defencive function, is to detect the input current of this end by under-voltage protection end UVP end to realize under-voltage protection function.

The part controlling to realize inside IC under-voltage protection function is input voltage protection circuit, and its theory diagram is as in figure 2 it is shown, can To find out, current sampling circuit outfan is connected to delay circuit, and the Main Function of delay circuit is the anti-of the electrostatic of intensifier circuit Interference performance.Because when beating negative electrostatic at remote control foot REM, the pulsewidth of electrostatic pulse is generally nanosecond ns level, the negative pressure at A Relatively big, add diode parasitic capacitance effect so that the negative pressure of A point is held time length, is μ s level during this period of time, at 150 μ s Left and right, can be considered input undervoltage the most always, easily triggers input undervoltage protection by mistake, causes under electric power output voltage Fall.In order to avoid protection by mistake, delay time can be arranged on 200 μ about s.Avoiding problems positive negative sense electrostatic pulse to pass through Disturb internal under-pressure protection circuit after delay circuit, thus further avoid and cause misoperation and power cutoff module, it is ensured that Module safety reliably working.But delay time also should not design oversize, system response time otherwise will be made slack-off.

Further, since the input undervoltage protection circuit in control chip is provided with delay circuit, delay circuit typically by resistance and Electric capacity forms, even if there being low level interference signal pulse, the persistent period is 100 μ about s, enters control chip, also Circuit will be delayed by filter and do not affect normal circuit operation, and on the other hand delay circuit can disturb with filtering circuit, carry The capacity of resisting disturbance of high under-voltage protecting circuit.

But being intended to make delay circuit, when chip startup or module resets, chip internal will be to electric capacity, d type flip flop, counting Devices etc. carry out initialization process, again because when chip startup or module resets, it is ensured that chip normally works, and does not enters Any guard mode, so just must be initialized as non-input undervoltage state, but is initialized as non-input undervoltage state, Can there is a problem in that sequential chart as shown in Figure 3, ENP_lv represents low-voltage module initializing signal, initializes after terminating as height Level；VIN_fault_L represents input undervoltage detection signal, Low level effective；UVIN_L represents under-voltage protection control signal, Low level effective；GATE is output pulse signal.When chip opens machine or module resets, initializing signal ENP_lv is low Level, is initialized as non-input undervoltage state, i.e. VIN_fault_L signal is high level, and this stage is not receive under-voltage protection Signal UVIN_L's, chip can normally work, i.e. GATE end can export pulse by normal condition.I.e. start or mould at chip During block reset, under-voltage protection function does not enable.But it is set during this period of time, once to occur that input voltage is less than When put under-voltage, i.e. input voltage vin < preset under-voltage value, then UVP signal UVIN_L is low level, now due to UVP signal UVIN_L is shielded by initializing signal, so that GATE end is in runaway condition, i.e. GATE end is still So having pulse output, power supply has the output voltage of moment and rises, and causes false triggering late-class circuit, impacts power supply, And do not meet power source performance index request.

Summary of the invention

It is an object of the invention to provide the time-delay method of a kind of input undervoltage protection circuit, before initializing signal terminates, owe After pressure protection signal is come, the GATE end of controller IC does not have output, to avoid false triggering to cause late-class circuit Impact.

Corresponding to this, it is a further object to provide the delay circuit of a kind of input undervoltage protection circuit, initializing Before signal ended, after UVP signal is come, the GATE end of controller IC does not have output, to avoid false triggering The impact that late-class circuit is caused.

To achieve these goals, the present invention is realized by techniques below measure, the time delay side of a kind of input undervoltage protection circuit Method, comprises the steps,

Sampled voltage establishment step, when soft start terminal voltage Vss slowly rises, output voltage feedback end voltage VFB follows soft opening Moved end voltage Vss, when conducting voltage Vbe1 of output voltage feedback end voltage VFB ＜ the first audion, makes the first audion Turn off, then the sampled voltage Vp set up after dividing potential drop by emitter voltage drop Ve of the first audion is zero；When output voltage feeds back During conducting voltage Vbe1 of terminal voltage VFB ＞ the first audion, make the first triode ON, then by the emitter stage of the first audion Pressure drop Ve sets up sampled voltage Vp after dividing potential drop；

Pulse output rate-determining steps, receives sampled voltage Vp, and compares sampled voltage Vp with setting value, when sampling electricity During pressure Vp ＜ setting value, comparator output low level signal, the most do not allow GATE end output pulse signal；Work as sampled voltage During Vp ＞ setting value, comparator output high level signal, then allow GATE end output pulse signal.

Preferably, in described sampled voltage establishment step, the slow rising of soft start terminal voltage Vss, is to be led to by the first current source Cross the output of soft start end, in order to charge to external capacitor, slowly to set up soft start terminal voltage Vss.

Preferably, in described pulse output rate-determining steps, setting value is second current source pressure drop Vcs at the 4th resistance.

For circuit, the present invention provides the delay circuit of a kind of input undervoltage protection circuit, including sampled voltage set up module and Pulse output control module, described sampled voltage sets up module and has output voltage feedback end and soft start end, and described pulse is defeated Go out control module and there is pulse output end,

Described sampled voltage sets up module, and when soft start terminal voltage Vss slowly rises, output voltage feedback end voltage VFB follows Soft start terminal voltage Vss, when conducting voltage Vbe1 of output voltage feedback end voltage VFB ＜ the first audion, makes the one or three Pole pipe turns off, then the sampled voltage Vp set up after dividing potential drop by emitter voltage drop Ve of the first audion is zero；Work as output voltage During conducting voltage Vbe1 of feedback end voltage VFB ＞ the first audion, make the first triode ON, then sending out by the first audion Emitter voltage drop Ve sets up sampled voltage Vp after dividing potential drop；

Described pulse output control module, receives sampled voltage Vp, and compares sampled voltage Vp with setting value, when adopting During sample voltage Vp ＜ setting value, comparator output low level signal, the most do not allow GATE end output pulse signal；Work as sampling During voltage Vp ＞ setting value, comparator output high level signal, then allow GATE end output pulse signal.

Preferably, the sampled voltage of the delay circuit of described input undervoltage protection circuit sets up module, including: the first current source, First power end, the first audion, the second audion, operational amplifier, the first resistance, the second resistance and the 3rd resistance, The outfan of the first current source emitter stage with soft start end and the second audion respectively is connected, and the colelctor electrode of the second audion divides Be not connected with the base stage of the second audion and the positive input terminal of operational amplifier, the negative input end of this operational amplifier respectively with fortune Calculating the outfan of amplifier and output voltage feedback end connects, the outfan of operational amplifier is also with the base stage of the first audion even Connecing, the colelctor electrode of the first audion and base stage short circuit, the colelctor electrode of the first audion connects the first power supply also by the first resistance End；The emitter stage of the first audion is by the second resistance connected and the 3rd resistance eutral grounding.

Preferably, the pulse output control module of the delay circuit of described input undervoltage protection circuit, comprise the second current source, Two power ends, under-voltage protection control signal end, initializing signal end, the 4th resistance, comparator, the first NAND gate, second NAND gate, the 3rd NAND gate and phase inverter, the second current source negative input end with the 4th resistance and comparator respectively is connected, than The positive input terminal of relatively device is connected between the second resistance and the 3rd resistance；Under-voltage protection control signal end is connected with second source end The input of one NAND gate, the outfan of the first NAND gate is connected the input of the second NAND gate with initializing signal end, and second The outfan of NAND gate is connected the input of the 3rd NAND gate with the outfan of comparator, and the outfan of the 3rd NAND gate connects anti- The input of phase device, the outfan of phase inverter connects GATE end.

Preferably, the another kind of sampled voltage of the delay circuit of described input undervoltage protection circuit sets up module, including: first Current source, the first power end, the first audion, operational amplifier, the first resistance, the second resistance, the 3rd resistance, first The outfan of current source positive input terminal with soft start end and operational amplifier respectively is connected, and the negative input end of operational amplifier divides Be not connected with outfan and the output voltage feedback end of operational amplifier, the outfan of operational amplifier also with the first audion Base stage connects, the colelctor electrode of the first audion and base stage short circuit, and the colelctor electrode of the first audion connects the also by the first resistance One power end；The emitter stage of the first audion is by the second resistance connected and the 3rd resistance eutral grounding.

The time-delay method of input undervoltage protection circuit of the present invention and having the beneficial effects that of circuit: efficiently utilize on VFB voltage The a period of time risen, during this period of time at Microsecond grade, receive input undervoltage protection signal, it is to avoid when chip starts or mould During block reset, the initializing signal shielding to input undervoltage protection signal, efficiently avoid input undervoltage defencive function and lost efficacy, And then avoid result in GATE end and have output, make the output voltage moment of power supply have rising, and then cause late-class circuit false triggering Phenomenon.

Accompanying drawing explanation

Fig. 1 is the circuit diagram of existing a kind of Switching Power Supply remote control circuit；

Fig. 2 is input voltage protection circuit figure in existing a controller IC；

Fig. 3 is the sequential chart of input voltage protection coherent signal in existing a controller IC；

Fig. 4 is the circuit diagram of the delay circuit of the input undervoltage protection circuit of the embodiment of the present invention one；

Fig. 5 is the circuit diagram of the delay circuit of the input undervoltage protection circuit of the embodiment of the present invention two.

Detailed description of the invention

In order to make the purpose of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, to this Invention further describes.Should be appreciated that specific embodiment described herein, and need not only in order to explain the present invention In limiting the present invention.

Embodiment one

As shown in Figure 4, for the circuit diagram of the embodiment of the present invention one.A kind of input utilizing the change of FB terminal voltage VFB to produce is owed The delay circuit of voltage protection circuit, sets up module and pulse output control module including sampled voltage, and sampled voltage sets up module There is FB end (also known as output voltage feedback end, the most together simply referred to as FB end) and SS end (also known as soft start end, below Together simply referred to as SS end), pulse output control module have GATE end (also known as pulse output end, the most together simply referred to as GATE End),

Sampled voltage sets up module, when SS terminal voltage Vss slowly rises, when SS terminal voltage Vss rises to the conducting of audion Q2 During voltage Vbe2, audion Q2 opens, and the output end voltage of operational amplifier A MP2 follows its positive input terminal voltage, i.e. FB end Voltage VFB follows SS terminal voltage Vss,

When conducting voltage Vbe1 of FB terminal voltage VFB ＜ audion Q1, represent that FB terminal voltage VFB is introduced into steady statue, Make audion Q1 turn off, then the sampled voltage Vp set up after dividing potential drop by emitter voltage drop Ve of audion Q1 is zero；

When conducting voltage Vbe1 of FB terminal voltage VFB ＞ audion Q1, represent that FB terminal voltage VFB comes into stable shape State, makes audion Q1 turn on, then set up sampled voltage Vp after dividing potential drop by emitter voltage drop Ve of audion Q1；

Pulse output control module, receives sampled voltage Vp, and compares sampled voltage Vp with setting value, and setting value is Current source Icom pressure drop Vcs on resistance R4,

When sampled voltage Vp ＜ setting value, comparator COMP output low level signal, the most do not allow GATE end to export pulse Signal；

When sampled voltage Vp ＞ setting value, comparator COMP exports high level signal, then allow GATE end output pulse letter Number.

Wherein, sampled voltage sets up module 101, including: current source Iss, power end VCCA, audion Q1 and Q2, fortune Calculate amplifier AMP2, resistance R1, R2 and R3, the outfan of current source Iss respectively with SS end and the transmitting of audion Q2 Pole connects, and the colelctor electrode of audion Q2 is connected with the base stage of audion Q2 and the positive input terminal of operational amplifier A MP2 respectively, The negative input end of this operational amplifier A MP2 is connected with outfan and the FB end of operational amplifier A MP2 respectively, operational amplifier The outfan of AMP2 also base stage with audion Q1 is connected, the colelctor electrode of audion Q1 and base stage short circuit, the collection of audion Q1 Electrode meets power end VCCA also by resistance R1；The emitter stage of audion Q1 is by the resistance R2 connected and resistance R3 ground connection；

Pulse output control module 102, comprise current source Icom, power end Vcc, under-voltage protection control signal end UVIN_L, Initializing signal end, resistance R4, comparator COMP, NAND gate NAND1, NAND2, NAND3 and phase inverter NOT, electric current Icom negative input end with resistance R4 and comparator COMP respectively in source is connected, and the positive input terminal of comparator COMP is connected to resistance Between R2 and resistance R3 (at the point of B shown in figure)；Under-voltage protection control signal end UVIN_L is connected NAND gate with power Vcc The input of NAND1, the outfan of NAND gate NAND1 is connected the input of NAND gate NAND2 with initializing signal end ENP_lv End, the outfan of NAND gate NAND2 is connected the input of NAND gate NAND3, NAND gate NAND3 with the outfan of comparator COMP Outfan connect the input of phase inverter NOT, the outfan of phase inverter NOT connects GATE end.

The delay control method of the input undervoltage protection circuit of the embodiment of the present invention one is: comprise the steps,

Sampled voltage establishment step, when SS terminal voltage Vss slowly rises, when SS terminal voltage Vss rises to the conducting of audion Q2 During voltage Vbe2, audion Q2 opens, and the output end voltage of operational amplifier A MP2 follows its positive input terminal voltage, i.e. FB end Voltage VFB follows SS terminal voltage Vss,

When conducting voltage Vbe1 of FB terminal voltage VFB ＜ audion Q1, represent that FB terminal voltage VFB is introduced into steady statue, Make audion Q1 turn off, emitter voltage drop Ve of audion Q1 the sampled voltage Vp set up after dividing potential drop is zero；

When conducting voltage Vbe1 of FB terminal voltage VFB ＞ audion Q1, represent that FB terminal voltage VFB comes into stable shape State, makes audion Q1 turn on, emitter voltage drop Ve of audion Q1 set up sampled voltage Vp after dividing potential drop；

Pulse output rate-determining steps, receives sampled voltage Vp, and compares sampled voltage Vp with setting value, and setting value is Current source Icom pressure drop Vcs on resistance R4,

When sampled voltage Vp ＜ setting value, comparator COMP output low level signal, the most do not allow GATE end to export pulse Signal；

As sampled voltage Vp ＞ current source Icom pressure drop Vcs on resistance R4, comparator COMP exports high level signal, Then allow GATE end output pulse signal.

Preferably, in sampled voltage establishment step, the slow rising of soft start terminal voltage Vss, is to be passed through by the first current source Soft start end exports, in order to charge to external capacitor, slowly to set up soft start terminal voltage Vss.

The operation principle of the delay circuit of input undervoltage protection circuit of the present invention is, it is assumed that SS end external capacitor Css, to ground, works as control After device processed starts, current source Iss charges to external capacitor Css, makes SS terminal voltage Vss slowly increase；Delay in SS terminal voltage Vss When rising to conducting voltage Vbe2 of audion Q2 slowly, audion Q2 opens, and the output end voltage of operational amplifier A MP2 is followed Its positive input terminal voltage, i.e. FB terminal voltage VFB follows SS terminal voltage Vss, and operational amplifier A MP2 is as voltage follower herein Using, before soft start terminates, or after UVP signal, initializing signal are come, GATE end does not have output, Specific works process is as follows,

When Vss rises above Vbe2 when, audion Q2 opens, and when FB terminal voltage VFB is more than Vbe1, opens Open audion Q1, then the positive input terminal voltage Vp of comparator COMP begins to ramp up；And the negative input end of comparator COMP connects Current source Icom pressure drop Vcs on resistance R4, its value is:

V_CS≈I_com·R₄ (1)

The voltage produced through resistance pressure-dividing network due to VFB voltage, its value is:

$V_P=\frac{V_{\mathrm{FB}}-V_{\mathrm{bel}}}{R_2+R_3}\&CenterDot;\frac{1}{R_3}---\left(2\right)$

Here the value under Vbe1 is the base-emitter drop of NPN type triode Q1, room temperature is at about 0.7V.At V_PElectricity When pressure is just set up, positive input terminal voltage < the negative input end voltage, i.e. V of comparator COMP_P<V_CS, COMP is defeated for this comparator Go out low level signal, turn off GATE end.Positive input terminal voltage as comparator COMP > negative input end voltage, i.e. V_P>V_CS, This comparator COMP exports high level signal, open GATE end, it is allowed to GATE end output pulse signal.According to Fig. 4, Utilize capacitor charge and discharge formula

I_SS·T_SS=C_SS·V_FB (3)

Can calculate the soft time of opening is:

$T_{\mathrm{SS}}=\frac{V_{\mathrm{FB}}\&CenterDot;C_{\mathrm{SS}}}{I_{\mathrm{SS}}}---\left(4\right)$

Due to this delay circuit utilize soft start voltage Vss of SS end to set up sampled voltage Vp, i.e. soft start voltage Vss liter To the cut-in voltage Vbe2 of audion Q2, (Vbe2 is the base-emitter drop of NPN type triode Q2, the value under room temperature At about 0.7V, now the positive input terminal voltage of amplifier AMP2 is about 0.7V), FB terminal voltage VFB follows amplifier AMP2 Positive input terminal voltage, i.e. FB terminal voltage VFB begins to ramp up from 0.7V, during until rising to setting value, thus utilizes FB The synchronized relation of terminal voltage VFB, sampled voltage Vp and soft start voltage Vss, it is ensured that delay time is set at Microsecond grade, Thus ensured the rapid response speed of Circuits System.

Again owing to beginning to ramp up from 0V in soft start voltage Vss, during until rising to setting value, such as chip start or During module resets, pulse output control module 102 responds input undervoltage protection signal, does not allow GATE end output pulse signal, Avoid initialization signal and the shielding of input undervoltage protection signal is caused the GATE end output by mistake controlling IC, i.e. eliminate Circuit is introduced into the GATE end link out of control during steady statue, thus avoids the output voltage moment of power supply to have rising, and then keeps away Exempt from the therefore phenomenon of the late-class circuit false triggering caused.

On the other hand, FB terminal voltage VFB directly begins to ramp up from 0.7V, accelerates and opens the machine time.And due to this delay circuit The absolute time delay not being independently of start-up circuit and produce, but the relative time delay followed soft start and produce, eliminating electricity Outside GATE end link out of control during the non-steady statue in road, also better ensure the Synchronization Control of input undervoltage protection and soft start. Separately do not comprise capacitor element due to this delay circuit, it is easier to the realization that circuit is integrated, and the Miniaturization Design of integrated circuit.

Embodiment two

As it is shown in figure 5, compared with embodiment one, the difference of the delay circuit of the present embodiment input undervoltage protection circuit is: adopt In sample Voltage Establishment module 201, eliminate audion Q2, i.e. sampled voltage and set up module, including: current source Iss, electricity Source VCCA, audion Q1, operational amplifier A MP2, resistance R1, R2 and R3, the outfan of current source Iss respectively with The positive input terminal of SS end and operational amplifier A MP2 connects, the negative input end of this operational amplifier A MP2 respectively with operation amplifier The outfan of device AMP2 and FB end connect, and the outfan of operational amplifier A MP2 also base stage with audion Q1 is connected, and three The colelctor electrode of pole pipe Q1 and base stage short circuit, the colelctor electrode of audion Q1 connects power end VCCA also by resistance R1；Audion The emitter stage of Q1 is by the resistance R2 connected and resistance R3 ground connection.Owing to the positive input terminal of operational amplifier A MP2 is directly connected to SS end and the outfan of current source Iss, such FB terminal voltage VFB follows directly after the change of SS terminal voltage Vss, when FB end When voltage VFB changes from 0 to 0.7V, audion Q1 is not turned on, and the positive input terminal voltage of comparator COMP is not the most built Vertical, and that comparator COMP negative input termination is the pressure drop Vcs that produces on resistance R4 of current source Icom, its value such as formula (1), shown in, so comparator COMP is output as low level, GATE is turned off；When FB terminal voltage VFB > Vbe1 time, than The positive input terminal voltage of relatively device COMP is the most slowly set up, but still less than its negative input end voltage Vcs, only as (VFB-Vbe1) The pressure drop Vp produced on divider resistance R3 is (i.e.) more than (mistake of consideration comparator during Vcs voltage Adjust voltage), comparator COMP just can overturn, and just can open GATE end.

Advantage of this embodiment is that, FB terminal voltage VFB follows directly after soft start voltage Vss, and its value excursion is big, Ye Jiyan Time the time longer, more fully ensure that and do not terminate at initializing signal, input undervoltage protection signal arrive during this period of time In, GATE end does not have pulse output, and output voltage would not rise, and then will not false triggering following stage circuit, it is ensured that The safe and reliable work of whole circuit module.

Embodiments of the present invention are not limited to this, according to the foregoing of the present invention, utilize this area ordinary technical knowledge and Customary means, without departing under the present invention above-mentioned basic fundamental thought premise, the present invention can also make other various ways Revise, replace or change, within the scope of all falling within rights protection of the present invention.

Claims (7)

1. a time-delay method for input undervoltage protection circuit, comprises the steps,

Sampled voltage establishment step, when soft start terminal voltage Vss slowly rises, output voltage feedback end voltage VFB follows soft Start end voltage Vss,

When conducting voltage Vbe1 of output voltage feedback end voltage VFB ＜ the first audion, the first audion is made to turn off, then The sampled voltage Vp set up after dividing potential drop by emitter voltage drop Ve of the first audion is zero；

When conducting voltage Vbe1 of output voltage feedback end voltage VFB ＞ the first audion, make the first triode ON, then After dividing potential drop, sampled voltage Vp is set up by emitter voltage drop Ve of the first audion；

Pulse output rate-determining steps, receives sampled voltage Vp, and compares sampled voltage Vp with setting value,

When sampled voltage Vp ＜ setting value, comparator output low level signal, the most do not allow GATE end output pulse signal；

When sampled voltage Vp ＞ setting value, comparator output high level signal, then allow GATE end output pulse signal.

The time-delay method of input undervoltage protection circuit the most according to claim 1, is characterized in that: described sampled voltage is set up In step, the slow rising of soft start terminal voltage Vss, is to be exported by soft start end by the first current source, in order to external electricity Capacity charge, slowly to set up soft start terminal voltage Vss.

The time-delay method of input undervoltage protection circuit the most according to claim 1, is characterized in that: described pulse output controls In step, setting value is second current source pressure drop Vcs at the 4th resistance.

4. a delay circuit for input undervoltage protection circuit, is characterized in that, sets up module and pulse output including sampled voltage Control module, described sampled voltage is set up module and is had output voltage feedback end and soft start end, described pulse output control module There is pulse output end,

Described sampled voltage sets up module, when soft start terminal voltage Vss slowly rises, output voltage feedback end voltage VFB with With soft start terminal voltage Vss,

When conducting voltage Vbe1 of output voltage feedback end voltage VFB ＜ the first audion, the first audion is made to turn off, then The sampled voltage Vp set up after dividing potential drop by emitter voltage drop Ve of the first audion is zero；

When conducting voltage Vbe1 of output voltage feedback end voltage VFB ＞ the first audion, make the first triode ON, then After dividing potential drop, sampled voltage Vp is set up by emitter voltage drop Ve of the first audion；

Described pulse output control module, receives sampled voltage Vp, and compares sampled voltage Vp with setting value,

When sampled voltage Vp ＜ setting value, comparator output low level signal, the most do not allow GATE end output pulse signal；

When sampled voltage Vp ＞ setting value, comparator output high level signal, then allow GATE end output pulse signal.

The delay circuit of input undervoltage protection circuit the most according to claim 4, is characterized in that:

Described sampled voltage sets up module, including: the first current source, the first power end, the first audion, the second audion, Operational amplifier, the first resistance, the second resistance and the 3rd resistance, the outfan of the first current source respectively with soft start end and The emitter stage of two audions connects, and the colelctor electrode of the second audion is respectively with the base stage of the second audion and operational amplifier just Input connects, and the negative input end of this operational amplifier is connected with outfan and the output voltage feedback end of operational amplifier respectively, The outfan of operational amplifier also base stage with the first audion is connected, the colelctor electrode of the first audion and base stage short circuit, and first The colelctor electrode of audion connects the first power end also by the first resistance；The emitter stage of the first audion the second electricity by series connection Resistance and the 3rd resistance eutral grounding.

6., according to the delay circuit of the input undervoltage protection circuit described in claim 4 or 5, it is characterized in that:

Described pulse output control module, comprises the second current source, second source end, under-voltage protection control signal end, initialization Signal end, the 4th resistance, comparator, the first NAND gate, the second NAND gate, the 3rd NAND gate and phase inverter, the second electric current Source negative input end with the 4th resistance and comparator respectively is connected, and the positive input terminal of comparator is connected to the second resistance and the 3rd resistance Between；Under-voltage protection control signal end is connected the input of the first NAND gate, the outfan of the first NAND gate with second source end With the input that initializing signal end is connected the second NAND gate, the outfan of the second NAND gate is connected with the outfan of comparator The input of three NAND gate, the outfan of the 3rd NAND gate connects the input of phase inverter, and the outfan of phase inverter connects GATE End.

The delay circuit of input undervoltage protection circuit the most according to claim 4, is characterized in that:

Described sampled voltage sets up module, including: the first current source, the first power end, the first audion, operational amplifier, First resistance, the second resistance, the 3rd resistance, the outfan of the first current source is respectively with soft start end and operational amplifier just Input connects, and the negative input end of operational amplifier is connected with outfan and the output voltage feedback end of operational amplifier respectively, The outfan of operational amplifier also base stage with the first audion is connected, the colelctor electrode of the first audion and base stage short circuit, and first The colelctor electrode of audion connects the first power end also by the first resistance；The emitter stage of the first audion the second electricity by series connection Resistance and the 3rd resistance eutral grounding.