CN104201197B - A kind of silicon carbide bipolar transistor - Google Patents
A kind of silicon carbide bipolar transistor Download PDFInfo
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- CN104201197B CN104201197B CN201410425765.XA CN201410425765A CN104201197B CN 104201197 B CN104201197 B CN 104201197B CN 201410425765 A CN201410425765 A CN 201410425765A CN 104201197 B CN104201197 B CN 104201197B
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 41
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims description 14
- 230000003071 parasitic effect Effects 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 2
- 230000006798 recombination Effects 0.000 abstract description 8
- 238000005215 recombination Methods 0.000 abstract description 8
- 238000000034 method Methods 0.000 abstract description 6
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 230000009286 beneficial effect Effects 0.000 abstract description 3
- 238000010276 construction Methods 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 description 10
- 229910052906 cristobalite Inorganic materials 0.000 description 10
- 239000000377 silicon dioxide Substances 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 229910052682 stishovite Inorganic materials 0.000 description 10
- 229910052905 tridymite Inorganic materials 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 9
- 238000002161 passivation Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 7
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 238000001465 metallisation Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 3
- 230000005527 interface trap Effects 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000003321 amplification Effects 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 229940090044 injection Drugs 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 230000032258 transport Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
- 230000004223 radioprotective effect Effects 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 238000003949 trap density measurement Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/0405—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising semiconducting carbon, e.g. diamond, diamond-like carbon
- H01L21/0425—Making electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
Abstract
The present invention relates to technical field of semiconductors, particularly relate to a kind of silicon carbide bipolar transistor.The silicon carbide bipolar transistor of the present invention, it is characterised in that at N+Launch site 205 and P+P between doped region 207‑Base 204 upper surface is provided with N+Epitaxial layer 210；Described N+Epitaxial layer 210 upper surface is provided with N+Epitaxial layer electrode 211；Described base stage 208 and N+Epitaxial layer 210 and N+Between epitaxial layer electrode 211, N+Epitaxial layer 210 and N+Epitaxial layer electrode 211 and N+SiO is passed through between launch site 205 and emitter stage 2062Dielectric layer 209 is isolated.Beneficial effects of the present invention is, can be effectively reduced surface recombination, improve current gain, simultaneously its simple in construction, is easier to realize in technique.Present invention is particularly suitable for silicon carbide bipolar transistor.
Description
Technical field
The invention belongs to technical field of semiconductors, particularly relate to a kind of silicon carbide bipolar transistor.
Background technology
Since in recent years, along with the fast development of microelectric technique, Development of Novel large power semiconductor device is increasingly by people
Concern, the application to device simultaneously also improves requirement.As third generation quasiconductor, carbofrax material has broad-band gap, height
The outstanding advantages such as electronics saturation drift velocity, high heat conductance, high critical breakdown electric field, be particularly suitable for making high-power, high frequency,
High temperature semiconductor device.Power electronic devices based on SiC material has the features such as high, high temperature resistant, the radioprotective of output,
Power electronic devices can be made to have the ability worked under greater power, smaller volume and more mal-condition.
Silicon carbide bipolar transistor npn npn (SiC BJT) is a kind of electric current control, normally-off device, by two back-to-back PN junctions
Composition, is divided into launch site, base and collecting zone three part.During device work, base injects a small amount of electric current, at launch site and collection
Bigger electric current will be formed between electricity district, thus reach to amplify the effect of electric current.Excellent due to the feature of device itself and material
Gesture, it is low that SiC BJT has conducting resistance, and electric current density is high, the feature that switching speed is fast.
Improve constantly pressure and current amplification factor, reduce the problem received much concern in conducting resistance always SiC BJT research.
In recent years, the research to SiC BJT also has made great progress, but still has the biggest problem not also to be fully solved at present.Commercialization
The obstacle that SiC BJT currently mainly exists is electrical property degenerate problem under the conditions of working long hours, show current gain reduce and
The raising of conducting resistance.Wherein outer base area etch areas SiC/SiO2Interface trap is one on the generation impact that transports of base carrier
Individual important reason.As a example by NPN pipe, when device is opened, substantial amounts of electronics is injected base by emitter stage, arrives outer base area table
During face, by SiC/SiO2Interface trap is captured, and with the hole of base, Surface combination effect occurs, and produces surface recombination current.
Surface recombination current is a part for base current, and base current can be caused to increase, and current gain reduces.Interface trap simultaneously
Existence can affect the life-span of carrier, can affect the current gain of device further, ultimately result in device degradation.
Except constantly to improve technique, reduce the interface trap density of states after the etching of outer base area and improve beyond device performance, it is also possible to
Start with from device architecture, reduce interfacial state impact.The United States Patent (USP) of Application No. 7345310B2 discloses one base outside
The SiC BJT structure of district's deposit one floor SiC passivation layer；Its main technical schemes is to utilize the built-in electricity between passivation layer and base
Gesture so that passivation layer is from exhausting, and the most complete depletion of passivation layer is by SiO2Dielectric layer separates with outer base area so that SiO2Medium
Layer directly can not contact with outer base area, and in the passivation layer simultaneously exhausted, free carrier is the most depleted, will not pass through SiO2Medium
Trap between layer and passivation layer produces complex effect.But due to the Built-in potential between SiC passivation layer and outer base area only
2.7V, need by passivation layer all from exhaust be accomplished by passivation layer thickness and concentration harsher requirement proposed, therefore its
Practicality is poor.
Summary of the invention
The purpose of the present invention, it is simply that the problem existed for above-mentioned Conventional silicon carbide bipolar transistor, proposing one can effectively drop
Low surface recombination, the silicon carbide bipolar transistor of raising current gain.
The technical scheme is that, a kind of silicon carbide bipolar transistor, including N+Substrate 202, it is arranged on N+Substrate 202
The N on upper strata-Drift region 203 and be arranged on N-The P on upper strata, drift region 203-Base 204；Described N+Substrate 202 lower surface is arranged
There is colelctor electrode 201；Described P-Upper surface middle part, base 204 is provided with N+Launch site 205, the both sides on its upper strata are respectively provided with
There is P+Doped region 207；Described N+Launch site 205 upper surface is provided with emitter stage 206；Described P+Doped region 207 upper surface is arranged
There is base stage 208；It is characterized in that, at N+Launch site 205 and P+P between doped region 207-Base 204 upper surface is provided with
N+Epitaxial layer 210；Described N+Epitaxial layer 210 upper surface is provided with N+Epitaxial layer electrode 211；Described base stage 208 and N+Epitaxial layer
210 and N+Between epitaxial layer electrode 211, N+Epitaxial layer 210 and N+Epitaxial layer electrode 211 and N+Launch site 205 and emitter stage
SiO is passed through between 2062Dielectric layer 209 is isolated.
The technical scheme that the present invention is total, by P-Surface, base 204 one layer of N contrary with base doping type of extension+Epitaxial layer
210 form parasitic diode, and at N+N is deposited on epitaxial layer 210+Epitaxial layer electrode 211.Apply voltage by external circuit, make
Parasitic diode is reverse-biased, controls P-The width of base 204 depletion layer on one side suppresses surface carrier concentration.Diode is anti-simultaneously
Partially, electric current it is possible to prevent to flow through from outer base area parasitic diode and affect device performance.Owing to the reverse-biased degree of parasitic diode can
Control with the size by regulation external voltage, so outer base area surface epitaxial layer concentration can be the highest, ohm can be directly used as
Contact is without carrying out high concentration ion injection；Additionally thickness requirement need not the thinnest, it is simple to technologic realization.
In the inventive solutions, N+Launch site 205 width can not be excessive, it is to avoid can not have because of edge-crowding effect of current
Effect utilizes N+The area of launch site 205；The doping content of launch site should be much larger than P-The doping content of base 204 is to improve transmitting
Efficiency, but simultaneously need to avoid the generation of band gap narrowing；N+Launch site 205 table top and base metallization 208 distance can not
The nearest, it is to avoid bigger electron concentration gradient makes base current increase and reduce current gain；P-The width of base 204 can not
The widest, in order to avoid reducing transport coefficient；
N+Epitaxial layer 210 and N+SiO is used respectively between launch site 205 and base metallization 2082Dielectric layer 209 separates.Separately
Outer N+The doping type of epitaxial layer 210 and P-Base 204 is identical and N+Launch site 205 is identical, and doping content can be with N+Send out
Penetrate district 205 identical.
Wherein N+Launch site 205, P-Base 204, N-Drift region 203 all by being epitaxially formed, N+Epitaxial layer 210 and N+Launch
District 205 can concurrently form, it is also possible to is formed by selective epitaxial.
When device is opened, a large amount of electronics pass through P-Base enters N-Drift region 203, produces conductivity modulation effect；During device work
Base N+Epitaxial layer metallic electrode 211 applies malleation, N+Epitaxial layer 210 and P-The parasitic diode formed between base 204
Reverse-biased, outer base area surface depletion.
Beneficial effects of the present invention is, can be effectively reduced surface recombination, improve current gain, simultaneously its simple in construction,
It is easier in technique realize.
Accompanying drawing explanation
Fig. 1 is traditional silicon carbide bipolar transistor npn npn structural representation；
Fig. 2 is the silicon carbide bipolar transistor npn npn structural representation of the present invention；
Fig. 3 is the silicon carbide bipolar transistor npn npn structure of the present invention and traditional silicon carbide bipolar transistor npn npn structure current gain
(Current Gain) and base current (IB) along with collector current (IC) the simulation curve figure that changes；
Fig. 4 be the present invention silicon carbide bipolar transistor npn npn fabrication processing in substrat structure schematic diagram；
Fig. 5 be the present invention silicon carbide bipolar transistor npn npn fabrication processing on substrate, generate drift region, base and transmitting
Structural representation behind district；
Fig. 6 be the present invention silicon carbide bipolar transistor npn npn fabrication processing in etch structural representation behind launch site；
Fig. 7 be the present invention silicon carbide bipolar transistor npn npn fabrication processing in after base growing epitaxial layers structural representation；
Fig. 8 be the present invention silicon carbide bipolar transistor npn npn fabrication processing in generate structure after heavily doped region at two ends, base and show
It is intended to；
Fig. 9 be the present invention silicon carbide bipolar transistor npn npn fabrication processing in deposit SiO2Structural representation after dielectric layer；
Figure 10 be the present invention silicon carbide bipolar transistor npn npn fabrication processing in etch SiO2Medium, generates metal contact hole,
And deposit structural representation after metal generation base stage, epitaxial layer electrode, emitter stage；
Figure 11 be the present invention silicon carbide bipolar transistor npn npn fabrication processing in structural representation after spanning set electrode.
Detailed description of the invention
Below in conjunction with the accompanying drawings the detailed description of the invention of the present invention is described
Fig. 1 is traditional silicon carbide bipolar transistor npn npn structure；Including colelctor electrode 101, N+Substrate 102, N-Drift region 103,
P-Base 104, N+Launch site 105, emitter stage 106, P+Doping 107, base stage 108, SiO2Dielectric layer 109.What it existed asks
Topic is, when device is opened, substantial amounts of electronics is injected base by emitter stage, when arriving surface, outer base area, by SiO2Interface trap is captureed
Obtain, and with the hole of base, Surface combination effect occurs, produce surface recombination current.Surface recombination current is the one of base current
Part, can cause base current to increase, and current gain reduces.The existence of interface trap simultaneously can affect the life-span of carrier, meeting
Affect the current gain of device further, ultimately result in device degradation.
Fig. 2 is the silicon carbide bipolar transistor npn npn structure of the present invention, including N+Substrate 202, it is arranged on N+Substrate 202 upper strata
N-Drift region 203 and be arranged on N-The P on upper strata, drift region 203-Base 204；Described N+Substrate 202 lower surface is provided with colelctor electrode
201；Described P-Upper surface middle part, base 204 is provided with N+Launch site 205, the both sides on its upper strata are respectively arranged with P+Doping
District 207；Described N+Launch site 205 upper surface is provided with emitter stage 206；Described P+Doped region 207 upper surface is provided with base stage
208；At N+Launch site 205 and P+P between doped region 207-Base 204 upper surface is provided with N+Epitaxial layer 210；Described N+
Epitaxial layer 210 upper surface is provided with N+Epitaxial layer electrode 211；Described base stage 208 and N+Epitaxial layer 210 and N+Epitaxial layer electrode
Between 211, N+Epitaxial layer 210 and N+Epitaxial layer electrode 211 and N+SiO is passed through between launch site 205 and emitter stage 2062Medium
Layer 209 isolation.
The operation principle of the present invention is:
In the silicon carbide bipolar transistor npn npn of the present invention, there is one by N+Epitaxial layer 210 and P-The parasitism two of base 204 composition
Pole is managed.When device is opened, a large amount of electronics are injected P by launch site 205-Base 204, a part of electronics enters N by base-
Drift region 203 is also finally collected by colelctor electrode；And another part can spread in base inner transverse.Now N+Epitaxial layer metallizes
Electrode 211 applies voltage by external circuit makes N+Epitaxial layer 210 and P-The parasitic diode that base 204 is formed is reverse-biased, makes P-Base
District 204 surface depletion.The electronics of horizontal proliferation and P-Hole in base 204 body cannot be near surface, outer base area.Regulate additional
The size of voltage can control P-Base 204 surface depletion layer width, makes carrier away from surface, outer base area, reduces recombination current.
N+Epitaxial layer 210 concentration is the biggest, to P-The depletion width extended in base 204 body is the biggest, is more conducive to carrier remote
From surface, N+Epitaxial layer 210 concentration can be with N+Launch site 205 is identical, and the two doping type is identical simultaneously, so N+Epitaxial layer
210 can be formed by the way of etching.Additionally P-Base 204 surface depletion layer width is mainly by N+Epitaxial layer metallic electrode
211 applied voltages control, N+The thickness of epitaxial layer 210 can be relatively big, is beneficial to technologic control.
As it is shown on figure 3, compared with traditional device, the device current gain of the present invention is greatly improved, equal colelctor electrode electricity
Stream (ICBase current (I under)B) be obviously reduced, as it is shown on figure 3, wherein, lines be hollow equilateral triangle for the present invention
The amplification of device is along with collector current (IC) change curve, lines are the base for device of the present invention of open squares
Electrode current (IB) along with collector current (IC) change curve, lines are the times magnification for traditional devices of filled inverted triangles
Number is along with collector current (IC) change curve, lines are to realize the circular base current (I for traditional devicesB) along with collection
Electrode current (IC) change curve.
The fabrication processing of the silicon carbide bipolar transistor npn npn of the present invention is:
1, SiC substrate prepares, and uses N-type heavy doping 4H-SiC substrate 401, and doping content is 1 × 1019cm-3, crystal orientation (0001),
Thickness is 5 μm, as shown in Figure 4；
2, use vapour phase epitaxy method, N-type heavy doping 4H-SiC substrate 401 uses continuous extension, form N-Drift region 402,
Thickness is 15 μm, and concentration is 5 × 1015cm-3；P-Base 403, thickness 1 μm, concentration 2 × 1017cm-3；N+Launch site 404,
Thickness 1 μm, concentration 3 × 1019cm-3, as shown in Figure 5.
3, reactive ion etching method is used, launch site mesa structure at etching, as shown in Figure 6；
4, carry out selective epitaxial growth and form N+Epitaxial layer 405, thickness is 0.3 μm, concentration 3 × 1019cm-3, such as Fig. 7 institute
Show；
5, Al ion is used to form P+Heavy doping 406, peak doping concentration is 1 × 1019cm-3, then in ar gas environment,
1600 DEG C of short annealings 5 minutes, activate and inject ion, as shown in Figure 8.
6, use chemical vapor deposition, deposit SiO2Dielectric layer 407, as shown in Figure 9.
7, formation base stage, emitter stage and N are performed etching+Epitaxial layer metal contact hole.Deposit base metallization 408, N+Epitaxial layer
Metal electrode 409, metallization emitter stage 410, metal is nickel, as shown in Figure 10.
8, deposit metallic nickel in the back side forms metallization colelctor electrode 411, as shown in figure 11.
Claims (1)
1. a silicon carbide bipolar transistor, including N+Substrate (202), it is arranged on N+The N on substrate (202) upper strata-Drift
District (203) and be arranged on N-The P on drift region (203) upper strata-Base (204)；Described N+Substrate (202) lower surface is provided with
Colelctor electrode (201)；Described P-Base (204) upper surface middle part is provided with N+Launch site (205), the both sides on its upper strata are divided
It is not provided with P+Doped region (207)；Described N+Launch site (205) upper surface is provided with emitter stage (206)；Described P+Doped region
(207) upper surface is provided with base stage (208)；It is characterized in that, at N+Launch site (205) and P+Between doped region (207)
P-Base (204) upper surface is provided with N+Epitaxial layer (210)；Described N+Epitaxial layer (210) upper surface is provided with N+Extension
Layer electrode (211)；Described base stage (208) and N+Epitaxial layer (210) and N+Between epitaxial layer electrode (211), N+Epitaxial layer
And N (210)+Epitaxial layer electrode (211) and N+SiO is passed through between launch site (205) and emitter stage (206)2Dielectric layer (209)
Isolation；Described N+Epitaxial layer (210) and P-Base (204) composition parasitic diode, described N+Epitaxial layer electrode (211) is used
In time opening at device, apply voltage by external circuit and make N+Epitaxial layer (210) and P-Parasitism two pole that base (204) forms
Manage reverse-biased, make P-Base (204) surface depletion, makes electronics and the P of horizontal proliferation-Internal hole, base (204) cannot be leaned on
Nearly surface, outer base area.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410425765.XA CN104201197B (en) | 2014-08-26 | 2014-08-26 | A kind of silicon carbide bipolar transistor |
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| CN201410425765.XA CN104201197B (en) | 2014-08-26 | 2014-08-26 | A kind of silicon carbide bipolar transistor |
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| CN104201197B true CN104201197B (en) | 2016-10-05 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102132388A (en) * | 2008-08-26 | 2011-07-20 | 本田技研工业株式会社 | Bipolar semiconductor device and method for manufacturing same |
| CN102610638A (en) * | 2012-03-22 | 2012-07-25 | 西安电子科技大学 | SiC-bipolar junction transistor (SiC-BJT) device for power integrated circuit and manufacturing method of SiC-BJT device |
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2014
- 2014-08-26 CN CN201410425765.XA patent/CN104201197B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102132388A (en) * | 2008-08-26 | 2011-07-20 | 本田技研工业株式会社 | Bipolar semiconductor device and method for manufacturing same |
| CN102610638A (en) * | 2012-03-22 | 2012-07-25 | 西安电子科技大学 | SiC-bipolar junction transistor (SiC-BJT) device for power integrated circuit and manufacturing method of SiC-BJT device |
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