CN104183494A - Trench type power metal oxide semiconductor structure and forming method thereof - Google Patents
Trench type power metal oxide semiconductor structure and forming method thereof Download PDFInfo
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- CN104183494A CN104183494A CN201310199270.5A CN201310199270A CN104183494A CN 104183494 A CN104183494 A CN 104183494A CN 201310199270 A CN201310199270 A CN 201310199270A CN 104183494 A CN104183494 A CN 104183494A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 19
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 4
- 150000004706 metal oxides Chemical class 0.000 title abstract description 4
- 238000002955 isolation Methods 0.000 claims abstract description 14
- 230000015572 biosynthetic process Effects 0.000 claims description 19
- 230000002093 peripheral effect Effects 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 7
- 230000005684 electric field Effects 0.000 abstract description 7
- 238000009826 distribution Methods 0.000 abstract description 4
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 238000002513 implantation Methods 0.000 description 14
- 150000002500 ions Chemical class 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000002262 irrigation Effects 0.000 description 1
- 238000003973 irrigation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003334 potential effect Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66553—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using inside spacers, permanent or not
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
- H01L29/7828—Vertical transistors without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
Abstract
The invention discloses a trench type power metal oxide semiconductor structure and a forming method thereof. The forming method of the trench type power metal oxide semiconductor structure comprises: an isolation groove is formed; two doping layers with different doping concentrations are formed, wherein the two doping layers are connected and are located at the periphery of the isolation groove; and an isolation structure is formed in the isolation groove. Because the two doping layers are connected and are arranged at the periphery of the isolation groove, the formed junction profile can be controlled based on ion implantation, thereby effectively alleviating electric field distribution and conduction losses.
Description
Technical field
The invention relates to aqueduct type power metal-oxide-semiconductor structure and its formation method, espespecially a kind of aqueduct type power metal-oxide-semiconductor structure and its formation method of passing through repeatedly Implantation control interface profile shape.
Background technology
In the application of power semiconductor, the performance of voltage endurance capability and Low ESR is unusual significant capability index, and traditional way uncontrollable interface profile (Junction Profile), therefore cannot manufacture higher voltage endurance capability and have Low ESR.
Summary of the invention
The invention provides a kind of formation method of aqueduct type power metal-oxide-semiconductor structure, comprise: first form an isolated groove, then form two doped layers with different levels of doping, and two doped layers are connected and are positioned at this isolated groove periphery, and formation one isolation structure is positioned at isolated groove.
In one embodiment, the present invention forms the front of this isolated groove step and also comprises: form an epitaxial layer, then form a gate trench in epitaxial layer, then form a grid structure in gate trench, then form this tagma peripheral around this grid structure, and this isolated groove is positioned at this this outside, tagma.
In one embodiment, the present invention forms an isolated groove and forms two doped layers with different levels of doping, is to comprise: form one first isolated groove; Form one first doped layer, be positioned at the first isolated groove peripheral; The first doped layer of etch isolates beneath trenches, to form one second isolated groove; And form one second doped layer, be positioned at the second isolated groove peripheral.
In one embodiment, the sectional area of the first isolated groove of the present invention is greater than the sectional area of this second isolated groove.
In one embodiment, these two doped layers of formation of the present invention are to use different angled ion to flow on diverse location to form.
In one embodiment, two doped layers of the present invention be from top to bottom form and concentration for by light to dense.
The present invention also provides a kind of aqueduct type power metal-oxide-semiconductor structure, comprising: an isolated groove; One isolation structure, is positioned at isolated groove; And two doped layers with different levels of doping, and two connected isolated groove peripheries that are positioned at of doped layers.
In one embodiment, the present invention also comprises: an epitaxial layer; One gate trench, is positioned at epitaxial layer; One grid structure, is positioned at gate trench; One this tagma, all around gate structure is peripheral; Wherein this isolated groove, is positioned at this this outside, tagma, and the degree of depth of this isolated groove is higher than the degree of depth of grid structure.
In one embodiment, isolated groove of the present invention comprises one first connected isolated groove and one second isolated groove, and these two doped layer correspondences are formed at this first isolated groove and this second isolated groove is peripheral.
In one embodiment, the sectional area of the first isolated groove of the present invention is greater than the sectional area of this second isolated groove.
In one embodiment, these two doped layers formation of the present invention are to use different angled ion to flow on diverse location to form.
In one embodiment, two doped layers of the present invention be from top to bottom form and concentration for by light to dense.
Aqueduct type power metal-oxide-semiconductor structure of the present invention and forming method thereof, makes the interface profile forming outside trenched side-wall repeatedly.This interface profile can be by injecting the control of ionic weight, form the design variation of width shape, when backfill oxide is to groove inside, metal-oxide semiconductor (MOS) (MOSFET) forms the potential effect of utilizing this district charge balance (Charge Balance) and reduces surface field effect (RESURF) when reverse blas operates, so just can form gentler Electric Field Distribution at groove and sidewall electric field, utilize whereby less space and the higher current potential integration of more efficient acquisition and lower conducting loss (RON) characteristic performance, separately also principle is done optimization adjustment by required epitaxial layer resistance and thickness whereby, make conducting lose more effective reduction, and then reduction element conductive loss.
Above general introduction and ensuing detailed description are all exemplary in nature, are in order to further illustrate claim of the present invention.And relevant other objects and advantages of the present invention are set forth the explanation follow-up and accompanying drawing.
Accompanying drawing explanation
Figure 1A～1J is depicted as an embodiment of the formation method of aqueduct type power metal-oxide-semiconductor structure of the present invention;
Another aqueduct type power metal-oxide-semiconductor structure of the present invention shown in Fig. 2;
Another aqueduct type power metal-oxide-semiconductor structure of the present invention shown in Fig. 3;
Shown in Fig. 4, aqueduct type power metal-oxide-semiconductor structure of the present invention carries out Implantation mode with rake angle;
Another aqueduct type power metal-oxide-semiconductor structure of the present invention shown in Fig. 5;
Another aqueduct type power metal-oxide-semiconductor structure of the present invention shown in Fig. 6.
Embodiment
Technical characteristics of the present invention is repeatedly to make at least two doped layers and is connected to form the interface profile outside trenched side-wall.And this interface profile can form the design variation of width shape by injecting the control of ionic weight (being concentration), and reach, at groove and sidewall electric field, forms gentler Electric Field Distribution, makes conducting lose more effective reduction, and then reduces element conductive loss.The design of this part can be applicable to the element region of metal-oxide-semiconductor structure or the groove of termination environment (Termination), to control injection ionic weight, reaches specific interface profile effectively to reach voltage endurance capability and Low ESR effect.
As Figure 1A～1J is depicted as an embodiment of the formation method of aqueduct type power metal-oxide-semiconductor structure of the present invention.It is applied in an embodiment of element region, and the groove in the termination environment of for example periphery or both sides also can have similar application.
First, the epitaxial layer (Epi) 12 of first growing up on a base material (Substrate) 10 as shown in Figure 1A.Then, in Figure 1B in interior formation one gate trench 14 of epitaxial layer 12, and the gate dielectric 16 of growing up in gate trench 14 inner sides.Then in Fig. 1 C, form a grid structure 18 in gate trench 14 inside, at this, for example with polysilicon deposition (Poly Depostion), arrive gate trench 14 inside and epitaxial layer 12 tops, and then see through (Etch back) mode of eat-backing by epitaxial layer 12 top deposit spathic silicons removals, only retain the inner polysilicon of gate trench 14, and form grid structure 18 in gate trench 14 inside.
Then, as shown in Fig. 1 D, form this tagma 20, all around gate structure 18 peripheries, wherein this tagma 20 P-type conduction type Implantation mode for example, is different from the epitaxial layer 12 that uses N-type conductivity type.Then,, as shown in Fig. 1 E, form one first isolated groove 22, be positioned at this 20 outsides, tagma, the wherein formation of the first isolated groove 22, for example, can become in advance a mask layer 24 to cover grid structure 18 and these tagma 20 parts, and then this tagma 20 of etching is to form the first isolated groove 22.The first isolated groove 22 is then for example, with the first concentration (P in this case
-representative), see through Implantation mode in epitaxial layer 12 to form the first doped layer 26, then as vertically downward arrow 27 directions are with driving (Drive-In; D/I) mode, makes P
-the first doped layer 26 to the left and right up and down diffusion, by P
-the first doped layer 26 be diffused into the first isolated groove 22 peripheries, periphery is for example bottom and bottom side.
Then, as Fig. 1 F is shown in the downward etching P of original the first isolated groove 22
-the first doped layer 26, or further etch into again epitaxial layer 12, to expand the first isolated groove 22 to second isolated grooves 28, and then carry out Implantation with different levels of doping, for example at this with the second concentration (P
+) see through Implantation mode, to interior formation the second doped layer 30 of epitaxial layer 12, then as vertically downward arrow 31 directions are to drive (Drive-In; D/I) mode, makes P
+the diffusion up and down to the left and right of the second doped layer 30, and make P
+the second doped layer 30 be diffused into the second isolated groove 28 peripheries, periphery is for example bottom and bottom side.
Then, as shown in Figure 1 G at the downward etching P of the second isolated groove 28
+the second doped layer 30, or further etch into epitaxial layer 12, to expand the second isolated groove 28 to the 3rd isolated groove 32, and then carry out Implantation with different levels of doping, for example at this with the 3rd concentration (P
+ ') through Implantation mode, form the 3rd doped layer 34, wherein the 3rd doped layer 34 for example can be used and the second concentration (P
+) concentration identical or that be greater than carries out, then as vertically downward arrow 31 directions are to drive (Drive-In; D/I) mode, makes P
+ 'the diffusion up and down to the left and right of the 3rd doped layer 34, and make P
+ 'the 3rd doped layer 34 be positioned at the 3rd isolated groove 32 peripheries, be for example bottom and bottom side.
Then, as Fig. 1 H is shown in the downward etching P of the 3rd isolated groove 32
+ 'the 3rd doped layer 34, or further etch into epitaxial layer 12, to expand the 3rd isolated groove 32 to the 4th isolated groove 36, then carry out ion implantation process, for example at this with the 4th concentration (P
++) through Implantation mode, form the 4th doped layer 38, wherein the 4th doped layer 38 for example can be used and be greater than the 3rd concentration (P
+ ') concentration carry out, then as vertically downward arrow 39 directions drive (Drive-In with heat; D/I) mode, makes P
++the diffusion up and down to the left and right of the 4th doped layer 38, and make P
++the 4th doped layer 38 be positioned at the periphery of the 4th isolated groove 36, periphery is for example bottom and bottom side.
Then, as Fig. 1 I forms an isolation structure 40, be positioned at the 4th isolated groove 36, wherein isolation structure 40 is for example used oxide layer (Oxide) to form, then as shown in Fig. 1 J, form respectively in the 42Yu Zhe tagma, source area 20 of N+, oxide layer 46 is in the source area 42 and grid structure 18 of N+, and heavily doped layer 48 (is for example used P
++) in this body, and be connected to the source area 42 and isolation structure 40 of N+, there is reduction impedance effect, and metal level 44 is in isolation structure 40, heavily doped layer 48 and oxide layer 46.As follows in forming process: oxide layer 41 above etching part in Fig. 1 I first, then see through the 42Yu Zhe tagma, source area 20 that implanted ions forms N+, then to both sides etching, comprise above part isolation structure 40, the source area 42 of part N+ and this tagma 20 of part form irrigation canals and ditches, again implanted ions is carried out to form heavily doped layer 48 in this tagma, finally just do metal level 44 depositions.
In addition, as Fig. 1 J forms aqueduct type power metal-oxide-semiconductor structure, wherein the first doped layer 26, the second doped layer 30, the 3rd doped layer 34 and the 4th doped layer 38 are for being all connected, certainly we can do the framework that is partly connected according to the actual requirements in design, for example controlling the connected interface profile (Junction Profile) that is positioned at this isolated groove periphery and obtains of at least two doped layers with different levels of doping, is all to belong to the embodiment that the present invention may change.
In addition, in Fig. 1 J embodiment, the first doped layer 26, the second doped layer 30, the 3rd doped layer 34 and the 4th doped layer 38 from top to bottom, for concentration turns the dense trapezoidal interface profile that forms by light.Another aqueduct type power metal-oxide-semiconductor structure of the present invention, wherein a plurality of doped layers, for example P as shown in Figure 2
+the 3rd doped layer 54, P
-'the second doped layer 52 and P
-the first doped layer 50 form, a plurality of doped layers from top to bottom, for concentration turns the light interface profile that forms inverted trapezoidal by dense.
In addition another aqueduct type power metal-oxide-semiconductor structure of the present invention, wherein a plurality of doped layers, for example P as shown in Figure 3,
-the 3rd doped layer 60, the second doped layer 62 and P of N-
-the first doped layer 64 form, with the variable concentrations of different conductivity types (P type and N-type), also can make interface profile (Junction Profile), be all to belong to the embodiment that the present invention may change.
Then, aqueduct type power metal-oxide-semiconductor structure of the present invention carries out Implantation mode with rake angle as shown in Figure 4.As shown in Figure 4, comprise four different steps 210, in 220,230,240, with different rake angles, carry out Implantation, isolated groove 250 at different depth, on 260,270,280 diverse location, form a plurality of doped layers, if to correspond to after Fig. 1 D, just can skip over Fig. 1 E and the driving (Drive-In that it goes without doing vertically downward; D/I), directly to Fig. 1 F, with the first rake angle (as step 210), carry out Implantation and form P
-the first doped layer 26, then in Fig. 1 G, with the second rake angle (as step 220), carrying out Implantation forms P
+the second doped layer 30, in Fig. 1 H, with the 3rd rake angle (as step 230) and the 4th rake angle (as step 240), carry out Implantation and form P
+ 'the 3rd doped layer 34 and P
++the 4th doped layer 38.
Another aqueduct type power metal-oxide-semiconductor structure of the present invention as shown in Figure 5, wherein from top to bottom form the first isolated groove 502, the second isolated groove 504, the 3rd isolated groove 506 and the 4th isolated groove 508 have different cross-sectional (or floor space), for example at this from top to bottom, sectional area is more and more less, and under variable concentrations is controlled, to obtain a plurality of doped layers be a more smooth-going interface profile, the first isolated groove 502 wherein, the second isolated groove 504, the 3rd isolated groove 506 and the 4th isolated groove 508 inwalls can become a clearance wall (Spacer) 510 in advance, wherein any two up and down connected clearance wall overlap, then isolated groove 502, 504, in 506 and 508, insert again oxide layer (Oxide) or polysilicon (Poly).
Another aqueduct type power metal-oxide-semiconductor structure of the present invention as shown in Figure 6, first isolated groove 602, second isolated groove 604, three isolated groove 606 and four isolated groove 608 with different cross-sectional identical with Fig. 5, under variable concentrations is controlled, to be a concentration turn the light interface profile that forms inverted trapezoidal by dense to the first doped layer 616, the second doped layer 614, the 3rd doped layer 612 and the 4th doped layer 610 of forming.
Aqueduct type power metal-oxide-semiconductor structure of the present invention and forming method thereof, do not limit element region or termination environment, as long as there is groove, see through the control of injecting ion concentration, form at least two and connect doped layer, repeatedly to make the interface profile forming outside trenched side-wall, reach the design variation of width shape, therefore can form charge balance (Charge Balance) and reduce surface field effect (RESURF), at groove and sidewall electric field, form gentler Electric Field Distribution, therefore improve withstand voltage degree and reduce element conductive loss.
As mentioned above, the present invention meets patent three important documents completely: the practicality in novelty, creativeness and industry.The present invention discloses with preferred embodiment hereinbefore, is so familiar with the technology person and it should be understood that this embodiment is only for describing the present invention, and should not be read as and limit the scope of the invention.It should be noted, such as, with variation and the displacement of this embodiment equivalence, all should be made as and be covered by category of the present invention.Therefore, protection scope of the present invention is when being as the criterion with the scope that appending claims was defined.
Claims (12)
1. a formation method for aqueduct type power metal-oxide-semiconductor structure, is characterized in that, comprising:
Form an isolated groove;
Formation has two doped layers of different levels of doping, and connected this isolated groove periphery that is positioned at of these two doped layers; And
Form an isolation structure, be positioned at this isolated groove.
2. the formation method of aqueduct type power metal-oxide-semiconductor structure according to claim 1, is characterized in that, forms the front of this isolated groove step and also comprises:
Form an epitaxial layer;
Form a gate trench in this epitaxial layer;
Form a grid structure in this gate trench; And
Form this tagma, peripheral around this grid structure, and this isolated groove is positioned at this this outside, tagma.
3. the formation method of aqueduct type power metal-oxide-semiconductor structure according to claim 1, is characterized in that, form this isolated groove and form two doped layers with different levels of doping, be to comprise:
Form one first isolated groove;
Form one first doped layer, be positioned at this first isolated groove peripheral;
This first doped layer of this first isolated groove below of etching, to form one second isolated groove; And
Form one second doped layer, be positioned at this second isolated groove peripheral.
4. the formation method of aqueduct type power metal-oxide-semiconductor structure according to claim 3, is characterized in that, the sectional area of this first isolated groove is greater than the sectional area of this second isolated groove.
5. the formation method of aqueduct type power metal-oxide-semiconductor structure according to claim 1, is characterized in that, forming these two doped layers is to use different angled ion to flow on diverse location to form.
6. the formation method of aqueduct type power metal-oxide-semiconductor structure according to claim 1, is characterized in that, these two doped layers be from top to bottom form and concentration for by light to dense.
7. an aqueduct type power metal-oxide-semiconductor structure, is characterized in that, comprising:
One isolated groove;
One isolation structure, is positioned at this isolated groove; And
Two doped layers with different levels of doping, and connected this isolated groove periphery that is positioned at of these two doped layers.
8. aqueduct type power metal-oxide-semiconductor structure according to claim 7, is characterized in that, also comprises:
One epitaxial layer;
One gate trench, is positioned at this epitaxial layer;
One grid structure, is positioned at this gate trench; And
One this tagma, peripheral around this grid structure, wherein this isolated groove, is positioned at this this outside, tagma, and the degree of depth of this isolated groove is higher than the degree of depth of grid structure.
9. aqueduct type power metal-oxide-semiconductor structure according to claim 7, it is characterized in that, this isolated groove comprises one first connected isolated groove and one second isolated groove, and these two doped layer correspondences are formed at this first isolated groove and this second isolated groove is peripheral.
10. aqueduct type power metal-oxide-semiconductor structure according to claim 8, is characterized in that, the sectional area of this first isolated groove is greater than the sectional area of this second isolated groove.
11. aqueduct type power metal-oxide-semiconductor structures according to claim 7, is characterized in that, it is to use different angled ion to flow on diverse location to form that these two doped layers form.
12. aqueduct type power metal-oxide-semiconductor structures according to claim 7, is characterized in that, these two doped layers be from top to bottom form and concentration for by light to dense.
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| CN201310199270.5A CN104183494B (en) | 2013-05-24 | 2013-05-24 | Trench type power metal oxide semiconductor structure and forming method thereof |
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| CN201310199270.5A CN104183494B (en) | 2013-05-24 | 2013-05-24 | Trench type power metal oxide semiconductor structure and forming method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106098751A (en) * | 2016-07-14 | 2016-11-09 | 电子科技大学 | A kind of power semiconductor terminal structure |
| TWI567830B (en) * | 2015-07-31 | 2017-01-21 | 帥群微電子股份有限公司 | Trench power transistor structure and manufacturing method thereof |
| CN107068759A (en) * | 2016-02-10 | 2017-08-18 | 瑞萨电子株式会社 | Semiconductor devices and its manufacture method |
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| CN1589499A (en) * | 2001-11-20 | 2005-03-02 | 通用半导体公司 | Trench MOSFET device with polycrystalline silicon source contact structure |
| CN101728266A (en) * | 2008-10-15 | 2010-06-09 | 尼克森微电子股份有限公司 | Manufacturing method of ditch-type power semiconductor |
| US20120098055A1 (en) * | 2010-07-06 | 2012-04-26 | Maxpower Semiconductor, Inc. | Power Semiconductor Devices, Structures, and Related Methods |
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2013
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1589499A (en) * | 2001-11-20 | 2005-03-02 | 通用半导体公司 | Trench MOSFET device with polycrystalline silicon source contact structure |
| US20040157384A1 (en) * | 2002-03-21 | 2004-08-12 | Blanchard Richard A. | Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step |
| CN101728266A (en) * | 2008-10-15 | 2010-06-09 | 尼克森微电子股份有限公司 | Manufacturing method of ditch-type power semiconductor |
| US20120098055A1 (en) * | 2010-07-06 | 2012-04-26 | Maxpower Semiconductor, Inc. | Power Semiconductor Devices, Structures, and Related Methods |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI567830B (en) * | 2015-07-31 | 2017-01-21 | 帥群微電子股份有限公司 | Trench power transistor structure and manufacturing method thereof |
| US9876106B2 (en) | 2015-07-31 | 2018-01-23 | Super Group Semiconductor Co., Ltd. | Trench power transistor structure and manufacturing method thereof |
| CN107068759A (en) * | 2016-02-10 | 2017-08-18 | 瑞萨电子株式会社 | Semiconductor devices and its manufacture method |
| CN106098751A (en) * | 2016-07-14 | 2016-11-09 | 电子科技大学 | A kind of power semiconductor terminal structure |
| CN106098751B (en) * | 2016-07-14 | 2018-11-23 | 电子科技大学 | A kind of power semiconductor terminal structure |
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