CN104157588B - Parallel detection method for three-dimensional size defects of SOT packaging chip pin - Google Patents
Parallel detection method for three-dimensional size defects of SOT packaging chip pin Download PDFInfo
- Publication number
- CN104157588B CN104157588B CN201410391570.8A CN201410391570A CN104157588B CN 104157588 B CN104157588 B CN 104157588B CN 201410391570 A CN201410391570 A CN 201410391570A CN 104157588 B CN104157588 B CN 104157588B
- Authority
- CN
- China
- Prior art keywords
- thread
- detection
- image
- pin
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
Abstract
The invention provides a parallel detection method for three-dimensional size defects of an SOT packaging chip pin. In the method, the detection process of a single SOT packaging chip is divided into seven procedures and respectively packaged in seven threads. The process thread function comprises a serial port detection thread, an image acquisition thread, an image detection thread, a result analysis thread, a synchronous code thread, an interface refresh thread and a database backup thread according to the detection process. The plurality of detection procedures for the SOT packaging chip are in parallel operation. Each of the image acquisition thread, the image detection thread and the result analysis thread comprises two modules, namely, a plane image detection module and a pin height detection module. With the method, parallel detection on the plurality of chips can be realized, plane pin size detection and three-dimensional parallel detection of the pin height can be realized, and the detection speed is obviously improved.
Description
Technical field
The present invention relates to semiconductor chip detection field, more particularly, to sot encapsulation class chip pin three-dimensional dimension defect is simultaneously
Row detection method.
Background technology
Sot encapsulation class chip size is less, and profile is simple, and volume of production is big.This chip typically has 3 to 6 pins.
Because chip pin is to undertake chip external interface function, if the unqualified chip that will directly affect of chip pin is in circuit board
On welding quality, impact circuit board normal work, therefore in order to ensure the reliability of chip outgoing, the defect of pin
Detection is an important step.
Sot encapsulation class chip pin dimensional defects detection on production line completes on specific station.In order to comprehensive
Detection chip pin defect, except detect pin planar dimension (pin length, pin widths, pin span detection),
Need to detect height of pin (detection of pin flatness), therefore in detection process, employ two video cameras respectively to chip
The length, width and height of pin are detected, thus realizing three-dimensional values.
The chip production amount of sot encapsulated type is big, needs the number of detection chip many, therefore for the real-time defect of system
Detection requirement is higher, and in actual production, the average detected cycle will reach 40ms/ piece.But during the three-dimensional values of reality,
The data acquisition of two stations result in the reduction of detection efficiency.
Therefore need a solution.
Content of the invention
In order to meet real-time and the high efficiency of sot encapsulated type chip pin detecting system.The goal of the invention of the present invention
Aim to provide a kind of sot encapsulation class chip pin three-dimensional dimension defect parallel detecting method.The method both can realize chip inspection
Survey process parallel, can realize again pin planar dimension detection with height of pin detect parallel, make detection speed have substantially
Raising.
The technical scheme that the sot encapsulation class chip pin three-dimensional dimension defect parallel detecting method of the present invention is adopted is:
Single sot encapsulation chip detection flow process is encapsulated in 7 threads, described thread arranges according to testing process, including serial ports inspection
Survey line journey, image acquisition thread, image detection thread, interpretation of result thread, synchronous coding thread, it is standby that database is refreshed at interface
Part thread.The testing process that multiple sot encapsulate chip can be with parallel running.
Wherein image acquisition thread, image detection thread and interpretation of result thread all comprise two modules: plane picture inspection
Survey module and height of pin detection module.Two detection modules can be with parallel running.
Described serial ports detection thread is used for being responsible for monitoring serial port, the image pick-up signal that real-time reception host computer sends, and
Analysis rs 232 serial interface signal, starts image acquisition process by control routine: when control routine is " 1 ", represents and only start pin
Planar dimension detection module；When control routine is " 2 ", represents and only start height of pin detection module；When control routine is
When " 3 ", expression system starts pin planar dimension detection module and height of pin detection module simultaneously；
Described image collecting thread is used for sot and encapsulates the plane picture collection of chip and the collection of height of pin image, and
Image is delivered in respective internal memory；
Described image detects that thread is used for sot encapsulation chip plane image and the pretreatment of height of pin image, projection divide
The larger image manipulation of the amounts of calculation such as analysis, template matching；
Described interpretation of result thread is used for sot and encapsulates at chip plane image and the result of height of pin image
Reason, whether qualified analysis pin size is, if unqualified, needs to judge chip defect type；
Described synchronous coding thread is mainly used in the result treatment of control routine " 3 ", and two independent operatings are not interfere with each other
Detection module result synchronous coding, Serial Port Information is sent to host computer, but if only start control routine " 1 "
Or control routine " 2 " does not then need to synchronize coding thread, directly testing result coding is sent to by Serial Port Information
Position machine startup interface refreshing database backup；
The image that thread is used for gathering chip is refreshed at described interface, the image after image procossing, graphics process close bond number
Flush on display interface according to, processing result image, data statisticss.
Described DB Backup thread be used for pin planar dimension detection module and height of pin resume module result and
Image treatment features data is saved in data base, and original image is saved in industrial computer file system.
Detection process is divided into serial ports detection, figure by the sot chip defect detection method of the present invention have the beneficial effect that first
As collection, image detection, interpretation of result, synchronous coding, interface refreshing database back up this 7 threads, on the one hand can be by
Whole detection process is distinguished clear, on the other hand can also make the different detecting step parallel runnings of different chips, by by chip
Each stage of detection is divided in different threads under just can be able to accepting when previously defects detection is not fully completed
The defect detection signal of a piece of chip, by image acquisition, image procossing, writes the time-consuming longer detection-phase of database on backstage
Run, it is to avoid impact normal program operation, and refreshing display interface and the relatively low line of backup database isopreference level can be made
Journey is postponed and being run, and improves the response speed of system.Secondly, pin planar dimension detection module and height of pin detection module make two
Individual flow process parallel synchronous are run, and improve processor utilization, shorten monolithic chip defects detection and take.
This method can improve cpu utilization rate simultaneously, optimizes program structure, saves system overhead.For process,
Thread runs and only needs to limited depositor and stack space, and thread oneself does not have whole resources that system process is had,
The system resource consuming during thread creation, scheduling switching and cancellation etc. is less.
Brief description
Fig. 1 is the system detectio flow chart that sot of the present invention encapsulates class chip pin three-dimensional dimension defect parallel detecting method；
Fig. 2 is that the testing process of sot encapsulation class chip pin three-dimensional dimension defect parallel detecting method of the present invention is schemed parallel.
Specific embodiment
With reference to embodiment, the present invention is further elaborated:
As shown in figure 1, the detection process that single sot encapsulates chip is encapsulated in 7 threads the present invention, including serial ports inspection
Survey line journey, image acquisition thread, image detection thread, interpretation of result thread, synchronous coding thread, thread data is refreshed at interface
Library backup thread.Wherein image acquisition thread, image detection thread, interpretation of result thread respectively comprise two modules: plane monitoring-network
Module and height of pin module.Wherein, image acquisition thread, image detection thread, interpretation of result thread, synchronous coding thread,
Thread database backup thread is refreshed using the thread communication method using global variable it is ensured that each variable is needing in interface
Shi Junke is obtained by global variable；Serial ports detection thread and serial ports are sent message and are led to using message message mechanism
The method of letter, self-defined message is sent to the message queue of corresponding main window, opens image acquisition by message response function
Thread and the thread of serial ports transmission message.The testing process that multiple sot encapsulate chip can be with parallel running；Plane monitoring-network module and
Height of pin module can be with parallel detection.
It is by system initialization first, including data base's global parameter loading, initialization of (a) serial ports, initial after system start-up
Change camera, light source configuration and Chip scale to be detected setting, character and pin field selection and Image semantic classification parameter etc., be
System initialization carries out the operation of each thread after completing.
Serial ports detection thread is used for being responsible for monitoring serial port, the image pick-up signal that real-time reception host computer sends, and analyzes
Rs 232 serial interface signal, starts image acquisition process by control routine: when control routine is " 1 ", represents and only start plane pin
The defects detection of size；When control routine is " 2 ", represent the defects detection module only starting height of pin detection；Work as control
When code processed is " 3 ", expression system starts pin planar dimension detection module and height of pin detection module simultaneously.
Image acquisition thread is responsible for controlling the collection of image, and image is delivered to internal memory.
Image detection line thread is responsible for image section pin feature and is carried out the calculating such as pretreatment, Projection Analysis, template matching
Measure larger image manipulation, be the pith of graphics system detection.During use, it is responsible for control plane image and height of pin
Image is delivered to internal memory by gigabit network cable by the collection of image, can be in manta g-031b industrial camera secondary development sdk
On the basis of gather image by designing certain logic.
Interpretation of result thread is responsible for for processing result image carrying out data analysiss, if unqualified, needs to judge that chip lacks
Sunken type, carries out data processing to height of pin image pin result, and whether qualified analysis pin size is.
Synchronous coding thread is mainly used in the result treatment of control routine 3, by non-interfering for two independent operatings detection
The result synchronous coding of module, Serial Port Information is sent to host computer.But if only start control routine 1 or control generation
Code 2 does not then need to synchronize coding thread, directly testing result coding is sent to host computer by Serial Port Information and is started
Database backup is refreshed at interface.
Interface refresh the image that thread is used for collecting chip, the image after image procossing, graphics process critical data,
Processing result image, data statisticss flush on interface.
DB Backup thread is used for pin planar dimension detection module and height of pin resume module result and image
Processing feature data is saved in data base, facilitates data query it is possible to original image is saved in industrial computer file system.
In order that thread departs from coupling with father's thread, it is to avoid the impact that after thread extinction, detection data is lost, father's thread
With sub- cross-thread using shared drive method transmission data by the way of communicated, that is, father's thread by need transmission variable or
Need the structure region of memory that the variable save to departing from coupling is opened up temporarily, by structure during father's thread creation sub-line journey
The pointer deposited in vivo is delivered to sub-line journey as parameter, and the structure region of memory temporarily opened up may proceed to be existed, will not be because of
The extinction of father's thread and disappear, sub-line journey can obtain the variable in structure by pointer, and destroys in time in sub-line journey
Structure, discharges structure internal memory, prevents RAM leakage.
As shown in Fig. 2 sot encapsulation class chip pin three-dimensional dimension defect parallel detecting method is by each by chip detection
The individual stage is divided into the detection that can accept multiple chips in different threads, and by image acquisition, image procossing, write number
Take longer detection-phase according to storehouse etc. in running background.
Claims (4)
1. a kind of sot encapsulation class chip pin three-dimensional dimension defect parallel detecting method it is characterised in that: single sot is encapsulated
Chip detection flow process is packaged in 7 threads, and described thread arranges according to testing process, adopts including serial ports detection thread, image
Thread database backup thread is refreshed at collection thread, image detection thread, interpretation of result thread, synchronous coding thread, interface；Many
Individual sot encapsulates the testing process parallel running of chip；Described image collecting thread, image detection thread and interpretation of result thread are equal
Comprise two modules: plane picture detection module and height of pin detection module；Described plane picture detection module and pin are high
Degree detection module parallel detection.
2. sot as claimed in claim 1 encapsulation class chip pin three-dimensional dimension defect parallel detecting method it is characterised in that:
Described serial ports detection thread is used for being responsible for monitoring serial port, the image pick-up signal that real-time reception host computer sends, and analyzes
Rs 232 serial interface signal, starts image acquisition thread；
Described image collecting thread control plane image and the collection of height of pin image, and image is delivered to internal memory；
Described image detection thread carries out pretreatment, projection point to character zone feature in plane picture and part pin feature
Analysis, the image manipulation of template matching；
Described interpretation of result thread carries out data and divides to character picture in plane picture and part pin size characteristic processing result
Analysis, carries out data processing to height of pin image pin result, and whether qualified analysis pin size is, if unqualified, needs
Judge chip defect type；
Described synchronous coding thread is used for the result synchronous coding of non-interfering for two independent operatings detection module, will
Serial Port Information is sent to host computer；
Described interface refresh the image that thread is used for collecting chip, the image after image procossing, graphics process critical data,
Processing result image, data statisticss flush to defects detection display interface；
Described DB Backup thread is used for pin planar dimension detection module and height of pin resume module result and image
Processing feature data is saved in data base, and original image is saved in industrial computer file system.
3. sot as claimed in claim 1 encapsulation class chip pin three-dimensional dimension defect parallel detecting method it is characterised in that:
Control Cooling is divided into 3 classes by described serial ports detection thread: when control routine is " 1 ", expression system only starts the flat of pin
Planar defect detection module；When control routine is " 2 ", expression system only starts the defects detection module of height of pin；Work as control
When code processed is " 3 ", expression system starts pin plane monitoring-network module and height of pin detection module simultaneously.
4. sot as claimed in claim 3 encapsulation class chip pin three-dimensional dimension defect parallel detecting method it is characterised in that:
Described synchronous coding thread when control routine is " 3 ", by the result of non-interfering for two independent operatings detection module
Synchronous coding, Serial Port Information is sent to host computer；When control routine is " 1 " or " 2 ", directly will be logical for testing result coding
Cross Serial Port Information and be sent to host computer startup interface refreshing database backup.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410391570.8A CN104157588B (en) | 2014-08-11 | 2014-08-11 | Parallel detection method for three-dimensional size defects of SOT packaging chip pin |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410391570.8A CN104157588B (en) | 2014-08-11 | 2014-08-11 | Parallel detection method for three-dimensional size defects of SOT packaging chip pin |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104157588A CN104157588A (en) | 2014-11-19 |
| CN104157588B true CN104157588B (en) | 2017-02-01 |
Family
ID=51883062
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410391570.8A Active CN104157588B (en) | 2014-08-11 | 2014-08-11 | Parallel detection method for three-dimensional size defects of SOT packaging chip pin |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104157588B (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112735969B (en) * | 2021-04-02 | 2021-08-06 | 高视科技(苏州)有限公司 | LED semiconductor packaging glue dispensing defect detection method, electronic equipment and storage medium |
| CN113218952B (en) * | 2021-04-25 | 2022-11-01 | 华南理工大学 | Method, device, equipment and medium for detecting multi-scale appearance defects of IC packaging carrier plate |
| US20230051313A1 (en) * | 2021-08-11 | 2023-02-16 | FootPrintKu Inc. | Method and system for analyzing specification parameter of electronic component, computer program product with stored program, and computer readable medium with stored program |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101976203A (en) * | 2010-09-26 | 2011-02-16 | 清华大学 | Parallelized simulation multithread management method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080099495A (en) * | 2007-05-09 | 2008-11-13 | 삼성전자주식회사 | Pipeline test apparatus and method |
| US20100023294A1 (en) * | 2008-07-28 | 2010-01-28 | Credence Systems Corporation | Automated test system and method |
-
2014
- 2014-08-11 CN CN201410391570.8A patent/CN104157588B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101976203A (en) * | 2010-09-26 | 2011-02-16 | 清华大学 | Parallelized simulation multithread management method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104157588A (en) | 2014-11-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102937594B (en) | Defect detecting system and method | |
| CN104157588B (en) | Parallel detection method for three-dimensional size defects of SOT packaging chip pin | |
| CN102063355B (en) | Automatic test server and system of disk array | |
| CN109961107A (en) | Training method, device, electronic equipment and the storage medium of target detection model | |
| CN101807061A (en) | Vision detection control system and method for integrated circuit tendon-cut system | |
| CN109167979B (en) | Processing method and system for artificial intelligence analysis of multi-path monitoring videos | |
| US10241895B2 (en) | Memory stack trace management tool | |
| CN104112413A (en) | LED display screen dead pixel point inspection system | |
| CN112231163A (en) | Multifunctional computer detection equipment and operation method thereof | |
| CN114153783B (en) | Method, system, computer device and storage medium for implementing multi-core communication mechanism | |
| US9529377B2 (en) | Adaptive voltage scaling circuit and chip | |
| CN111866500B (en) | Image testing device based on FPGA, CPU and WIFI6 | |
| CN103489817B (en) | defect detecting system and method | |
| CN102541705B (en) | Testing method for computer and tooling plate | |
| US20230196756A1 (en) | Method for detecting defects and electronic device | |
| CN203658991U (en) | Computer evidence obtaining system | |
| CN208240624U (en) | Semiconductor assembly and test device | |
| CN114724985B (en) | Packaging transmission control system of photovoltaic module chip | |
| CN112420535A (en) | Chip manufacturing method and system | |
| CN112964723B (en) | Visual detection method and system for double-sided multi-target equidistant array | |
| US20230305976A1 (en) | Data flow-based neural network multi-engine synchronous calculation system | |
| CN106908455A (en) | IMAQ terminal, glass surface defects on-line detecting system and method | |
| US11816016B2 (en) | Identifying causes of anomalies observed in an integrated circuit chip | |
| CN213904332U (en) | Mainboard temperature detecting system | |
| WO2022153827A1 (en) | Article detection method, device, and electronic apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |