CN104155812A - Array substrate, method for manufacturing same and liquid crystal display device - Google Patents
Array substrate, method for manufacturing same and liquid crystal display device Download PDFInfo
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- CN104155812A CN104155812A CN201410366579.3A CN201410366579A CN104155812A CN 104155812 A CN104155812 A CN 104155812A CN 201410366579 A CN201410366579 A CN 201410366579A CN 104155812 A CN104155812 A CN 104155812A
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- resin bed
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Abstract
The invention provides an array substrate, a method for manufacturing the same and a liquid crystal display device, and relates to the technical field of display. The array substrate comprises a supporting substrate, a thin film transistor, a resin layer and a pixel electrodes and further comprises a passivation layer on the basis of the supporting substrate, the thin film transistor, the resin layer and the pixel electrodes, the thin film transistor, the resin layer and the pixel electrodes are sequentially arranged on the supporting substrate, and the passivation layer is arranged between the resin layer and the pixel electrodes and completely wraps the resin layer. The array substrate, the method and the liquid crystal display device have the advantage that various mura phenomena due to the fact that an existing resin layer is exposed in air can be prevented. The invention is used for designing and manufacturing array substrates and liquid crystal display devices with the array substrates.
Description
Technical field
The present invention relates to display technique field, relate in particular to a kind of array base palte and preparation method thereof, liquid crystal indicator.
Background technology
Thin Film Transistor (TFT) liquid crystal display (Thin Film Transistor-Liquid Crystal Display, TFT-LCD) has the features such as volume is little, low in energy consumption, radiationless, dominate in current monitor market.
TFT-LCD comprises array base palte, color membrane substrates and the liquid crystal layer between the two.Wherein, array base palte comprise the grid that is arranged on underlay substrate, with grid line, gate insulation layer, semiconductor active layer, source electrode and drain electrode, the pixel electrode etc. of grid with layer.
Wherein, owing to having stray capacitance between grid and drain electrode; and in the time that this array base palte is bottom gate type array base palte; owing to only having at most the protective seam of one deck silicon nitride to be vulnerable to the interference of data line generation electric field between pixel electrode and data line; therefore; conventionally adopt the lower resin bed of specific inductive capacity to replace protective seam, to solve the problem of above-mentioned stray capacitance and interference.
But in the time that resin material is exposed in air, it easily absorbs moisture, thereby cause the appearance of various picture qualities bad (mura) phenomenon.
Summary of the invention
The invention provides a kind of array base palte and preparation method thereof, liquid crystal indicator, can avoid because resin bed is exposed to the various mura phenomenons that cause in air.
For achieving the above object, the present invention adopts following technical scheme:
On the one hand, a kind of array base palte is provided, comprise underlay substrate, be successively set on thin film transistor (TFT), resin bed and pixel electrode on described underlay substrate, on this basis, described array base palte also comprises the passivation layer being arranged between described resin bed and described pixel electrode, and described passivation layer wraps up described resin bed completely.
Preferably, the edge 1000-2000 μ m of underlay substrate described in the Edge Distance of described resin bed; The edge of described passivation layer flushes with the edge of described underlay substrate.
Preferably, described array base palte also comprises and is arranged on public electrode between described resin bed and described passivation layer.
Based on above-mentioned, preferred, the material of described resin bed is photoresist.
Preferably, described array base palte also comprises and is arranged on described resin bed near described underlay substrate one side and the adhesion layer that contacts with described resin bed; Wherein, described adhesion layer is for strengthening the adhesiveness of described resin bed.
On the other hand, provide a kind of liquid crystal indicator, comprise the array base palte described in above-mentioned any one.
Again on the one hand, a kind of preparation method of array base palte is provided, comprise: on underlay substrate, form successively thin film transistor (TFT), resin bed and pixel electrode, on this basis, described method is also included between described resin bed and described pixel electrode and forms passivation layer, and described passivation layer wraps up described resin bed completely.
Preferably, form described resin bed and described passivation layer comprises:
On the substrate that is formed with described thin film transistor (TFT), form described resin bed by a composition technique, described resin bed comprises the first via hole of the drain electrode of exposing described thin film transistor (TFT); Wherein, the edge 1000-2000 μ m of underlay substrate described in the Edge Distance of described resin bed; On the substrate that is formed with described resin bed, form described passivation layer by a composition technique, described passivation layer comprises second via hole corresponding with described the first via hole; Wherein, the edge of described passivation layer and the edge of described underlay substrate flush.
Further preferred, described on the substrate that is formed with described thin film transistor (TFT), form described resin bed by a composition technique, comprising:
On the substrate that is formed with described thin film transistor (TFT), form photoresist film; Adopt normal masks plate to being formed with the base board to explosure of described photoresist film, form the complete exposed portion of photoresist and photoresist unexposed portion; Wherein, the region of at least corresponding described the first via hole of the complete exposed portion of described photoresist and the fringe region of described underlay substrate, corresponding other regions of described photoresist unexposed portion; After development, described photoresist unexposed portion forms described resin bed.
Based on above-mentioned, preferred, described method also comprises: between described resin bed and described passivation layer, form public electrode; Wherein, in described the first via hole and position corresponding to described the second via hole, described public electrode disconnects.
The invention provides a kind of array base palte and preparation method thereof, liquid crystal indicator, this array base palte comprises underlay substrate, is successively set on thin film transistor (TFT), resin bed and pixel electrode on described underlay substrate, on this basis, described array base palte also comprises the passivation layer being arranged between described resin bed and described pixel electrode, and described passivation layer wraps up described resin bed completely.
Because described resin bed is between described thin film transistor (TFT) and described pixel electrode, therefore, no matter be top gate type thin film transistor or bottom gate thin film transistor, the array base palte that the embodiment of the present invention provides, all can increase between grid and pixel electrode, distance between drain electrode or grid and pixel electrode, be subject to thereby can solve stray capacitance between grid and drain electrode and pixel electrode the problem that data line or grid line disturb.On this basis, owing to being also provided with the passivation layer of the described resin bed of parcel, described passivation layer can make described resin bed and air, water completely cut off, thereby can avoid because resin bed is exposed to the various mura phenomenons that cause in air.
Brief description of the drawings
In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The schematic top plan view of a kind of array base palte that Fig. 1 provides for the embodiment of the present invention;
Fig. 2 is that the AA ' of array base palte shown in Fig. 1 is to cross-sectional schematic;
The schematic top plan view of resin bed and passivation layer in a kind of array base palte that Fig. 3 provides for the embodiment of the present invention;
The structural representation one of a kind of array base palte that Fig. 4 provides for the embodiment of the present invention;
The structural representation two of a kind of array base palte that Fig. 5 provides for the embodiment of the present invention;
The process schematic diagram of preparing resin bed and passivation layer that Fig. 6 a-6b provides for the embodiment of the present invention;
The process schematic diagram of preparing resin bed that Fig. 7 a-7b provides for the embodiment of the present invention.
Reference numeral:
01-array base palte; 10-underlay substrate; 20-thin film transistor (TFT); 201-grid; 202-gate insulation layer; 203-semiconductor active layer; 204-source electrode; 205-drain electrode; 206-grid line; 207-data line; 30-resin bed; 30a-photoresist film; The complete exposed portion of 30a1-photoresist; 30a2-photoresist unexposed portion; 301-the first via hole; 40-pixel electrode; 50-passivation layer; 501-the second via hole; 60-public electrode; 70-adhesion layer.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.
The embodiment of the present invention provides a kind of array base palte 01, as illustrated in fig. 1 and 2, this array base palte 01 comprises underlay substrate 10, be successively set on described underlay substrate 10 thin film transistor (TFT) 20, resin bed 30 and pixel electrode 40, on this basis, described array base palte 01 also comprises the passivation layer 50 being arranged between described resin bed 30 and described pixel electrode 40, and described passivation layer 50 wraps up described resin bed 30 completely.
Wherein, described thin film transistor (TFT) 20 comprises grid 201, gate insulation layer 202, semiconductor active layer 203, source electrode 204 and drain electrode 205.Described array base palte also comprises the grid line 206 being electrically connected with described grid 201, the data line 207 being electrically connected with described source electrode 204.
It should be noted that, the first, the type of described thin film transistor (TFT) 20 is not limited, it can be top gate type, can be also bottom gate type.
The second, the material of the semiconductor active layer 203 to described thin film transistor (TFT) 20 does not limit, and it can be amorphous silicon, metal oxide etc.
Wherein, in the time that the material of described semiconductor active layer 203 is amorphous silicon, preferably between described semiconductor active layer 203 and described source electrode 204, drain electrode 205, ohmic contact layer is set.In the time that the material of described semiconductor active layer 203 is metal-oxide semiconductor (MOS), while forming described source electrode 204 and described drain electrode 205 for fear of etching, described semiconductor active layer 203 is impacted, preferably, before forming the described source electrode 204 of the rear formation of described semiconductor active layer 203 and described drain electrode 205, form etching barrier layer.
In addition, the material of described semiconductor active layer 203 can be also other, specifically can set according to actual conditions, does not limit at this.
The 3rd, described passivation layer 50 can contact with described resin bed 30, also can between described passivation layer 50 and described resin bed 30, other patterned layer be set, as long as in the final described array base palte 01 forming, described passivation layer 50 wraps up described resin bed 30 completely.
Wherein, described passivation layer 50 wraps up described resin bed 30 completely, be: the projection of described resin bed 30 on described underlay substrate 10 is overlapped in the projection of described passivation layer 50 on described underlay substrate 10 completely, and the size of the projection of described passivation layer 50 on described underlay substrate 10 is greater than the size of the projection of described resin bed 30 on described underlay substrate 10.
The embodiment of the present invention provides a kind of array base palte 01, comprise underlay substrate 10, be successively set on thin film transistor (TFT) 20, resin bed 30 and pixel electrode 40 on described underlay substrate, on this basis, described array base palte 01 also comprises the passivation layer 50 being arranged between described resin bed 30 and described pixel electrode 40, and described passivation layer 50 wraps up described resin bed 30 completely.
Because described resin bed 30 is between described thin film transistor (TFT) 20 and described pixel electrode 40, therefore, no matter be top gate type thin film transistor or bottom gate thin film transistor, the array base palte that the embodiment of the present invention provides, all can increase between grid 201 and pixel electrode 40, distance between drain electrode 205 or grid 201 and pixel electrode 40, thereby can solve grid 201 and drain stray capacitance between 205 and pixel electrode 40 are subject to the problem that data line 207 or grid line 206 disturb.On this basis, owing to being also provided with the passivation layer 50 of the described resin bed 30 of parcel, described passivation layer 50 can make described resin bed 30 and air, water completely cut off, thereby can avoid because resin bed 30 is exposed to the various mura phenomenons that cause in air.
In the time that this array base palte 01 is applied to liquid crystal indicator, exert an influence for fear of the transmitance to liquid crystal indicator, in the embodiment of the present invention, the material of described resin bed 30 is preferably set to have to the resin material of high permeability.
On this basis, the material of described resin bed 30 is preferably photoresist material, can simplify like this processing step while forming described resin bed 30, and saves cost.
Preferably, as shown in Figure 3, the edge 1000-2000 μ m of underlay substrate 10 described in the Edge Distance of described resin bed 30; The edge of described passivation layer 50 flushes with the edge of described underlay substrate 10.
By in the time forming described resin bed 30, make the edge 1000-2000 μ m of underlay substrate 10 described in the Edge Distance of described resin bed 30, can be in the time of the described passivation layer 50 of follow-up formation, easily make described passivation layer 50 wrap up described resin bed 30 completely,, be unlikely to because the Edge Distance of underlay substrate 10 described in the Edge Distance of resin bed 30 is too little, and cannot form in the side of described resin bed 30 appropriate section of described passivation layer 30.
Preferably, the array base palte 01 that the embodiment of the present invention provides goes for the production of a senior super dimension switch technology (Advanced Super Dimensional Switching is called for short ADS) type liquid crystal indicator.Wherein, a senior super dimension switch technology, its core technology characteristic description for: the electric field producing by electric field that in same plane, gap electrode edge produces and gap electrode layer and plate electrode interlayer forms multi-dimensional electric field, make in liquid crystal cell between gap electrode, directly over electrode, all aligned liquid-crystal molecules can both produce rotation, thereby improved liquid crystal work efficiency and increased light transmission efficiency.A senior super dimension switch technology can improve the picture quality of TFT-LCD product, has high resolving power, high permeability, low-power consumption, wide visual angle, high aperture, low aberration, without advantages such as water of compaction ripples (Push Mura).
Therefore, as shown in Figure 4, described array base palte 01 also comprises and is arranged on public electrode 60 between described resin bed 30 and described passivation layer 50.
Wherein, described public electrode 60 is plate electrode, and described pixel electrode 40 is gap electrode.
Here, described public electrode 60 is arranged on to described resin bed 30 tops, can also avoids public electrode 60 to be subject to the interference of data line 207 or grid line 206.
Based on above-mentioned, preferred, as shown in Figure 5, described array base palte 01 also comprises and is arranged on described resin bed 30 near described underlay substrate 10 1 sides and the adhesion layer 70 that contacts with described resin bed 30; Wherein, described adhesion layer 70 is for strengthening the adhesiveness of described resin bed 30.
Here, because resin bed 30 is strong not with the rete bond strength being in contact with it, therefore adopt described adhesion layer 70 strengthen described resin bed 30 and be positioned at for example source electrode 204 of the most close described resin bed 30 of thin film transistor (TFT) 20 of described resin bed 30 belows and the bond strength of drain electrode 205, its material can be selected for example silicon nitride.
It should be noted that, the size of described adhesion layer 70 can be in full accord with the size of described resin bed 30, in the case, can adopt common mask plate to form described adhesion layer 70 and described resin bed 30 by a composition technique simultaneously; Certainly, the size of described adhesion layer 70 can be inconsistent with the size of described resin bed 30, in the case, can be according to actual conditions, adopt composition technique once or twice to form described adhesion layer 70 and described resin bed 30; Specifically can set according to actual conditions, not limit at this.
The embodiment of the present invention also provides a kind of liquid crystal indicator, comprises above-mentioned array base palte 01.
Herein, described in the embodiment of the present invention, liquid crystal indicator can be specifically product or the parts that liquid crystal display, LCD TV, digital album (digital photo frame), mobile phone, panel computer etc. have any Presentation Function.
The embodiment of the present invention also provides a kind of preparation method of array base palte 01, shown in figure 1 and Fig. 2, the method comprises: on underlay substrate 10, form successively thin film transistor (TFT) 20, resin bed 30 and pixel electrode 40, on this basis, described method is also included between described resin bed 30 and described pixel electrode 40 and forms passivation layer 50, and described passivation layer 50 wraps up described resin bed 30 completely.
Wherein, described thin film transistor (TFT) 20 comprises grid 201, gate insulation layer 202, semiconductor active layer 203, source electrode 204 and drain electrode 205.Described array base palte also comprises the grid line 206 being electrically connected with described grid 201, the data line 207 being electrically connected with described source electrode 204.
Because described resin bed 30 is formed between described thin film transistor (TFT) 20 and described pixel electrode 40, therefore, no matter be top gate type thin film transistor or bottom gate thin film transistor, the array base palte that the embodiment of the present invention provides, all can increase between grid 201 and pixel electrode 40, distance between drain electrode 205 or grid 201 and pixel electrode 40, thereby can solve grid 201 and drain stray capacitance between 205 and pixel electrode 40 are subject to the problem that data line 207 or grid line 206 disturb.On this basis, owing to being also provided with the passivation layer 50 of the described resin bed 30 of parcel, described passivation layer 50 can make described resin bed 30 and air, water completely cut off, thereby can avoid because resin bed 30 is exposed to the various mura phenomenons that cause in air.
Preferably, forming described resin bed 30 and described passivation layer 50 specifically can comprise the steps:
S101, as shown in Figure 6 a, is being formed with on the substrate of described thin film transistor (TFT) 20, forms described resin bed 30 by a composition technique, and described resin bed 30 comprises the first via hole 301 that exposes described drain electrode 205; Wherein, the edge 1000-2000 μ m of underlay substrate 10 described in 30 Edge Distances of described resin bed.
Wherein, preferably the material of described resin bed 30 is set to have the resin material of high permeability.On this basis, the material of described resin bed 30 is preferably photoresist material, can simplify like this processing step while forming described resin bed 30, and saves cost.
S102, as shown in Figure 6 b, is being formed with on the substrate of described resin bed 30, forms described passivation layer 50 by a composition technique, and described passivation layer 50 comprises second via hole 501 corresponding with described the first via hole 301; Wherein, the edge of described passivation layer 50 flushes with the edge of described underlay substrate 10.
On this basis, the described pixel electrode 40 of follow-up formation just can be electrically connected with described drain electrode 205 by described the second via hole 501 and described the first via hole 301.
Further, above-mentioned steps S101, specifically can realize as follows:
S1011, as shown in Figure 7a, is being formed with on the substrate of described thin film transistor (TFT) 20, forms photoresist film 30a.
S1012, as shown in Figure 7b, adopts normal masks plate to being formed with the base board to explosure of described photoresist film 30a, forms the complete exposed portion 30a1 of photoresist and photoresist unexposed portion 30a2; Wherein, the region of at least corresponding described the first via hole 301 of the complete exposed portion 30a1 of described photoresist and the fringe region of described underlay substrate 10, corresponding other regions of described photoresist unexposed portion 30a2.
S1013, with reference to shown in figure 6a, after development, described photoresist unexposed portion 30a2 forms described resin bed 30.
Based on above-mentioned, preferred, shown in figure 4, described method also comprises: between described resin bed 30 and described passivation layer 50, form public electrode 60; Wherein, in the position of described the first via hole 301 and described the second via hole 501 correspondences, described public electrode 60 disconnects.
Here, described public electrode 60 is arranged on to described resin bed 30 tops, can also avoids public electrode 60 to be subject to the interference of data line 207 or grid line 206.
Further preferred, shown in figure 5, described array base palte 01 also comprises and is formed on described resin bed 30 near described underlay substrate 10 1 sides and the adhesion layer 70 that contacts with described resin bed 30; Wherein, described adhesion layer 70 is for strengthening the adhesiveness of described resin bed 30.
Here, adopt described adhesion layer 70 strengthen described resin bed 30 and be positioned at for example source electrode 204 of the most close described resin bed 30 of thin film transistor (TFT) 20 of described resin bed 30 belows and the bond strength of drain electrode 205, its material can be selected for example silicon nitride.
It should be noted that, the size of described adhesion layer 70 can be in full accord with the size of described resin bed 30, in the case, can adopt common mask plate to form described adhesion layer 70 and described resin bed 30 by a composition technique simultaneously; Certainly, the size of described adhesion layer 70 can be inconsistent with the size of described resin bed 30, in the case, can be according to actual conditions, adopt composition technique once or twice to form described adhesion layer 70 and described resin bed 30; Specifically can set according to actual conditions, not limit at this.
The above; be only the specific embodiment of the present invention, but protection scope of the present invention is not limited to this, any be familiar with those skilled in the art the present invention disclose technical scope in; can expect easily changing or replacing, within all should being encompassed in protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of described claim.
Claims (10)
1. an array base palte, comprise underlay substrate, be successively set on thin film transistor (TFT), resin bed and pixel electrode on described underlay substrate, it is characterized in that, described array base palte also comprises the passivation layer being arranged between described resin bed and described pixel electrode, and described passivation layer wraps up described resin bed completely.
2. array base palte according to claim 1, is characterized in that, the edge 1000-2000 μ m of underlay substrate described in the Edge Distance of described resin bed;
The edge of described passivation layer flushes with the edge of described underlay substrate.
3. array base palte according to claim 1, is characterized in that, described array base palte also comprises and is arranged on public electrode between described resin bed and described passivation layer.
4. according to the array base palte described in claims 1 to 3 any one, it is characterized in that, the material of described resin bed is photoresist.
5. according to the array base palte described in claims 1 to 3 any one, it is characterized in that, described array base palte also comprises and is arranged on described resin bed near described underlay substrate one side and the adhesion layer that contacts with described resin bed;
Wherein, described adhesion layer is for strengthening the adhesiveness of described resin bed.
6. a liquid crystal indicator, is characterized in that, comprises the array base palte described in claim 1 to 5 any one.
7. the preparation method of an array base palte, comprise: on underlay substrate, form successively thin film transistor (TFT), resin bed and pixel electrode, it is characterized in that, described method is also included between described resin bed and described pixel electrode and forms passivation layer, and described passivation layer wraps up described resin bed completely.
8. method according to claim 7, is characterized in that, forms described resin bed and described passivation layer comprises:
On the substrate that is formed with described thin film transistor (TFT), form described resin bed by a composition technique, described resin bed comprises the first via hole of the drain electrode of exposing described thin film transistor (TFT); Wherein, the edge 1000-2000 μ m of underlay substrate described in the Edge Distance of described resin bed;
On the substrate that is formed with described resin bed, form described passivation layer by a composition technique, described passivation layer comprises second via hole corresponding with described the first via hole; Wherein, the edge of described passivation layer and the edge of described underlay substrate flush.
9. method according to claim 8, is characterized in that, described on the substrate that is formed with described thin film transistor (TFT), forms described resin bed by a composition technique, comprising:
On the substrate that is formed with described thin film transistor (TFT), form photoresist film;
Adopt normal masks plate to being formed with the base board to explosure of described photoresist film, form the complete exposed portion of photoresist and photoresist unexposed portion; Wherein, the region of at least corresponding described the first via hole of the complete exposed portion of described photoresist and the fringe region of described underlay substrate, corresponding other regions of described photoresist unexposed portion;
After development, described photoresist unexposed portion forms described resin bed.
10. according to the method described in claim 7 to 9 any one, it is characterized in that, described method also comprises: between described resin bed and described passivation layer, form public electrode; Wherein, in described the first via hole and position corresponding to described the second via hole, described public electrode disconnects.
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| WO2022036748A1 (en) * | 2020-08-19 | 2022-02-24 | 武汉华星光电技术有限公司 | Array substrate, array substrate manufacturing method, and liquid crystal display panel |
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Application publication date: 20141119 |