CN104145537A - Method for manufacturing thin-line circuit - Google Patents
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- CN104145537A CN104145537A CN201380010024.9A CN201380010024A CN104145537A CN 104145537 A CN104145537 A CN 104145537A CN 201380010024 A CN201380010024 A CN 201380010024A CN 104145537 A CN104145537 A CN 104145537A
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Abstract
The invention relates to a method for manufacturing a thin-line circuit in manufacture of a printed circuit board, an IC substrate, etc. According to the method, a first conductive layer (10) on a smooth surface and a second conductive layer (11) which is arranged on a coarse wall (5b) of at least one opening (4) formed after deposition of the first conductive layer and is selected from a conductive polymer, a colloid noble metal and a conductive carbon particle are used.
Description
Technical field
The present invention relates to a kind of method of manufacturing printed circuit board (PCB), IC substrate etc.More particularly, the present invention relates to a kind of method of manufacturing fine line circuitry.
Background technology
The continuous microminiaturization of the feature of HDI printed circuit board (PCB), IC substrate etc. need to be than the more advanced manufacture method of conventional method (as formed circuit by printing and engraving method).
In a kind of technique, the method for known manufacture fine line circuitry is semi-additive process (SAP), and it for example, starts from exposed dielectric stack layers 1 (its at least a portion at dorsal part has copper region (it can be () contact area 2)) and the second dielectric layer 3 of being attached to the dorsal part of dielectric stack layers 1.Described substrate is illustrated in Fig. 1 a.For example, form at least one perforate 4 (as Microvia) by () laser drill in stack layer 1, it extends through described substrate, and to the copper region 2 on the dorsal part of stack layer 1, (Fig. 1 b).In next step, the dielectric surface of stack layer 1 is carried out to de-smear technique, it causes the roughened surface 5b of the roughening top surface 5a of stack layer 1 and the dielectric sidewall of at least one perforate 4, and (Fig. 1 is c).
Need for example, to make roughening top surface 5a and roughening sidewall 5b further activate and electroplate without electric formula for follow-up copper by () deposition containing the activator of noble metal.Then, by one conductive seed 6 (it is generally made of copper) being deposited to without electric formula plating, on the roughening top surface 5a of stack layer 1 and the roughening sidewall 5b of at least one perforate 4, (Fig. 1 d).Described conductive layer 6 has the thickness of 0.8 μ m to 1.5 μ m conventionally, needs described thickness: a) on roughening top surface 5a, to provide sufficient conductivity to electroplate for subsequent copper; And b) conductivity guaranteeing also to provide sufficient during without electric formula electro-coppering to the roughening sidewall 5b of at least one perforate 4.
Then, thicker copper layer 8 is optionally electroplated onto in the perforate of patterned resist layer 7 and (Fig. 1 e is to f) in the roughening of stack layer 1 and the roughening of activation top surface and at least one perforate 4 and activation dielectric walls.(Fig. 1 g) and remove those parts that cover without electro-coppering 8 of conductive layer 6 by difference etching method (Fig. 1 h) to remove patterned resist layer 7.Described technique is disclosed in (for example) US 6,278, and 185B1 and US 6,212, in 769B1.
A shortcoming of SAP method is the weak adherence between conductive layer 6 and the dielectric surface of stack layer 1.Described weak adherence can cause in the subsequent fabrication steps of printed circuit board (PCB) or follow-up use, occurring unexpected layering by subsequently copper being electroplated onto to the copper track that forms on conductive layer 6.
In addition, the de-smear technique that puts on the top surface of stack layer 1 causes the roughening of dielectric surface.On the one hand, need to make described dielectric surface roughening to provide adherence between described dielectric surface and conductive layer 6; On the other hand, the roughening top surface 5a of stack layer 1 does not allow to form fine line circuitry (if live width and wire spacing are 10 μ m or less fine line circuitry).
The roughening top surface of stack layer 1 needs harsh etching condition, to remove those regions that cover without electro-coppering 8 of conductive layer 6.Harsh etching condition causes the unexpected erosion of copper layer 8 and cannot realize the required form of electro-coppering feature.
A kind of adhesive method of the first metal layer on smooth dielectric surface of improving is disclosed in US 2011/0247865A1.Can and the polymer adhesion coating of plating catalyst or its precursor phase mutual reactance be deposited on smooth dielectric layer and increase thus described dielectric layer and the first metal layer deposited thereon between adherence.In the time that the contact pad from through hole and sidewall remove the glue slag that forms during described through hole forms and other unexpected residue, described polymer adhesion coating suffers erosion.The forcibly metallization in subsequent process steps for described through hole of described cleaning.Therefore, form unexpected wedge in the interface of the sidewall of described polymer adhesion coating/the first metal layer/described through hole, and therefore the adherence of described the first metal layer on described smooth dielectric surface reduces.
object of the present invention
Therefore, object of the present invention is for providing a kind of method of manufacturing fine line circuitry, its avoid being derived from make the top surface roughening of stack layer 1 and afterwards by conductive layer deposition to the shortcoming on described roughening top surface or make it drop to minimum level, and between conductive layer 6 and the top surface of stack layer 1, provide sufficient adherence simultaneously.
Summary of the invention
This target solves by the method for manufacturing fine line circuitry, and described method sequentially comprises following steps:
(i) provide have the dielectric stack layers 1 of front side 1a and dorsal part 1b surf zone and wherein at least a portion of back surface region 1b comprise copper region 2, and wherein make dielectric layer 3 be attached to described back surface region 1b and the adhesion promoter layer 9 of the group of the nano-scale oxide particle composition that wherein makes to select free organic silane compound, the porphyrin being substituted, copper precursor compound and have at least one adherance that contains the chemical functional group who is adapted to be incorporated into substrate is attached to the front side 1a surf zone of stack layer 1;
(ii) the first conductive layer 10 is deposited on adhesion promoter layer 9;
(iii) form at least one perforate 4, it extends through the first conductive layer 10, adhesion promoter layer 9 and stack layer 1 at least one copper region 2;
(iv) dielectric sidewall and the copper region 2 of clean at least one perforate 4, to obtain through clean sidewall 5b and through clean copper region 2;
(v) at least on clean sidewall 5b, forming the second conductive layer 11, colloidal solid, conductive carbon particle and the group by the copper composition without electric formula electroplating deposition that wherein the second conductive layer 11 selects free conducting polymer, comprises noble metal;
(vi) resist layer 7 is applied on the first conductive layer 10 or on the second conductive layer 11 in order to avoid the second conductive layer 11 passes through the deposited copper without electric formula plating; And make described resist layer 7 patternings;
(vii) by electroplating, copper layer 8 is deposited in the perforate of patterning resist layer 7;
(viii) remove described patterning resist layer 7 and
(ix) remove those parts that cover without copper electroplating layer 8 of the first conductive layer 10 or the second conductive layer 11 in order to avoid the second conductive layer 11 passes through the deposited copper without electric formula plating.
The first conductive layer 10 shows sufficient adherence to the front side 1a surf zone of stack layer 1.In addition; because the front side 1a surf zone of stack layer 1 was not applied to de-smear technique before deposition the first conductive layer 10; and because in the time of the sidewall of clean at least one perforate 4 and copper region 2; the first conductive layer 10 is also as protective layer; so it is smooth that the front side 1a surf zone of stack layer 1 keeps, and therefore to form fine line circuitry (for example live width and wire spacing are 10 μ m or less fine line circuitry) be possible.The smooth front side 1a surf zone of stack layer 1 also allow to use gentle etching condition with in step (ix), remove the first conductive layer 10 completely those in step (vi) and the part that (vii), patterned resist layer 7 covers.
Therefore, can realize the required form of electro-coppering feature, and after the sidewall and copper region 2 of clean described at least one perforate 4, between the front side 1a surf zone of the first conductive layer 10 and stack layer 1, keep high adhesion.
Brief description of the drawings
Fig. 1 shows according to half additive process (SAP) of art methods.
Fig. 2 shows according to the method for manufacture fine line circuitry of the present invention.
Embodiment
The method of manufacturing fine line circuitry is below described in more detail.Diagram shown in literary composition only illustrates described technique.Described diagram is not drawn in proportion, that is, it does not reflect actual size or the feature of pressing different layers in layer.In whole description, identical numeral refers to identical element.
Referring now to Fig. 2 a, according to a preferred embodiment of the invention, dielectric stack layers 1 is provided, and it can for example, be made up of organic material or fiber reinforcement organic material or particle enhancing organic material etc. (: epoxy resin, polyimides, bismaleimides-triazine, cyanate, poly-benzocyclobutene or its glass fiber compound material etc.).Stack layer 1 comprises front side 1a and dorsal part 1b.The front side 1a of stack layer 1 is made up of exposed dielectric substance, and it has the smooth surface that comprises adhesion promoter layer 9.At least a portion of the dorsal part 1b of stack layer 1 is attached with copper region 2, and it can be (for example) contact pad, copper filling vias or copper filling micro-blind vias.The dorsal part 1b of stack layer 1 is also attached with the second dielectric layer 3.Described pressure layer is illustrated in Fig. 2 a.
The adhesion promoter layer 9 that is attached to the front side 1a of stack layer 1 can be thin layer, for example, and individual layer, the layer being formed by some individual layers or be distributed in adhesion on the smooth surface of stack layer 1 front side 1a and promote the island of material.Need adhesion promoter layer 9 to realize the abundant adhesion between smooth front side 1a and first conductive layer 10 of stack layer 1.
Preferably, the front side 1a surf zone of stack layer 1 does not stand de-smear method, to keep the smooth surface of described front side 1a surf zone of stack layer 1.Replace the top surface that cleans stack layer 1 by standard method.
Then, adhesion promoter layer 9 is deposited on the top surface of stack layer 1.Suitable deposition process is (for example) dip-coating, spin coating, ink jet printing, spraying and vapour deposition (as chemical vapour deposition (CVD) (CVD) and physical vapour deposition (PVD) (PVD)).
Adhesion promoter layer 9 is preferably selected from:
By the layer that deposits at least one organic silane compound and use subsequently oxidizer treatment to obtain;
Be configured to the organic molecule of bind metal ion, for example, be disclosed in WO 2009/029863A1.Described organic molecule preferably contains the surface activity part that is selected from the front part of large ring, encircles greatly complex compound, sandwich co-ordination complex and polymer thereof.Most preferably, the surface activity part of this type adhesion promoter layer 9 is the porphyrin being substituted;
Copper precursor compound (as N-heterocyclic carbene copper (I) compound being disclosed in US 2009/0004385A1) layer;
Be selected from the nano-scale oxide particle of one or many person in silica, aluminium oxide, titanium oxide, zirconia, tin oxide and Zinc oxide particles, it has at least one adherance that contains the chemical functional group who is adapted to be incorporated into substrate.Suitable functional group is (for example) amino, carbonyl, carboxyl, ester, epoxy radicals, sulfydryl, hydroxyl, acrylic, methacrylic acid group, acid anhydride, acyl halide, halogen, pi-allyl, vinyl, styrene, aryl, acetenyl, nitrogen base changes; 5 to the 6 element heterocycle alkyl that contain 1 to 3 nitrogen-atoms; Nicotimine amide groups, bipyridyl, nitrile, isonitrile and thiocyanates.This type of adhesion promoter layer 9 is disclosed in EP 11191974.2.
Specially suitable adhesion promoter layer 9 can be formed by the method that sequentially comprises following steps:
(a) the front side 1a of the solution-treated stack layer 1 that use comprises at least one organic silane compound; And optionally
(b) use the solution-treated front side 1a that comprises oxidant.
Described organic silane compound is preferably selected from the group being expressed from the next:
A
(4–x)SiB
x
Wherein
Each A is hydrolyzable groups independently,
X is 1 to 3, and
Each B is independently selected from by C
1-C
20the group that alkyl, aryl, aminoaryl and the functional group being represented by following formula form:
C
nH
2nX，
Wherein
N is preferably 0 to 20, and more preferably 0 to 8, and
X is preferably selected from by amino, amide groups, hydroxyl, alkoxyl, halogen, sulfydryl, carboxyl, carboxyl ester, carboxylic acid amides, thiocarboxamide, acyl group, vinyl, pi-allyl, styryl, epoxy radicals, epoxycyclohexyl, glycidoxypropyl, isocyanate group, thiocyano-, sulphur isocyanate group, urea groups, ghiourea group, guanidine radicals, sulphur glycidoxypropyl, acryloxy, methacryloxy, carboxyl ester and Si (OR)
3(wherein R is C
1-C
5alkyl) composition group.
More preferably, hydrolyzable groups A Xuan Zi – OH, – OR
2(and R wherein
2select free C
1-C
5the) of group of alkyl composition is Ji – OCOR
3(and R wherein
3for H or C
1-C
5alkyl).
The example with the particular types compound of above formula is vinyl silanes, aminoalkyl silane, urea groups alkyl silane ester, epoxyalkylsilane and methacryloxy alkyl silane ester, and wherein organic reaction functional group is respectively vinyl, amino, urea groups, epoxy radicals and methacryloxy.The example of vinyl silanes is vinyl trichlorosilane, vinyltriethoxysilane, vinyltrimethoxy silane, vinyl-tri--(β (2)-methoxy ethoxy) silane and vinyltriacetoxy silane.The example of aminoalkyl silane (it is for preferred organosilan of the present invention) is γ-(3)-aminopropyltriethoxywerene werene, gamma-amino propyl trimethoxy silicane, N-β-(aminoethyl)-gamma-amino propyl trimethoxy silicane and N'-(β-aminoethyl)-N-(β-aminoethyl)-gamma-amino propyl trimethoxy silicane.Suitable urea groups alkyl silane ester is γ-urea groups alkyl triethoxysilane, and suitable epoxyalkylsilane is β-(3,4-epoxycyclohexyl)-ethyl trimethoxy silane and γ-glycidoxypropyltrimewasxysilane.Available methacryloxypropyl silane ester is γ-methacryloxypropyl trimethoxy silane and γ-methacryloxypropyl-tri--('beta '-methoxy ethyoxyl) silane.
Described at least one organic silane compound can be monomer organic silane compound or made the oligomerization organic silane compound that monomer organic silane compound of the present invention (part) is hydrolyzed and condensation obtains before on the surface that deposits to dielectric substrate.
The hydrolysis of organic silane compound and condensation are by being known in technique.For example, described monomer organic silane compound for example, is reacted, to generate the settled solution derived from the oligomerization organic silane compound of described monomer organic silane compound with acid catalyst (acetic acid or watery hydrochloric acid).
Described by hydrolysis should comprise within the scope of the invention derived from the oligomerization silane of monomer organic silane compound of the present invention.
At the temperature between between 15 to 50 DEG C, make the front side 1a of stack layer 1 contact the time of 10 seconds to 10 minutes with the solution that comprises at least one organic silane compound.
Then, optionally make the front side 1a of stack layer 1 contact with the solution that comprises oxidant.
Described oxidant can be acidity or the alkaline aqueous solution of permanganate, hydroperoxides and sulfuric acid or chromic acid.
For example, taking the alkaline solution of permanganate (sodium permanganate or potassium permanganate) as preferably.Described solution preferably contains 20-100g/l high manganese ion and 10-40g/l hydroxide ion.Preferred hydroxyl ion source is NaOH or potassium hydroxide.
At the temperature between between 20 to 95 DEG C, the front side 1a that makes stack layer 1 with described in comprise oxidant solution contact for 1 to 30min time, to obtain average surface roughness R
abe less than the roughened surface of 150nm.
After deposition adhesion promoter layer 9, be optionally cured step.Maximum curing temperature is in the scope of 25 to 250 DEG C, more preferably in the scope of 100 to 200 DEG C.
Then, preferably, can make water clean the top surface of stack layer 1.
The adhesion promoter layer 9 that is attached to the front side 1a of stack layer 1 is stablized for the formation that makes the first conductive layer, the combination on the 1a surface, front side without the copper ion in electric formula electroplating bath and stack layer 1 for example, using in stabilizing step (ii) also promotes the deposition of metallic copper.
Then,, in step (ii), the first conductive layer 10 is deposited on adhesion promoter layer 9.This is illustrated in Fig. 2 b.The first conductive layer 10 acts on the conductive matrices of electro-coppering 8 in step (vii) together with the second conductive layer 11 use.
Preferably, the first conductive layer 10 comprises copper and by electroplating to deposit without electric formula.Preferably, in the case, for example, deposited colloid, the solution that comprises precious metal ion that contains noble metal or make described substrate activation the solution that comprises palladium complex before without electric formula deposited copper by ().Most preferred activation is for passing through depositing Pd-tin colloid, palladium ion and palladium complex.Described method is in use for a long time and knows for those skilled in the art in technique.
What be applicable to deposited copper electroplates electrolyte including (for example) copper ion source, pH adjusting agent, complexing agent (as EDTA), alkanolamine or tartrate, accelerator, stabilizer additive and reducing agent without electric formula.In most of the cases, use formaldehyde as reducing agent, other conventional reducing agent is hypophosphites, dimethylamine borane and boron hydride.Be for example compound of mercaptobenzothiazoler, thiocarbamide, various other sulphur compound, cyanide and/or hydroferrocyanate and/or cobaltocyanide, polyethyleneglycol derivative, heterocyclic nitrogen compounds, methyl butynol and propionitrile for electroplating electrolytical typical stabilizer additive without electric formula copper.In addition, often by making stable air stream use molecular oxygen to be used as stabilizer additive (ASM handbook by described copper electrolytes, the 5th volume: Surface Engineering (Surface Engineering), 311-312 page and little C.F Claire (C.F.Coombs, Jr.), " printed circuit handbook (Printed Circuits Handbook) ", 2001, the 5th edition, the 28.5th chapter, the 28.7th to 28.10 pages).
The first conductive layer 10 has 0.01 to 1.5 μ m conventionally, more preferably 0.05 to 0.8 μ m and the most preferably thickness of 0.1 to 0.6 μ m.
The in the situation that of the inventive method, the first conductive layer 10 can be thinner, with the conductive surface that is provided for electroplating, because than the roughening dielectric surface in SAP method situation, can on the 1a surf zone of the smooth front side of stack layer 1, obtain the first conductive layer 10 fully conducting electricity by lower thickness.Comparable another reason thinner in standard SAP method of the first conductive layer 10 is because do not need the first conductive layer 10 to be electroplated onto at least one perforate 4 simultaneously.Advantage without undergoing the front side 1a surf zone of the stack layer 1 of roughening technique before deposition the first conductive layer 10 is: a) when remove those parts that cover without described copper layer 8 of the first conductive layer 10 in step (ix) time, reduce the risk of destroying copper layer 8; And the part of wanting etching removal that b) reduces the first conductive layer 10 is still stayed on the front side 1a surf zone of stack layer 1 and can cause the risk of short circuit.Suitable etchant preferably corrodes the first conductive layer 10 but not copper electroplating layer 8, because have different micro-structural (as particle size) by electroplate and electroplate the copper depositing without electric formula.But in the case of the roughening front side 1a surf zone of stack layer 1, must apply more harsh etching condition, and therefore, cannot avoid in the case the etching of copper electroplating layer 8 to corrode.Therefore, can realize by the inventive method the required form of copper feature (as track).In addition between indivedual features of copper layer 8, unlikely there is, the unexpected residue (it can be short circuit source) of the first conductive layer 10.
Then, for example, form at least one perforate 4 that arrives at least one copper region 2 through the first conductive layer 10, adhesion promoter layer 9 and stack layer 1 downwards by () laser drill, described copper region 2 is as the metal bottom of at least one perforate 4.At least one perforate 4 is (for example) Microvia.The formation of at least one perforate 4 is illustrated in Fig. 2 c.
Then, cleaning procedure is carried out in the sidewall at least one perforate 4 and copper region 2, the glue slag and other residue that while forming at least one perforate 4 to remove, produce.Described cleaning procedure can be de-smear technique.This is feasible, because be attached to the first conductive layer 10 of the front side 1a of stack layer 1 and protect the smooth surface of described front side 1a during the dielectric sidewall of at least one perforate 4 is carried out to de-smear.
Preferably, (Fig. 2 d) sidewall by clean at least one perforate 4 of wet chemistry de-smear method or plasma de-smear method and copper region 2.Described method be known in technique (for example: little C.F. Claire (C.F.Coombs, Jr.), " printed circuit handbook (Printed Circuits Handbook) ", 2001, the 5th edition, the 28.4th chapter, the 28.5th to 28.7 pages).
Wet chemistry de-smear method comprises following steps: a) make the superficial expansion of the dielectric sidewall of at least one perforate 4; Use at least one perforate 4 of permanganate solution etching dielectric sidewall surface and c) remove MnO by reduction from the dielectric sidewall of at least one perforate 4
2.Thus, also the surface in the copper region 2 from least one perforate 4 removes glue slag and other residue from the formation of at least one perforate 4 in step (iii).
Plasma de-smear is Dry chemistry, wherein make the surface of dielectric substrate be exposed to (for example) oxygen and/or fluorocarbon gases (for example CF
4).
After the sidewall and copper region 2 of clean at least one perforate 4, make at least one perforate 4 described at least being deposited to by the second conductive layer 11 that selects free conducting polymer, colloid noble metal granule, conductive carbon particle and form by the one in group form without the copper of electric formula electroplating deposition through cleaning on sidewall 5b.
If apply conducting polymer as the second conductive layer 11, make so described conducting polymer only deposit at least one perforate 4 on clean sidewall 5b.This is illustrated in Fig. 2 e.
Preferably, the conducting polymer that the second conductive layer 11 comprises the group that selects free polythiophene, polypyrrole, polyaniline, its derivative and compositions of mixtures.
Most preferred conducting polymer is selected from polythiophene, its derivative and composition thereof.
The second conductive layer 11 that comprises polythiophene, its derivative and composition thereof described in the method that can sequentially comprise following steps forms:
A) make contacting with water-soluble polymer solution through clean sidewall 5b of at least one perforate 4,
B) use permanganate solution process at least one perforate 4 through clean sidewall 5b, and
C) use the acidic aqueous solution of aqueous matrix that contains at least one thiophene compound and at least one sulfonic acid or acid microemulsion process at least one perforate 4 through clean sidewall 5b.
Described method causes the only selectivity on clean sidewall 5b at least one perforate 4 to form conductive organic polymer.Form without conducting polymer at the first conductive layer 10 and on the copper region 2 of at least one perforate 4 rear exposure of formation.
The group that selects copolymer, polyvinyl alcohol, polyacrylate, polyacrylamide, polyvinylpyrrolidone of free polyvinylamine, polymine, polyvinyl imidazole, alkylamine ethylene oxide copolymer, polyethylene glycol, polypropylene glycol, ethylene glycol and polypropylene glycol and composition thereof to form for step water-soluble polymer a).The concentration of described water-soluble polymer is in 20mg/l arrives the scope of 10g/l.
The solution of described water-soluble polymer can contain water-miscible organic solvent in addition, and it selects the group of half ether and the half ester composition of free ethanol, propyl alcohol, ethylene glycol, diethylene glycol, glycerol, dioxin (dioxin), butyrolactone, 1-METHYLPYRROLIDONE, dimethyl formamide, dimethylacetylamide, ethylene glycol.Described water-miscible organic solvent can respective pure form utilization or is diluted through water.The concentration of described water-miscible organic solvent is in 10ml/l arrives the scope of 200ml/l.During step a), the solution of described water-soluble polymer is remained at the temperature within the scope of 25 DEG C to 85 DEG C, and substrate is immersed in this solution and continues 15 seconds to 15 minutes.
Then, step b) in, the sidewall 5b through this processing of at least one perforate 4 is contacted with permanganate solution.The source of high manganese ion can be any water-soluble permanganate compounds.The source of described high manganese ion is preferably selected from sodium permanganate and potassium permanganate.The concentration of high manganese ion is in 0.1mol/L arrives the scope of 1.5mol/L.Described permanganate solution can be acidity or alkalescence.Preferably, the pH value of described permanganate solution is in 2.5 to 7 scope.By step b), on clean sidewall 5b, form MnO at least one perforate 4
2layer.
Then step c) in, make contacting with the solution that comprises thiophene compound and sulfonic acid through clean sidewall 5b of at least one perforate 4.
Described thiophene compound is preferably selected from the assorted substituted thiophene of 3-and the assorted substituted thiophene of 3,4-.Most preferably, described thiophene compound selects the group of free 3,4-rthylene dioxythiophene, 3-methoxythiophene, 3-methyl-4-methoxythiophene and derivative composition thereof.The concentration of described thiophene compound arrives 1mol/L at 0.001mol/L, more preferably in 0.005mol/L arrives the scope of 0.05mol/L.
Described sulfonic acid is selected from the group that comprises methanesulfonic acid, ethyl sulfonic acid, methane-disulfonic acid, ethionic acid, naphthalene-1-5-disulfonic acid, DBSA, polystyrolsulfon acid and composition thereof.By set-up procedure c) in the required pH value of solution used set the concentration of described sulfonic acid.Preferably, the pH value of described solution is set in 0 to 3 scope, more preferably in 1.5 to 2.1 scope.
When make in c) in step at least one perforate 4 through clean sidewall 5b with described in contain at least one thiophene compound and at least one sulfonic acid the acidic aqueous solution of aqueous matrix or acid microemulsion while contacting, described thiophene compound is at the MnO depositing in b) with step
2polymerization when contact.Then, by by thiophene compound at MnO
2existence under the polythiophene and the derivative thereof that obtain form the second conductive layer 11.
Described method only causes the upper conductive organic polymer that forms of those parts that are made up of dielectric substrate material at substrate surface (be at least one perforate 4 through clean sidewall 5b).The surface of the first conductive layer 10 is not containing the described conductive organic polymer as the second conductive layer 11.
Also can apply and relate to method (the printed circuit handbook (Printed Circuits Handbook) that uses conductive carbon particle (as graphite), the 5th edition, 2001, editor: little C.F Claire (C.F.Coombs, Jr.), the 30.4th to 30.6 pages).First process substrate surface and then apply with conductive carbon particle.Then, be dried described carbon coating and remove the carbon granule part being deposited on the first conductive layer 10.Described carbon coating is as the second conductive layer 11 and be suitable as the surface for electro-coppering.
In another embodiment of the present invention, the second conductive layer 11 forms (printed circuit handbook (Printed Circuits Handbook) by colloid noble metal, 2001, the 5th edition, editor: little C.F Claire (C.F.Coombs, Jr.), the 30.2nd to 30.4 pages).Can for example, between the indivedual colloid palladium particles that are adsorbed onto substrate surface, provide sulphur " bridge " to increase the conductivity of colloid palladium particle by ().Therefore, the conductivity of described absorption colloid palladium particle is high enough to as the second conductive layer 11 for follow-up electro-coppering.
In another embodiment of the present invention, the second conductive layer 11 is by forming without electric formula electro-coppering.Described copper be deposited to the first conductive layer 10, at least one perforate 4 on clean sidewall 5b and copper region 2.Preferably, before depositing the copper as the second conductive layer 11 without electric formula, remove described the first conductive layer 10.Therefore, in this embodiment, the second conductive layer 11 deposits on the front side 1a surf zone of stack layer 1, at least one perforate 4 on clean sidewall 5b and copper region 2.Preferably, in the case, between step (iv) and step (v), remove the first conductive layer 10.
Then, anticorrosive additive material be deposited on the first conductive layer 1 and make its patterning to form patterning resist layer 7.This is illustrated in Fig. 2 f.The negative image that patterning resist layer 7 is the circuit pattern that deposits by electro-coppering in next step.
Photoetching process order for imaging (patterning) relates to substantially: photopolymer materials (erosion resistant) is applied to the first conductive layer 10; Make this photoresist with required pattern exposure; And exposing patterns is developed.Liquid and desciccator diaphragm erosion resistant all can be used for forming patterning resist layer 7.Preferably, form described patterning resist layer 8 with dry film erosion resistant.
Suitable erosion resistant, make it be deposited on substrate surface and the method that forms pattern by being known (little C.F Claire (C.F.Coombs in technique, Jr.), " printed circuit handbook (Printed Circuits Handbook) ", 2001, the 5th edition, the 26th chapter, the 26.1st to 26.30 pages).
Then, clean the surface of described substrate and then make it be suitable for forming copper deposit 8 by electro-coppering.Be illustrated in Fig. 2 g through the substrate of electroplating.
The electroplating solution that is applicable to the copper deposition of step (viii) is known in technique.Preferably, use the acid copper electroplating bath that comprises copper ion, acid, organic additive and chloride ion.Described copper electroplating bath composition is disclosed in (for example) little C.F Claire (C.F.Coombs, Jr.), " printed circuit handbook (Printed Circuits Handbook) ", 2001, the 5th edition, the 29.4th chapter, in the 29.4th to 29.15 pages.
Then, remove patterning resist layer 7 by method known in technique.Peelable, dissolving, ablation or remove patterning resist layer 7 by other method.Peel off and be dissolved as wet chemical process, and ablation utilization (for example) laser beam so that patterning resist layer 7 evaporate.This is illustrated in Fig. 2 h.The wet chemical process that is applicable to remove patterning resist layer 7 is described in (for example) little C.F Claire (C.F.Coombs, Jr.), " printed circuit handbook (Printed Circuits Handbook) ", 2001, the 5th edition, 26.6.6 chapter, the 26.27th page and 33.3.2 chapter, in the 33.5th page.
Can (for example) at high temperature remove patterning resist layer 7 completely with NaOH or the potassium hydroxide solution realization of 1 molar concentration or higher molar concentration, wherein often use rust-inhibiting additive with limit copper oxidation.In addition, can remove patterning resist layer 7 by one or many person in following material: halogenated hydrocarbons (as carrene), amine and derivative thereof (as methyl-sulfoxide, dimethyl formamide, METHYLPYRROLIDONE), glycol ethers (as glycol monoethyl ether), ethanol, ketone (as methylethylketone and acetone) and for example isopropyl alcohol, sulfuric acid, ammonium persulfate and caustic alkali and amphyl material and other different materials of mixture.
For example may need, according to adjust solution kind and parameter time of contact and the solution temperature of solution (with) for the type of the erosion resistant of patterning resist layer 7.Described adjustment is common program to those of ordinary skill in the art.
A kind of method that is specially adapted to remove patterning resist layer 7 is disclosed in EP 1904898B1, and described method comprises following steps:
A) use the aqueous solution that contains alkali to process substrate; And
B) after this, the solution that use contains alkali and at least one stripping enhancing agent is further processed described substrate, wherein said at least one stripping enhancing agent selects free hexylene glycol, ethylene glycol monoethyl ether, ethylene glycol monobutyl ether, ethylene glycol list isopropyl ether, propylene glycol monomethyl ether, dihydroxypropane single-ether, propylene glycol monobutyl ether, diethylene glycol monomethyl ether, diethylene glycol monoethyl ether, Diethylene glycol monopropyl ether, diethylene glycol monobutyl ether, dipropylene glycol monomethyl ether, DPE, DPG list propyl ether, Dipropylene glycol mono-n-butyl Ether, triethylene glycol monomethyl ether, Triethylene glycol ethyl ether, Triethylene glycol Monoisopropyl Ether, triethylene glycol butyl ether, Tripropylene glycol monomethyl Ether, tripropylene glycol list ether, Tripropylene glycol Propyl Ether, Tri(propylene glycol)butyl ether,mixture of isomers, the group of ethylene glycol list isopropyl ether and propylene glycol methyl ether acetate composition.
In step (ix), remove the part that those patterned resist layers 7 of the first conductive layer 10 cover and therefore cover without electro-coppering deposit 8.This is illustrated in Fig. 2 i.Can be for example, by () as difference etching (the little C.F Claire (C.F.Coombs that establishes technique, Jr.), " printed circuit handbook (Printed Circuits Handbook) ", 2001, the 5th edition, the 33.4th chapter, the 33.6th to 33.18 pages) remove described part.In normal experiment, select suitable etching solution and etching condition.Preferred etch combination be selected from sulfuric acid-peroxide etchant and comprise iron chloride and ferric sulfate in one or many person's etchant.
The inventive method is many-sided with respect to the advantage of SAP method known in technique:
Adhesion promoter 9 is applied on the front side 1a surf zone of stack layer 1 and allows to avoid for example, to make front side 1a surf zone roughening by () de-smear method, so that the abundant adherence to the first conductive layer 10 to be provided.The impact of the smooth front side 1a surf zone of stack layer 1 is as follows:
Compared with implementing the art methods of roughening of described front side 1a surf zone, on the 1a surf zone of the front side of stack layer 1, manufacturing live width and wire spacing is that 10 μ m or less fine line circuitry are feasible.
Compared with the roughening front side 1a surf zone of stack layer 1, can reduce the thickness of the first conductive layer 10, this allows laser after forming the first conductive layer 10 to get out at least one perforate 4.
In addition be deposited on, the very difficulty of difference etching of the first conductive layer 10 on the smooth front side 1a surf zone of stack layer 1.This reduces the risk of the short circuit causing due to the nubbin of the first conductive layer 10 after etching and reduces in addition the erosion to copper layer 8 during etching step (ix).The shape of the electro-coppering feature therefore, obtaining by the inventive method improves.
Claims (14)
1. manufacture a method for fine line circuitry, it comprises following steps in the following order:
(i) provide there is front side (1a) and the dielectric stack layers (1) of dorsal part (1b) surf zone and at least a portion of wherein said dorsal part (1b) surf zone to comprise copper region (2), and wherein make dielectric layer (3) be attached to described dorsal part (1b) surf zone and wherein make adhesion promoter layer (9) be attached to described front side (1a) surf zone of described stack layer (1), described adhesion promoter layer (9) selects free organic silane compound, the porphyrin being substituted, copper precursor compound and there is the group of the nano-scale oxide particle composition of at least one adherance that contains the chemical functional group who is adapted to be incorporated into substrate,
(ii) the first conductive layer (10) is deposited on described adhesion promoter layer (9);
(iii) form at least one perforate (4), it extends through described the first conductive layer (10), described adhesion promoter layer (9) and described stack layer (1) to described at least one copper region (2);
(iv) dielectric sidewall and the described copper region (2) of clean described at least one perforate (4), to obtain through clean sidewall (5b) and through clean copper region (2);
(v) at upper the second conductive layer (11) that forms of the clean sidewall (5b) of at least described warp, colloidal solid, conductive carbon particle and the group by the copper composition without electric formula electroplating deposition that wherein said the second conductive layer (11) selects free conducting polymer, comprises noble metal;
(vi) resist layer (7) is applied on described the first conductive layer (10) or on described the second conductive layer (11) in order to avoid described the second conductive layer (11) passes through the deposited copper without electric formula plating; And make described resist layer (7) patterning;
(vii) by electroplating, copper layer (8) is deposited in the described perforate of described patterning resist layer (7);
(viii) remove described patterning resist layer (7) and
(ix) remove those parts that cover without described copper electroplating layer (8) of described the first conductive layer (10) or described the second conductive layer (11) in order to avoid described the second conductive layer (11) passes through the deposited copper without electric formula plating.
2. the method for manufacture fine line circuitry according to claim 1, wherein said adhesion promoter layer (9) forms by following steps:
(a) surface described in the solution-treated that use comprises at least one organic silane compound; And
(b) surface described in the solution-treated that use comprises oxidant.
3. according to the method for the manufacture fine line circuitry described in claim 1 and 2, wherein said at least one organic silane compound is expressed from the next:
A
(4–x)SiB
x
Wherein
Each A is hydrolyzable groups,
X is 1 to 3, and
Each B is independently selected from by C
1-C
20the group that alkyl, aryl, aminoaryl and the functional group being expressed from the next form:
C
nH
2nX，
Wherein
N is 0 to 15, and
X selects free amino group, amide groups, hydroxyl, alkoxyl, halogen, sulfydryl, carboxyl, carboxyl ester, carboxylic acid amides, thiocarboxamide, acyl group, vinyl, pi-allyl, styryl, epoxy radicals, epoxycyclohexyl, glycidoxypropyl, isocyanate group, thiocyano-, sulphur isocyanate group, urea groups, ghiourea group, guanidine radicals, sulphur glycidoxypropyl, acryloxy, methacryloxy, carboxyl ester and Si (OR)
3the group of composition,
And wherein R is C
1-C
5alkyl.
4. the method for manufacture fine line circuitry according to claim 3, wherein said hydrolyzable groups A selects free – OH, – OR
2(and R wherein
2select free C
1-C
5the) of group of alkyl composition is Ji – OCOR
3(and R wherein
3for H or C
1-C
5alkyl) composition group.
5. according to the method for the manufacture fine line circuitry described in claim 2 to 4, the alkaline aqueous solution that wherein said oxidant is high manganese ion.
6. according to the method for the manufacture fine line circuitry described in arbitrary claim in previous claim, wherein said the first conductive layer (10) comprises by the copper without electric formula electroplating deposition.
7. according to the method for the manufacture fine line circuitry described in arbitrary claim in previous claim, wherein said at least one perforate (4) forms by laser drill.
8. according to the method described in arbitrary claim in previous claim, the described dielectric sidewall of wherein said at least one perforate (4) and described copper region (2) are clean by de-smear method.
9. according to the method for the manufacture fine line circuitry described in arbitrary claim in previous claim, wherein said the second conductive layer (11) comprises conducting polymer, and it selects the group of free polythiophene, polypyrrole, polyaniline, its derivative and compositions of mixtures.
10. according to the method for the manufacture fine line circuitry described in arbitrary claim in previous claim, wherein form described the second conductive layer (11) in step (v) by following steps:
(v) a) make the clean sidewall (5b) of described warp of described at least one perforate (4) contact with water-soluble polymer solution,
(v) b) use permanganate solution to process the clean sidewall (5b) of described warp of described at least one perforate (4), and
(v) c) use the acidic aqueous solution of the aqueous matrix that contains at least one thiophene compound and at least one sulfonic acid or the clean sidewall (5b) of described warp of described at least one perforate (4) of acid microemulsion processing.
The method of 11. manufacture fine line circuitry according to claim 10, wherein said water-soluble polymer selects the group of copolymer, polyvinyl alcohol, polyacrylate, polyacrylamide, polyvinylpyrrolidone of free polyvinylamine, polymine, polyvinyl imidazole, alkylamine ethylene oxide copolymer, polyethylene glycol, polypropylene glycol, ethylene glycol and polypropylene glycol and composition thereof composition.
12. according to the method for the manufacture fine line circuitry described in arbitrary claim in claim 10 and 11, and wherein said at least one thiophene compound selects the group of the assorted substituted thiophene of free 3-and the assorted substituted thiophene composition of 3,4-.
13. according to the method for the manufacture fine line circuitry described in arbitrary claim in claim 10 to 12, wherein said at least one sulfonic acid is selected from and comprises methanesulfonic acid, ethyl sulfonic acid, methane-disulfonic acid, ethionic acid, naphthalene-1, the group of 5-disulfonic acid, DBSA, polystyrolsulfon acid and composition thereof.
14. according to the method for the manufacture fine line circuitry described in arbitrary claim in claim 10 and 13, and the pH value of the wherein said solution that comprises at least one thiophene compound and at least one sulfonic acid is in 0 to 3 scope.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP12750351 | 2012-03-29 | ||
| EP120750351 | 2012-03-29 | ||
| PCT/EP2013/052318 WO2013143732A1 (en) | 2012-03-29 | 2013-02-06 | Method for manufacture of fine line circuitry |
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| Publication Number | Publication Date |
|---|---|
| CN104145537A true CN104145537A (en) | 2014-11-12 |
Family
ID=51853646
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201380010024.9A Pending CN104145537A (en) | 2012-03-29 | 2013-02-06 | Method for manufacturing thin-line circuit |
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| CN111690957A (en) * | 2019-08-12 | 2020-09-22 | 长春石油化学股份有限公司 | Surface-treated copper foil |
| CN114556065A (en) * | 2019-05-08 | 2022-05-27 | 沃扎诺有限公司 | Substrate comprising nanowires |
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