CN104143985A - 数字模拟转换器、可编程伽玛校正缓冲电路及显示装置 - Google Patents
数字模拟转换器、可编程伽玛校正缓冲电路及显示装置 Download PDFInfo
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Abstract
本发明公开一种数字模拟转换器,用以根据N位的第一数字信号输出第一输出模拟电压或根据N位的第二数字信号输出第二输出模拟电压,其包括:第一电压产生器(210),耦接于第一参考电压与第二参考电压之间,用于产生介于第一参考电压与第二参考电压之间的2N个第一模拟电压;第一电压选择器(220),根据N位的第一数字信号从2N个第一模拟电压中选择出第一输出模拟电压;第二电压产生器(230),耦接于第二参考电压与第三参考电压之间,用于产生介于第二参考电压与第三参考电压之间的2N个第二模拟电压;第二电压选择器(240),根据N位的第二数字信号从2N个第二模拟电压中选择出第二输出模拟电压。本发明还公开一种可编程伽玛校正缓冲电路及显示装置。
Description
技术领域
本发明涉及一种数字模拟转换器、可编程伽玛校正缓冲电路及显示装置。
背景技术
在液晶显示装置(LCD)中,大多数会设置伽马校正电路来产生伽马校正电压,以进行影像的伽马校正。源极驱动电路会依据伽马校正信号来产生液晶显示装置所需的驱动信号,使液晶显示装置呈现所需的亮度。
在伽马校正电路中通常包括将输入的数字信号转换为模拟信号的数字模拟转换器(DAC)。目前在市面上存在许多不同的数字模拟转换器,例如电阻串(R-String)数字模拟转换器。图1是一种现有的3位的电阻串数字模拟转换器。参照图1,3位的电阻串数字模拟转换器100包括一串电阻器110以及选择器120。选择器120包括选择线121及与选择线121交叉设置的控制线122,其中,每两条控制线122被数字信号的其中一位(bit)所控制,并且每两条控制线122之一连接至一非门123。每条选择线121上均包括开关元件124,其中,开关元件124设置在每条选择线121与每两条控制线122之一的交叉处。开关元件124可例如是NMOS晶体管。每一开关元件124被数字信号的其中一位(bit)所控制。
电阻串连接于一高参考电压(VH)与一低参考电压(VL)之间。每一选择线121连接于电阻串中的一节点。同一时间只有一条选择线121上的所有开关元件124被输入的数字信号打开,且将电阻串中相对应的一节点的电压耦接于输出节点(V0)。
电阻串数字模拟转换器100需要23=8条选择线121。而且,每一条选择线121需要3个开关元件124。因此,3位的电阻串数字模拟转换器100需要23×3=24个开关元件124。
由此可知,以N位电阻串数字模拟转换器为例,其需要2N条选择线。而且,每一条选择线需要N个开关元件。因此,N位的电阻串数字模拟转换器需要2N×N个开关元件。由此可以看出,当输入的数字信号的位数增加时,开关元件的数量也急速增加,从而导致布局面积扩大。这对于缩小芯片以及降低成本将是不利的。
发明内容
为了解决上述现有技术存在的问题,本发明的目的在于提供一种数字模拟转换器,用以根据N位的第一数字信号输出第一输出模拟电压或根据N位的第二数字信号输出第二输出模拟电压,其中,所述数字模拟转换器包括:第一电压产生器,耦接于第一参考电压与第二参考电压之间,用于产生介于第一参考电压与第二参考电压之间的2N个第一模拟电压;第一电压选择器,耦接于所述第一电压产生器,并根据所述N位的第一数字信号从第一电压产生器产生的2N个第一模拟电压中选择出所述第一输出模拟电压;第二电压产生器,耦接于第二参考电压与第三参考电压之间,用于产生介于第二参考电压与第三参考电压之间的2N个第二模拟电压;第二电压选择器,耦接于所述第二电压产生器,并按照所述N位的第二数字信号从第二电压产生器产生的2N个第二模拟电压中选择出所述第二输出模拟电压。
进一步地,所述数字模拟转换器还包括:第一电压跟随器,用于将第一电压选择器根据所述N位的第一数字信号选择出的所述第一输出模拟电压输出。
进一步地,所述第一电压产生器包括串联的2N-1个第一电阻器和至少一个第二电阻器。
进一步地,所述第一电压选择器包括2N条第一选择线,其中,每条第一选择线对应耦接于第一电压产生器,以提供与该条第一选择线对应的第一输出模拟电压,每条第一选择线包括串联的N个第一开关元件,其中,每个第一开关元件由所述N位的第一数字信号的其中一位来决定其导通或截止。
进一步地,所述数字模拟转换器还包括:第二电压跟随器,用于将第二电压选择器根据所述N位的第二数字信号选择出的所述第二输出模拟电压输出。
进一步地,所述第二电压产生器包括串联的2N-1个第三电阻器和至少一个第四电阻器。
进一步地,所述第二电压选择器包括2N条第二选择线,其中,每条第二选择线对应耦接于第二电压产生器,以提供与该条第二选择线对应的第二输出模拟电压,每条第二选择线包括串联的N个第二开关元件,其中,每个第二开关元件由所述N位的第二数字信号的其中一位来决定其导通或截止。
本发明的另一目的还在于提供一种可编程伽玛校正缓冲电路,包括:数字信号接收器,用于接收数字信号,并将接收到的数字信号提供给数字模拟转换器;上述的数字模拟转换器,用于将由数字信号接收器提供的数字信号转换为相应的模拟电压。
本发明的又一目的又在于提供一种显示装置,包括:上述的可编程伽玛校正缓冲电路,用于将输入的数字信号转换为相应的模拟电压;数据驱动器,用于根据所述可编程伽玛校正缓冲电路提供的模拟电压产生显示面板所需的驱动电压;扫描驱动器,用于顺序产生扫描信号;显示面板,响应于由数据驱动器提供的驱动电压及由扫描驱动器提供的扫描信号显示影像。
进一步地,所述显示面板为液晶显示面板或者有机发光二极管显示面板。
本发明的数字模拟转换器、可编程伽玛校正缓冲电路及显示装置,减少了开关元件的数量,从而使得布局面积减小,利于缩小芯片尺寸以及成本的降低。
附图说明
通过结合附图进行的以下描述,本发明的实施例的上述和其它方面、特点和优点将变得更加清楚,附图中:
图1是一种现有的电阻串数字模拟转换器。
图2是根据本发明的实施例的数字模拟转换器的电路结构图。
图3是根据本发明的实施例的可编程伽玛校正缓冲电路的模块示意图。
图4是根据本发明的实施例的显示装置的结构示意图。
具体实施方式
以下,将参照附图来详细描述本发明的实施例。然而,可以以许多不同的形式来实施本发明,并且本发明不应该被解释为限制于这里阐述的具体实施例。相反,提供这些实施例是为了解释本发明的原理及其实际应用,从而使本领域的其他技术人员能够理解本发明的各种实施例和适合于特定预期应用的各种修改。
图2是根据本发明的实施例的数字模拟转换器的电路结构图。
参照图2,根据本发明的实施例的数字模拟转换器(Digital-to-AnalogConverter,DAC)200可例如是一2位的数字模拟转换器,其可实现图1所示的3位的数字模拟转换器100的功能,并且所用开关元件数量大幅减少,从而使本发明的实施例的数字模拟转换器200布局面积减小,利于缩小其所占芯片尺寸以及成本的降低。
根据本发明的实施例的数字模拟转换器200可包括第一电压产生器210、第一电压选择器220、第二电压产生器230以及第二电压选择器240。
第一电压产生器210耦接于第一参考电压(例如,高参考电压)VH和第二参考电压(例如,半高参考电压)(VH-VL)/2之间,以输出介于第一参考电压VH和第二参考电压(VH-VL)/2之间的一组(即22个)第一模拟电压V0、V1、V2、V3。在本实施例中,第一电压产生器210包括串联耦接在一起的3(即22-1)个第一电阻器211和一个第二电阻器212,其中,第二电阻器212的电阻值为第一电阻器211的电阻值的一半。这组第一模拟电压V0、V1、V2、V3是该3个第一电阻器211和一个第二电阻器212之间的节点电压。这里,这组第一模拟电压V0、V1、V2、V3可指的是图1所示的3位的数字模拟转换器100产生的8个电压中的4个高电压。例如,图1所示的3位的数字模拟转换器100产生的8个电压从小到大依次为V0、V1、V2、V3、V4、V5、V6、V7,这组第一模拟电压V0、V1、V2、V3分别为图1所示的3位的数字模拟转换器100产生的4个高电压V4、V5、V6、V7。
第一电压选择器220耦接于第一电压产生器210,并依照输入的第一数字信号(例如2位的数字信号)从这组第一模拟电压V0、V1、V2、V3中选择出一第一输出模拟电压。在本实施例中,第一电压选择器220包括4(即,22)条第一选择线221及与每条第一选择线221交叉设置的4(即,22)条第一控制线222,其中,每两条第一控制线222被第一数字信号的其中一位(bit)所控制,并且每两条第一控制线222之一连接至一第一非门223。每条第一选择线221上均包括2(即,22-1)个第一开关元件224,其中,每一第一开关元件224设置在该条第一选择线221与每两条第一控制线222之一的交叉处。在本实施例中,第一开关元件224可例如是NMOS晶体管。每一第一开关元件224被第一数字信号的其中一位(bit)所控制。第一电压选择器220接收的输入的第一数字信号通过控制这些第一开关元件224的导通或截止状态选择相应的第一输出模拟电压。
每一第一选择线221连接于第一电压产生器210中的对应的一节点。同一时间只有一条第一选择线221上的所有第一开关元件224被输入的第一数字信号打开,且将第一电压产生器210中相对应的一节点的模拟电压输出。
例如,当第一电压选择器220接收的输入的第一数字信号的位数为00时,第一模拟电压V0(即图1所示的3位的数字模拟转换器100产生的高电压V4)为第一电压选择器220选择出的第一输出模拟电压。当第一电压选择器220接收的输入的第一数字信号的位数为01时,第一模拟电压V1(即图1所示的3位的数字模拟转换器100产生的高电压V5)为第一电压选择器220选择出的第一输出模拟电压。当第一电压选择器220接收的输入的第一数字信号的位数为10时,第一模拟电压V2(即图1所示的3位的数字模拟转换器100产生的高电压V6)为第一电压选择器220选择出的第一输出模拟电压。当第一电压选择器220接收的输入的第一数字信号的位数为11时,第一模拟电压V3(即图1所示的3位的数字模拟转换器100产生的高电压V7)为第一电压选择器220选择出的第一输出模拟电压。
此外,根据本发明的实施例的数字模拟转换器200还可包括第一电压跟随器250,用于将第一电压选择器220按照输入的第一数字信号选择出的相应的第一输出模拟电压输出。其中,第一电压跟随器250可例如是运算放大器,但本发明并不限制于此。
第二电压产生器230耦接于第二参考电压(例如,半高参考电压)VH/2和第三参考电压(例如,低参考电压)VL之间,以输出介于第二参考电压VH/2和第三参考电压VL之间的一组(即22个)第二模拟电压V0’、V1’、V2’、V3’。在本实施例中,第二电压产生器230包括串联耦接在一起的一个第四电阻器232和3(即22-1)个第三电阻器231,其中,第三电阻器231的电阻值为第四电阻器232的电阻值的一半,第四电阻器232的电阻值与第一电阻器211的电阻值相等。这组第二模拟电压V0’、V1’、V2’、V3’是该一个第四电阻器232和3个第三电阻器231之间的节点电压。这里,这组第二模拟电压V0’、V1’、V2’、V3’可指的是图1所示的3位的数字模拟转换器100产生的8个电压中的4个低电压。例如,图1所示的3位的数字模拟转换器100产生的8个电压从小到大依次为V0、V1、V2、V3、V4、V5、V6、V7,这组第二模拟电压V0’、V1’、V2’、V3’分别为图1所示的3位的数字模拟转换器100产生的4个低电压V0、V1、V2、V3。
第二电压选择器240耦接于第二电压产生器230,并依照输入的第二数字信号(例如,2位的第二数字信号)从这组第二模拟电压V0’、V1’、V2’、V3’中选择出一第二输出模拟电压。在本实施例中,第二电压选择器240包括4(即22)条第二选择线241及与每条第二选择线241交叉设置的4(即22)条第二控制线242,其中,每两条第二控制线242被第二数字信号的其中一位(bit)所控制,并且每两条第二控制线242之一连接至一第二非门243。每条第二选择线241上均包括2(即22-1)个第二开关元件244,其中,每一第二开关元件244设置在每条第二选择线241与每两条第二控制线242之一的交叉处。第二开关元件244可例如是NMOS晶体管。每一第二开关元件244被第二数字信号的其中一位(bit)所控制。第二电压选择器240接收的输入的第二数字信号通过控制这些第二开关元件244的导通或截止状态选择相应的第二输出模拟电压。
每一第二选择线241连接于第二电压产生器230中的对应的一节点。同一时间只有一条第二选择线241上的所有第二开关元件244被输入的第二数字信号导通,且将第二电压产生器230中相对应的一节点的第二输出模拟电压输出。
例如,当第二电压选择器240接收的输入的第二数字信号的位数为00时,第二模拟电压V0’(即图1所示的3位的数字模拟转换器100产生的低电压V0)为第二电压选择器240选择出的第二输出模拟电压。当第二电压选择器240接收的输入的第二数字信号的位数为01时,第二模拟电压V1’(即图1所示的3位的数字模拟转换器100产生的低电压V1)为第二电压选择器240选择出的第二输出模拟电压。当第二电压选择器240接收的输入的第二数字信号的位数为10时,第二模拟电压V2’(即图1所示的3位的数字模拟转换器100产生的低电压V2)为第二电压选择器240选择出的第二输出模拟电压。当第一电压选择器220接收的输入的第二数字信号的位数为11时,第二模拟电压电平V3’(即图1所示的3位的数字模拟转换器100产生的低电压V3)为第二电压选择器240选择出的第二输出模拟电压。
此外,根据本发明的实施例的数字模拟转换器200还可包括第二电压跟随器260,用于将第二电压选择器240按照输入的第二数字信号提供的相应的第二输出模拟电压输出。其中,第二电压跟随器260可例如是运算放大器,但本发明并不限制于此。
此外,在本实施例中,上述的第一数字信号和第二数字信号可根据实际情况同时被输入,也可根据实际情况分时被输入,本发明并不做具体限定。
由上可以得知,本发明的实施例的2位的数字模拟转换器200需要8条选择线,其能够输出8(即23)个模拟电压,从而实现图1所示的3位的数字模拟转换器100的功能。而且,每一条选择线需要2个开关元件。因此,本发明的实施例的2位的数字模拟转换器200需要16(2×8)个开关元件。而图1所示的3位的数字模拟转换器100则需要24(3×8)各开关元件。因此,本发明的实施例的2位的数字模拟转换器200减少了开关元件的数量,从而使得其布局面积减小,利于缩小其所占芯片尺寸以及成本的降低。
此外,虽然上述的本发明的实施例的数字模拟转换器200以2位的数字模拟转换器为例,但本发明并不局限于此。本发明的数字模拟转换器可为N位的数字模拟转换器,例如,N位的数字模拟转换器需要2N+1条选择线,其能够输出2N+1个输出模拟电压,从而实现N+1位的数字模拟转换器的功能。而且,每一条选择线需要N个开关元件。因此,N位的数字模拟转换器需要N×2N+1个开关元件,而N+1位的数字模拟转换器需要(N+1)×2N+1个开关元件,其中,N为正整数。由此可知,N位的数字模拟转换器需要的开关元件的数量远少于N+1位的数字模拟转换器需要的开关元件的数量。
图3是根据本发明的实施例的可编程伽玛校正缓冲电路的模块示意图。
参照图3,根据本发明的实施例的可编程伽玛校正缓冲电路(P-GammaCircuit)包括数字信号接收器100和图2所示的数字模拟转换器200。
数字信号接收器100接收数字信号(其可由IC芯片内部设定),并将接收到的数字信号提供给数字模拟转换器200。数字模拟转换器200接收由数字信号接收器100提供的数字信号,并将接收到的数字信号转换为相应的模拟电压(或称伽马校正电压)。
图4是根据本发明的实施例的显示装置的结构示意图。
参照图4,根据本发明的实施例的显示装置包括:可编程伽玛校正缓冲电路1、数据驱动器2、扫描驱动器3及显示面板4。
可编程伽玛校正缓冲电路1为图3所示的可编程伽玛校正缓冲电路,其将输入的数字信号转换为相应的模拟电压(或称伽马校正电压)。数据驱动器2用于根据可编程伽玛校正缓冲电路1提供的模拟电压产生显示面板4所需的驱动电压。扫描驱动器3用于顺序产生扫描信号。显示面板4响应于由数据驱动器2提供的驱动电压及由扫描驱动器3提供的扫描信号显示影像。其中,显示面板4可为液晶显示面板或者有机发光二极管(OLED)显示面板。
虽然已经参照特定实施例示出并描述了本发明,但是本领域的技术人员将理解:在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下,可在此进行形式和细节上的各种变化。
Claims (10)
1.一种数字模拟转换器,用以根据N位的第一数字信号输出第一输出模拟电压或根据N位的第二数字信号输出第二输出模拟电压,其特征在于,所述数字模拟转换器包括:
第一电压产生器(210),耦接于第一参考电压与第二参考电压之间,用于产生介于第一参考电压与第二参考电压之间的2N个第一模拟电压;
第一电压选择器(220),耦接于所述第一电压产生器(210),并根据所述N位的第一数字信号从第一电压产生器(210)产生的2N个第一模拟电压中选择出所述第一输出模拟电压;
第二电压产生器(230),耦接于第二参考电压与第三参考电压之间,用于产生介于第二参考电压与第三参考电压之间的2N个第二模拟电压;
第二电压选择器(240),耦接于所述第二电压产生器(230),并根据所述N位的第二数字信号从第二电压产生器(230)产生的2N个第二模拟电压中选择出所述第二输出模拟电压。
2.根据权利要求1所述的数字模拟转换器,其特征在于,所述数字模拟转换器还包括:
第一电压跟随器(250),用于将第一电压选择器(220)根据所述N位的第一数字信号选择出的所述第一输出模拟电压输出。
3.根据权利要求1或2所述的数字模拟转换器,其特征在于,所述第一电压产生器(210)包括串联的2N-1个第一电阻器(211)和至少一个第二电阻器(212)。
4.根据权利要求1或2所述的数字模拟转换器,其特征在于,所述第一电压选择器(220)包括2N条第一选择线(221),其中,每条第一选择线(221)对应耦接于第一电压产生器(210),以提供与该条第一选择线(221)对应的第一输出模拟电压,每条第一选择线(221)包括串联的N个第一开关元件(224),其中,每个第一开关元件(224)由所述N位的第一数字信号的其中一位来决定其导通或截止。
5.根据权利要求1所述的数字模拟转换器,其特征在于,所述数字模拟转换器还包括:
第二电压跟随器(260),用于将第二电压选择器(240)根据所述N位的第二数字信号选择出的所述第二输出模拟电压输出。
6.根据权利要求1或5所述的数字模拟转换器,其特征在于,所述第二电压产生器(230)包括串联的2N-1个第三电阻器(231)和至少一个第四电阻器(232)。
7.根据权利要求1或5所述的数字模拟转换器,其特征在于,所述第二电压选择器(240)包括2N条第二选择线(241),其中,每条第二选择线(241)对应耦接于第二电压产生器(230),以提供与该条第二选择线(241)对应的第二输出模拟电压,每条第二选择线(241)包括串联的N个第二开关元件(244),其中,每个第二开关元件(244)由所述N位的第二数字信号的其中一位来决定其导通或截止。
8.一种可编程伽玛校正缓冲电路,包括:
数字信号接收器(100),用于接收数字信号,并将接收到的数字信号提供给数字模拟转换器(200);
权利要求1至7任一项所述的数字模拟转换器(200),用于将由数字信号接收器(100)提供的数字信号转换为相应的输出模拟电压。
9.一种显示装置,包括:
权利要求8所述的可编程伽玛校正缓冲电路,用于将输入的数字信号转换为相应的输出模拟电压;
数据驱动器(2),用于根据所述可编程伽玛校正缓冲电路提供的输出模拟电压产生显示面板(4)所需的驱动电压;
扫描驱动器(3),用于顺序产生扫描信号;
显示面板(4),响应于由数据驱动器(2)提供的驱动电压及由扫描驱动器(3)提供的扫描信号显示影像。
10.根据权利要求9所述的显示装置,其特征在于,所述显示面板(4)为液晶显示面板或者有机发光二极管显示面板。
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CN104143985B (zh) | 2017-06-23 |
US20160253939A1 (en) | 2016-09-01 |
US9633591B2 (en) | 2017-04-25 |
WO2016011678A1 (zh) | 2016-01-28 |
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