WO2016169383A1 - 低压数字模拟信号转换电路、数据驱动电路和显示系统 - Google Patents

低压数字模拟信号转换电路、数据驱动电路和显示系统 Download PDF

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Publication number
WO2016169383A1
WO2016169383A1 PCT/CN2016/077262 CN2016077262W WO2016169383A1 WO 2016169383 A1 WO2016169383 A1 WO 2016169383A1 CN 2016077262 W CN2016077262 W CN 2016077262W WO 2016169383 A1 WO2016169383 A1 WO 2016169383A1
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voltage
output
signal
module
analog
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PCT/CN2016/077262
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English (en)
French (fr)
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张盛东
冷传利
林兴武
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北京大学深圳研究生院
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Priority to US15/568,975 priority Critical patent/US10665145B2/en
Publication of WO2016169383A1 publication Critical patent/WO2016169383A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/68—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
    • H03M1/682—Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits both converters being of the unary decoded type
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0083—Converters characterised by their input or output configuration
    • H02M1/0093—Converters characterised by their input or output configuration wherein the output is created by adding a regulated voltage to or subtracting it from an unregulated input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/76—Simultaneous conversion using switching tree
    • H03M1/765—Simultaneous conversion using switching tree using a single level of switches which are controlled by unary decoded digital signals

Definitions

  • the present application relates to the field of display device technologies, and in particular, to a digital-to-analog converter, a data driving circuit, and a display system that realize display at low cost.
  • the display system is a medium for information transmission and is closely related to people's lives.
  • the mainstream display system is a liquid crystal display system (LCD), and an active matrix organic light emitting diode display system (AMOLED) has also begun to emerge in a small size field.
  • LCD liquid crystal display system
  • AMOLED active matrix organic light emitting diode display system
  • it is necessary to convert a digital signal representing image information into an analog signal to be displayed on the panel. This requires a digital-to-analog converter (DAC).
  • DAC digital-to-analog converter
  • the design of the DAC is the core module in the column driver chip. In the display system, as shown in FIG.
  • the DAC generally generates voltage values required for each level of gray in the form of a resistor string, and the digital signal of the input DAC is selected by the transfer transistor array PTL to correspond to the voltage value of the gray scale. If the gray level of the display system is 256, then 256 resistors are needed to generate 256 different voltages.
  • LCD and OLED display systems are used to drive the analog signal of the display screen to medium and high voltage signals, and the high voltage analog signal is selected from the voltage division of the resistor string in the DAC, which causes the resistor string to be applied with medium and high voltage.
  • the related devices such as the transfer transistor array PTL in the DAC should be medium and high voltage devices, while the medium and high voltage devices require more power consumption and occupy a larger chip area.
  • the present application provides a low voltage digital analog signal conversion circuit comprising:
  • At least one voltage dividing unit (10), the voltage dividing unit (10) includes: a plurality of resistors connected in series between the low-limit voltage and the high-limit voltage, and the voltage-divided output from the series node of the resistor and the high-voltage connection terminal end;
  • the selecting unit (11) is respectively connected to the voltage dividing output end of each voltage dividing unit (10), the selecting unit (11) is for inputting a digital signal, and selecting one of the divided voltage output terminals according to the control of the digital signal And outputting the voltage signal to be compensated on the voltage dividing output terminal;
  • a voltage compensation unit (12) connected to the selection unit (11) for respectively inputting the voltage signal to be compensated and the digital signal output by the selection unit, and compensating the voltage signal to be compensated according to the digital signal, so that the compensated voltage is a digital signal The corresponding analog voltage.
  • the present application provides a data driving circuit, including:
  • a data input module for inputting a digital signal containing image data
  • a latch connected to the data input module for digital signal locking
  • the input end of the selection unit (11) and the voltage compensation unit (12) is connected to the output end of the latch.
  • the present application provides a display system including the above data driving circuit.
  • the voltage dividing unit comprises: a plurality of resistors connected in series between the low voltage limit and the high limit voltage, a voltage dividing output terminal drawn from the series node of the resistor and the high voltage limit terminal;
  • the analog signal conversion circuit, the data driving circuit, and the display system are low-voltage devices, which not only have low power consumption, but also occupy a small chip area.
  • 1 is a schematic structural view of a conventional resistor string and a transmission transistor array
  • FIG. 2 is a Gamma curve diagram of a conventional digital-to-analog converter participating in a display process
  • FIG. 3 is a schematic structural diagram of a conventional digital-to-analog converter using a resistor string
  • FIG. 5 is a schematic structural diagram of a low voltage digital analog signal conversion circuit according to an implementation of the present application.
  • FIG. 6 is a schematic structural diagram of an analog adding module including an input capacitor according to an embodiment of the present application.
  • FIG. 7 is another schematic structural diagram of an analog adding module including an input capacitor according to an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of an analog adding module including an input resistor according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of an analog adding module including a voltage-to-current module and a current-to-voltage mode according to an embodiment of the present application;
  • FIG. 2 is a Gamma curve of an N-bit digital-to-analog converter, where N is a positive integer.
  • N is a positive integer.
  • the digital input signal changes from 20 to N 2
  • the voltage range for the DAC output signal V outLow to V outHigh the voltage range for the DAC output signal V outLow to V outHigh.
  • the size of V outLow and V outHigh is determined by the brightness range of the LCD or OLED panel, the pixel circuit, the characteristics of the liquid crystal molecules, and the like.
  • FIG. 3 is a block diagram of a group of column driving circuits.
  • the column driver circuit includes a data input module (typically a shift register module), a latch module, a digital to analog conversion module, and an output buffer.
  • the digital to analog conversion module includes a resistor string and a transfer transistor array PTL. Both the latch module and the digital-to-analog conversion module are N bits. Therefore, in the digital-to-analog conversion module, there are 2 N different voltage values between the V outLow and V outHigh ranges, which are generated by the resistor division in the resistor string. The 2 N different voltage values generated by the resistor string can be shared in the chip of the column driver circuit.
  • Each of the digital-to-analog converters selects one of 2 N different voltage values as the output of the digital-to-analog converter through the transfer transistor array PTL therein.
  • the N-bit digital signal representing the image data is output through the input module and the latch module. This output serves as the input of the transfer transistor array PTL of the digital-to-analog converter, and the N-bit digital signal determines the size of the output signal, thereby realizing digital simulation. Conversion.
  • the analog signal output by the digital-to-analog converter is then sent to the panel through the output buffer to achieve image display.
  • the present application discloses a low-voltage digital-to-analog signal conversion circuit, a data driving circuit, and a display system.
  • the inventive idea is to divide the resistor string into a plurality of segmented resistor strings, that is, a voltage dividing unit, and one end of each voltage dividing unit is connected.
  • the low voltage that is, the low voltage, is usually 0 voltage, thereby reducing the voltage value of each output node of each voltage dividing unit.
  • the low-voltage digital signal-to-analog signal circuit (hereinafter referred to as a low-voltage digital-to-analog conversion circuit) disclosed in the present application inputs an N-bit digital signal, and correspondingly, an output signal having an output voltage ranging from V outLow to V outHigh , wherein V outHigh >V outLow , N is a positive integer, as shown in Figure 4 is the Gamma graph of the low-voltage digital-to-analog conversion circuit.
  • the abscissa is the input N-bit digital signal, and the ordinate is the corresponding output voltage range is V. Analog signal from outLow to V outHigh .
  • the low voltage digital-to-analog conversion circuit of the present application includes:
  • the voltage dividing unit 10 includes a plurality of resistors connected in series between the low voltage limit and the high limit voltage, and a voltage dividing output terminal drawn from the series node of the resistor and the high voltage limit terminal. It should be noted that some high voltage limits of the voltage dividing unit 10 do not have corresponding digital signals. In this case, it is not necessary to draw a voltage dividing output terminal from the high voltage end of the voltage dividing unit 10, but directly from this point.
  • the series node of the resistance of the voltage unit 10 can lead to a plurality of voltage dividing outputs.
  • the selecting unit 11 is respectively connected to the voltage dividing output end of each voltage dividing unit 10, and the selecting unit 11 is configured to input a digital signal, select one of the divided voltage output terminals according to the control of the digital signal, and output the voltage dividing output end.
  • the voltage signal to be compensated on the selection unit 11 may include a transmission transistor array, and the switching circuit formed by the transmission transistor array has a one-to-one correspondence with the voltage dividing output terminals of the voltage dividing units 10, and the voltage dividing output terminals and the output of the selecting unit 11 respectively End connected.
  • each voltage dividing unit 10 In order to further reduce the voltage applied to each voltage dividing unit 10, the low-voltage voltage of each voltage dividing unit 10 can be made zero when designing the low-voltage digital-to-analog conversion circuit, and in order to achieve better effects, design points are obtained. When the unit 10 is pressed, each can be made The high limit voltage of the voltage dividing unit 10 is as close as possible or even equal.
  • the voltage compensation unit 12 is connected to the selection unit 11 for inputting the voltage signal to be compensated and the digital signal output by the selection unit 11, respectively, and compensating the voltage signal to be compensated according to the digital signal, so that the compensated voltage is corresponding to the digital signal. Analog voltage.
  • the voltage compensation unit 12 determines the compensation value of the voltage signal to be compensated according to the division rule of the digital signal and the voltage dividing unit 10, and adds the voltage to be compensated and the compensation value to output.
  • the voltage compensation unit 12 has various implementation manners, and the following examples are illustrated:
  • the voltage compensation unit 12 includes a compensation voltage selection module 13 and an analog addition module 14.
  • the compensation voltage selection module 13 is configured to output a compensation signal according to a division rule of the digital signal and the voltage dividing unit 10, the compensation signal is used to compensate the voltage signal to be compensated; the compensation voltage selection module 13 may include a compensation voltage terminal and a switch module.
  • the number of the compensation voltage terminals is the same as the number of the voltage dividing units 10, and the voltage value of the compensation voltage terminal is equal to the voltage value to be compensated for the voltage signal to be compensated at the voltage dividing output end of each voltage dividing unit 10;
  • one switch module is only connected to one compensation voltage terminal, one end of the switch module is connected to the compensation voltage terminal, the other end is connected to one input end of the analog addition module 14, and the control terminal of the switch module is used for inputting the number.
  • the signal is turned on and off under the control of the digital signal to output a compensation signal.
  • the analog adding module 14 has an input terminal connected to the output end of the selecting unit 11 and another input terminal connected to the output end of the compensating voltage selecting module 13 for outputting the to-be-compensated voltage signal and the compensating voltage selecting module 13 outputted by the selecting unit 11.
  • the voltage of the output compensation signal is added and output; the signal output by the analog addition module 14 is the output signal of the voltage compensation unit 12.
  • the analog addition module 14 has a variety of configurations, and several of them are described below.
  • the analog addition module 14 includes an amplifier and a number of input capacitors.
  • the analog addition module 14 includes capacitors C1, C2, and C3, and an amplifier, where V 100 and V 200 are the two inputs of the analog addition module 14, and V out is the output of the analog addition module 14. .
  • the connection method is:
  • the working process of the analog addition module 14 is divided into two phases.
  • the switches S 11 , S 12 , and S 13 are turned on, and the switches S 21 and S 22 are turned off.
  • V 100 and V 200 are respectively coupled to the first ends of the capacitors C1 and C2, and the negative input terminals of the amplifiers are The output is shorted, and the charge at the negative input can be expressed as:
  • the switches S 21 , S 22 are turned on, and the switches S 11 , S 12 , S 13 are turned off, and the first ends of the capacitors C1 and C2 are respectively coupled to the ground.
  • the negative input of the amplifier is in a floating state, and its charge remains unchanged, which can be expressed as:
  • V out V X + (V 100 * C1 + V 200 * C2) / C3.
  • V out V ref + V 100 + V 200 .
  • V ref 0
  • V out V 100 + V 200 is obtained , that is, the function of voltage addition is realized.
  • the analog adding module 14 may further include a capacitor C3, but includes capacitors C1 and C2, and an amplifier, wherein V 100 and V 200 are two input terminals of the analog adding module 14, and V out is The output of the analog addition module 14 is simulated.
  • the connection method is:
  • Amplifier positive input is grounded, a switch S 11 indirectly negative input terminal and the output terminal; said negative input terminal of the amplifier is also connected to one end of a capacitor C2, the other end of the capacitor C2 is connected via a switch S 21 to the output of the amplifier; capacitor C2 is connected one end of the switch S 21 is further connected to one end of a switch S 13, the other terminal of the switch S 13 a is the analog input of adder module 14; the negative input of the amplifier through a capacitor C1 is connected to a grounding switch S 22, one end of the capacitor C1 and the ground switch S 22 is connected to the other is also connected to one end of the switch 12 is S, 12 is the other end of the switch S to the analog adder 14 of the other module An input.
  • the switches S 11 , S 12 , and S 13 are turned on, and the switches S 21 and S 22 are turned off.
  • V 100 and V 200 are respectively coupled to the first ends of the capacitors C1 and C2, and the negative input terminals of the amplifiers are The output is shorted, and the charge at the negative input can be expressed as:
  • V out V 200 + (V 100 * C1) / C2.
  • V out V 100 + V 200 , that is, the function of voltage addition is realized.
  • the switches S 11 , S 12 , S 13 , S 21 , S 22 in Figs. 6 and 7 refer to devices having a switching function.
  • the analog addition module 14 includes an amplifier and a number of input resistors.
  • the analog addition module 14 includes four resistors and an amplifier, wherein V 100 and V 200 are the two inputs of the analog addition module 14, and V out is the output of the analog addition module 14.
  • the connection method is:
  • a resistor R1 is connected between the negative input terminal and the output terminal of the amplifier; a grounding resistor R2 is further connected to the negative input end of the amplifier; a positive input end of the amplifier is connected to one end of a resistor R3, and the other end of the resistor R3 is An input terminal of the analog adding module 14; a positive input end of the amplifier is connected to one end of a resistor R4, and the other end of the resistor R4 is another input end of the analog adding module 14, wherein the resistors R2, R3 and The resistance of R4 is equal, both are R; the resistance of resistor R1 is twice that of resistor R2, which is 2*R.
  • V X (V 100 + V 200 )/2.
  • the analog addition module 14 includes a voltage to current module and a current to voltage module.
  • the analog addition module 14 includes:
  • the input terminal of the voltage-to-current module is an input end of the analog adding module 14 for converting the voltage signal to be compensated outputted by the selecting unit 11 into a current signal output; if the voltage signal output by the unit 11 is selected For V 100 , after inputting this voltage to current module, its output current is V 100 *g m , where g m is the transconductance of the above voltage to current module.
  • the input end of the other voltage-to-current module is another input end of the analog adding module 14 for converting the compensation signal outputted by the compensation voltage selection module 13 into a current signal output; if the voltage signal output by the compensation voltage selection module 13 is V 200. After inputting this voltage to current module, its output current is V 200 *g m .
  • An adding node is configured to add and output the current signals output by the two voltage-to-current modules, that is, add V 100 *g m and V 200 *g m , and output values are (V 100 +V 200 )* The current signal of g m .
  • a current-to-voltage module the output end of which is an output end of the analog adding module 14 for converting the current signal outputted by the adding node into a voltage signal for output, that is, the input value is (V 100 +V 200 )*g m
  • the current signal is converted to V 100 +V 200 , thereby achieving the function of voltage addition. Since the sum of the currents is easier to implement, as long as the current to be added flows through the same node, it can be realized. Therefore, the voltage-to-current method is used to convert the voltage addition problem into a current addition, which makes the scheme more practical. easily.
  • the present application further provides a data driving circuit, which may include:
  • a data input module for inputting a digital signal containing image data
  • a latch connected to the data input module for digital signal locking
  • the input terminal of the selection unit 11 and the voltage compensation unit 12 is connected to the output terminal of the latch.
  • the present application also proposes a display system including the above Data drive circuit.
  • the present embodiment further clarifies the above-mentioned low-voltage digital-to-analog conversion circuit, in particular, the low-limit voltage, the high-limit voltage, and the voltage value of the compensation signal output by the voltage compensating unit 12 connected to each voltage dividing unit 10.
  • the low-voltage digital-to-analog conversion circuit of the present application inputs a digital signal of N bits, and correspondingly, an analog signal whose output voltage ranges from V outLow to V outHigh .
  • the low voltage digital-to-analog conversion circuit of the present application includes:
  • k voltage dividing unit 10 wherein an i-th dividing means, one end of a low voltage V L (i.e., low threshold voltage), the other end a voltage value V i of the terminal voltage (i.e., a high threshold voltage), for outputting A signal having a voltage range of V L to V i ; wherein k is a positive integer greater than 1, and i ranges from a positive integer less than or equal to k.
  • the first voltage dividing unit 10 is connected to a low voltage V L at one end and a voltage terminal of V 1 at the other end for outputting a signal having a voltage range of V L to V 1 ;
  • the voltage unit 10 is connected to a low voltage V L at one end and a voltage terminal of V 2 at the other end for outputting a signal having a voltage range of V L to V 2 , and so on, the kth voltage dividing unit 10, One end is connected to a low voltage V L , and the other end is connected to a voltage terminal having a voltage value of V k for outputting a signal having a voltage range of V L to V k .
  • the voltage dividing unit 10 of FIG. 5 includes two resistors connected in series, which is for illustration only, and does not mean that each voltage dividing unit 10 includes two resistors.
  • the selecting unit 11 is configured to select a signal of a certain voltage value of a certain voltage dividing unit according to the input N-bit digital signal for output; in other words, the input end of the selecting unit 11 receives the N-bit digital signal, and according to the digital signal Selecting a certain value of the output voltage range of one of the k voltage dividing units 10 to output a voltage signal, for example, selecting a second voltage dividing unit 10 output voltage range V L ⁇ V according to the digital signal. A value of 2 is used to output a voltage signal.
  • the voltage compensating unit 12 is configured to output the signal of the transmission transistor array 11 with a value of V ci voltage compensation when the selection unit 11 selects a signal of a certain voltage value of the i-th voltage dividing unit for output, because One end of the voltage dividing unit 10 is connected to a low level V L , and the portion where the voltage is pulled down is added back.
  • the signal outputted by the voltage compensating unit 12 is an output signal of the low-voltage digital-to-analog conversion circuit, and the output analog signal is sent to the panel through the output buffer to realize image display.
  • the voltage compensating unit 12 When selecting 11 to select a signal of a certain voltage value of the first voltage dividing unit for output, the voltage compensating unit 12 outputs a voltage compensation value of V c1 to the output signal of the selecting unit 11; when the selecting unit 11 selects the second When a signal of a certain voltage value of the voltage dividing unit is output, the voltage compensating unit 12 outputs a voltage compensation value of V c2 to the output signal of the selecting unit 11, and so on, when the selecting unit 11 selects the kth branch. When a signal of a certain voltage value of the pressure unit is output, the voltage compensation unit 12 outputs a voltage compensation value of V ck to the output signal of the selection unit 11.
  • the value of the output signal of the selection unit 11 is V ci voltage compensation, which means that if the voltage value of the output signal of the selection unit 11 is V out , the value is V ci voltage compensation, and the final output is The voltage value of the signal is V out +V ci .
  • the voltage compensation unit 12 includes a compensation voltage selection module 13 and an analog addition module 14. The details are described below.
  • the compensation voltage selection module 13 is configured to output a compensation signal having a voltage value of V ci when the selection unit 11 selects a signal of a certain voltage value of the i-th voltage dividing unit 10 for output. For example, when the selection unit 11 selects a signal of a certain voltage value of the first voltage dividing unit 10 for output, the compensation voltage selection module 13 outputs a compensation signal having a voltage value of V c1 .
  • the compensation voltage selection module 13 may include k compensation voltage terminals and k switch modules.
  • the value of the i-th compensation voltage terminal is V ci
  • the value of i is a positive integer less than or equal to k, that is, the value of the first compensation voltage terminal is V c1
  • the second compensation voltage terminal is The value is V c2 , and so on, and the value of the kth compensation voltage terminal is V ck .
  • the k switch modules wherein one end of the i-th switch module is connected to the i-th compensation voltage terminal, and the other end is used as an output end of the compensation voltage selection module 14 for selecting the i-th voltage dividing unit 10 when the selecting unit 11 selects When a signal of a certain voltage value at the voltage dividing output is output, a signal is output to output a voltage value of V ci .
  • one end of the first switching module is connected to the first compensation voltage terminal, and the other end is used as an output terminal of the compensation voltage selection module 14.
  • the selection unit 11 selects a signal of a certain voltage value of the first voltage dividing unit 10.
  • the first switching module is turned on to output a signal of the first compensation voltage terminal voltage value V c1 to the analog adding module 14.
  • the k switch modules can be turned on and off according to the digital signal and the division rule of the voltage dividing unit 10. There are various implementation manners, for example, using a controller that receives the i-th branch.
  • a signal is sent to control the conduction of the i-th switching module, and the remaining switching modules are disconnected, where the value of i is The range, as described above, is a positive integer less than or equal to k, that is, when the controller receives the digital signal in the interval of the digital signal corresponding to the Gamma curve in the interval of the module signal output by the first voltage dividing unit 10 , a signal is sent to control the first switch module to be turned on, and the remaining switch modules are turned off; the controller receives the interval of the digital signal corresponding to the block signal output from the second voltage dividing unit 10 on the Gamma curve.
  • a signal is sent to control the second switch module to be turned on, the other switch modules are turned off, and so on, and will not be described again.
  • V L , V i and V ci are configured as:
  • V L is configured to be a low level, and preferably, V L can be zero.
  • V outLow ⁇ V outHigh taken not equal to V outLow k-1 distinct voltage values V outHigh, which is the voltage value of the k-1 are arranged in ascending voltage value of the i-th
  • V 1 V out1 -V out0 +V L
  • V c1 V out0 -V L ;
  • V 2 V out2 -V out1 +V L
  • V c2 V out1 -V L ;
  • V k V outk -V outk-1 +V L
  • V ck V outk-1 -V L .
  • V outLow ⁇ V outHigh taken not equal to V outLow
  • k-1 distinct voltage values V outHigh allowing this value representative of the k-1 points average V outLow ⁇ V outHigh, That is, V outLow (V out0 ), V out1 , V out2 , ..., V outi , ..., V outk-1 , V outHigh (V outk ) are one-difference series.
  • the ordinates V outLow to V outHigh are divided into k sections, and accordingly, the abscissa is also divided into k sections, 0 ⁇
  • the digital signal in the 1 interval corresponds to the analog signal of V out0 to V out1
  • the digital signal in the 1 to 2 interval corresponds to the analog signal of V out1 to V out2 , and so on.
  • a resistor string similar to that of FIG. 3 can be divided into a plurality of voltage dividing units 10 that meet the requirements as required.
  • FIG. 9 is the Gamma graph of the low-voltage digital-to-analog conversion circuit as in FIG. 4 .
  • k is 4 in FIG. 4, it is as shown in FIG.
  • the Gamma curve is segmented into four parts, the ordinate is from large to small, and the voltage values are V out4 (V outHigh ), V out3 , V out2 , V out1 , V out0 (V outLow ), respectively.
  • the abscissa is also divided into four parts, 0 to 1 interval, 1 to 2 interval, 2 to 3 interval, and 3 to 2 N interval.
  • the digital signal corresponding to the 0 ⁇ 1 interval corresponds to the output voltage range of V out0 to V out1 , and the voltage difference is V out1 -V out0 ;
  • the digital signal corresponding to the output range of 1 to 2 is V out1 ⁇ V out2 , the voltage difference
  • the value is V out2 -V out1 ;
  • the digital signal corresponding to the output range of 2 to 3 is V out3 ⁇ V out2 , the voltage difference is V out3 -V out2 ;
  • the digital signal of 3 ⁇ 2 N interval corresponds to the output voltage range It is V out4 ⁇ V out3 and the voltage difference is V out4 -V out3 .
  • Figure 10 illustrates one implementation of the segmentation shown in Figure 9.
  • the selection unit 11 may be a transfer transistor array whose structure remains unchanged, i.e., still similar to the transfer transistor array PTL of FIG. Different from FIG. 3, FIG. 10 no longer has a resistor string with V outLow and V outHigh at both ends, but divides the resistor string in FIG. 3 into four segments, that is, divided into four voltage dividing units 10, first.
  • the voltage range of the voltage dividing unit 10 is 0 to V out1 -V out0 , that is, one end thereof is grounded, and the other end is connected to a voltage terminal of V out1 -V out0 ;
  • the voltage range of the second voltage dividing unit 10 is 0 to V Out2 -V out1 , that is, one end is grounded and the other end is connected to a voltage terminal of V out2 -V out1 ;
  • the third voltage dividing unit 10 has a voltage range of 0 to V out3 -V out2 , that is, one end is grounded and the other end is The voltage is in the range of V out3 - V out2;
  • the voltage of the fourth voltage dividing unit 10 is 0 - V out4 - V out3 , that is, one end is grounded and the other end is connected to a voltage terminal of V out4 - V out3 .
  • the starting voltage of the output of each voltage dividing unit is reduced to zero, which can effectively reduce the voltage value of each voltage dividing unit. Therefore, although the overall structure of the circuit of the selection unit 11 is unchanged, similar to the transfer transistor array PTL in FIG. 3, since the resistance string is segmented, the output voltage of each voltage dividing unit is lowered to a low voltage range, Therefore, when the relevant device in the cell 11 is selected, such as when it is a transfer transistor array, the transistor can also be implemented by a low voltage process, so that the selection unit 11 becomes a low voltage device, which has the characteristics of low power consumption and small footprint.
  • the data input module inputs an N-bit digital signal through the N-bit latch module, and the selection unit 11 selectively outputs an analog signal having a corresponding voltage value based on the input N-bit digital signal.
  • This voltage value is not the original display voltage, but is a voltage value that is pulled down to the low voltage region because the resistor string is segmented. In order to make the final display signal the original display voltage, the voltage value needs to be pulled at this time. The low part is pulled back again. This pullback of the voltage value back to the original display voltage value can be achieved by the compensation voltage selection module 13 and the analog addition module 14.
  • the analog addition module 14 has at least two input terminals, one of which is connected to the output of the selection unit 11, and the other input is connected to the compensation voltage selection module 13, and the compensation voltage selection module 13 is output due to the Gamma curve or the resistance. Voltage loss caused by string segmentation. Since the Gamma curve is divided into four segments, there are four voltage values to choose from, which are controlled by switches S 1 , S 2 , S 3 , and S 4 respectively . When the input digital signal is in the range of 0 to 1, S 1 is turned on. The remaining switches are open; when the input digital signal is in the 1 to 2 interval, S 2 is turned on, the remaining switches are turned off, and so on. Thus, the analog adder module 14 is again recovered by the low voltage signal.
  • the switches S 1 , S 2 , S 3 , and S 4 refer to devices having a switching function.
  • the switches S 1 , S 2 , S 3 , and S 4 are turned on and off according to the division rules of the digital signal and the voltage dividing unit 10, and may be implemented in various manners, for example, by using a controller.
  • the control S 1 When receiving the digital signal in the interval of 0 to 1, the control S 1 is turned on, and the other switches are turned off; when the digital signal in the interval 1 to 2 is received, the control S 2 is turned on, and the remaining switches are turned off; When the digital signal in the interval 2 to 3 is received, the control S 3 is turned on, and the remaining switches are turned off; when the digital signal in the 3 to 2 N interval is received, the control S 4 is turned on, and the remaining switches are turned off.
  • the value of k is an integer greater than 1, and k may also be equal to 1, that is, the low-voltage digital-to-analog conversion circuit includes a voltage dividing unit 10, which will be described in detail below with reference to FIG.
  • the voltage dividing unit 10 is connected to a low voltage V L at one end and a voltage terminal of V outHigh -V outLow +V L at the other end for output voltage range V L ⁇ V outHigh -V outLow + V L signal; Jiaoyou ground, V L may be equal to 0, then dividing unit 10 has one end grounded and the other end terminal of a voltage value of the voltage of V outHigh -V outLow.
  • the selecting unit 11 is configured to select a signal of a certain voltage value of the voltage dividing unit 10 according to the input digital signal for output.
  • the voltage compensating unit 12 is configured to select a signal for selecting a certain voltage value of the voltage dividing unit 10 for output, and output a voltage compensation value of V outLow -V L to the output signal of the selecting unit 11, as described above. when V L is zero, the voltage compensation unit 12 outputs a signal transmission transistor array 11 to compensate for the value of V outLow.
  • the voltage compensation unit 12 can be implemented by an adder module having one input connected to the output of the pass transistor array 11 and the other input to a reference voltage of V outLow .
  • the low-voltage digital-to-analog conversion module described above can be applied to other products in addition to the data driving circuit in the display and the display.

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Abstract

本申请公开了低压数字模拟信号转换电路、数据驱动电路和显示系统，至少一个分压单元(10)，所述分压单元(10)包括：若干串联在低限电压和高限电压之间的电阻，从电阻的串联节点和高限电压连接端引出的分压输出端。通过引入分压单元(10)，使得本申请的低压数字模拟信号转换电路、数据驱动电路和显示系统为低压器件，不仅功耗低，而且占用芯片面积小。

Description

低压数字模拟信号转换电路、数据驱动电路和显示系统 技术领域
本申请涉及显示器件技术领域，尤其涉及一种低成本实现显示的数模转换器、数据驱动电路和显示系统。
背景技术
显示系统作为信息传递的一种媒介，与人们的生活息息相关。目前主流的显示系统是液晶显示系统(LCD)，此外有源矩阵有机发光二极体显示系统(AMOLED)也开始在小尺寸领域崭露头角。不管是LCD显示系统还是OLED显示系统，都需要将表示图像信息的数字信号转换成模拟信号才能在面板上显示出来。这其中就需要用到数字模拟转换器(DAC)。在显示系统中，DAC的设计是列驱动芯片中最核心的模块。在显示系统中，如图1所示，DAC一般采用电阻串的形式产生各级灰度所需的电压值，用传输晶体管阵列PTL选择输入DAC的数字信号对应灰度的电压值。如果显示系统的灰度级为256级，则需要256个电阻，以产生256个不同的电压。
LCD和OLED等显示系统用于驱动显示屏的模拟信号为中高压信号，而这中高压的模拟信号要从上述DAC中的电阻串的分压中选取，这就使得电阻串被施加了中高压，进而使得DAC中的传输晶体管阵列PTL等相关器件要为中高压器件，而中高压器件需要更大的功耗和占用更大芯片面积。
发明内容
根据本申请的第一方面，本申请提供低压数字模拟信号转换电路包括：
至少一个分压单元(10)，所述分压单元(10)包括：若干串联在低限电压和高限电压之间的电阻，从电阻的串联节点和高限电压连接端引出的分压输出端；
选择单元(11)，分别与各分压单元(10)的分压输出端连接，所述选择单元(11)用于输入数字信号，根据数字信号的控制从分压输出端中选择一个接通，并输出该分压输出端上的待补偿电压信号；
电压补偿单元(12)，其与选择单元(11)相连，用于分别输入选择单元输出的待补偿电压信号和数字信号，根据数字信号对待补偿电压信号进行补偿，使得补偿后的电压为数字信号所对应的模拟电压。
根据本申请的第二方面，本申请提供一种数据驱动电路，包括：
数据输入模块，用于输入包含图像数据的数字信号；
锁存器，与数据输入模块相连，用于数字信号锁定；
上述的低压数字模拟信号转换电路，其选择单元(11)、电压补偿单元(12)的输入端与锁存器的输出端相连。
根据本申请的第三方面，本申请提供一种包括上述数据驱动电路的显示系统。
通过引入分压单元，分压单元包括：若干串联在低限电压和高限电压之间的电阻，从电阻的串联节点和高限电压连接端引出的分压输出端；使得本申请的低压数字模拟信号转换电路、数据驱动电路和显示系统为低压器件，不仅功耗低，而且占用芯片面积小。
附图说明
图1为传统的电阻串和传输晶体管阵列的一种结构示意图；
图2为传统的数模转换器参与显示过程时的Gamma曲线图；
图3为传统的利用电阻串实现数模转换器的一种结构示意图；
图4为本申请一种实施例的低压数字模拟信号转换电路的一种Gamma曲线图；
图5为本申请一种实施的低压数字模拟信号转换电路的一种结构示意图；
图6为本申请一种实施例的包括若输入电容的模拟加法模块的一种结构示意图；
图7为本申请一种实施例的包括若输入电容的模拟加法模块的另一种结构示意图；
图8为本申请一种实施例的包括若输入电阻的模拟加法模块的一种结构示意图；
图9为本申请一种实施例的包括电压转电流模块和电流转电压模的模拟加法模块的一种结构示意图；
图10为申请当k＝4时的低压数字模拟信号转换电路的一种Gamma曲线图；
图11为申请当k＝4时的低压数字模拟信号转换电路的一种结构示意图；
图12为申请当k＝1时的低压数字模拟信号转换电路的一种结构示意图。
具体实施方式
下面通过具体实施方式结合附图对本申请作进一步详细说明。
请参考图2，图2为一N位数模转换器的Gamma曲线，N为正整数。从图2中可以看到，当输入的数字信号从20到2N变化时，数模转换器输出信号的电压范围为VoutLow到VoutHigh。VoutLow和VoutHigh的大小由LCD或OLED面板的亮度范围、像素电路、液晶分子特性等决定。
请参考图3，图3为一组列驱动电路的模块结构。列驱动电路包括数据输入模块(通常是移位寄存器模块)、锁存器模块、数模转换模块和输出缓冲。数模转换模块包括电阻串和传输晶体管阵列PTL。锁存器模块和数模转换模块都为N位，因此数模转换模块中，VoutLow～VoutHigh范围之间有2N个不同的电压值，它们通过电阻串中的电阻分压的方式产生，电阻串产生的2N个不同的电压值可以在列驱动电路的芯片中共享。每一路数模转换器通过其内的传输晶体管阵列PTL从2N个不同的电压值中选出一个作为数模转换器的输出。代表图像数据的N位数字信号通过输入模块和锁存器模块输出，此输出作为数模转换器的传输晶体管阵列PTL的输入，N位数字信号决定了其输出信号的大小，从而实现数字模拟的转换。数模转换器输出的模拟信号再通过输出缓冲器送到面板上，以实现图像的显示。
本申请公开了低压数字模拟信号转换电路、数据驱动电路和显示系统，其发明思路在于：通过将上述的电阻串分成若干个分段式电阻串即分压单元，每个分压单元的一端接低电压即低限电压，通常可为0电压，从而降低每一个分压单元各输出节点的电压值。
具体地，本申请公开的低压数字信号转模拟信号电路(以下简称低压数模转换电路)，输入N位的数字信号，对应地，输出电压范围为VoutLow～VoutHigh的模拟信号，其中VoutHigh>VoutLow，N为正整数，如图4所示为本低压数模转换电路的Gamma曲线图，其横坐标为输入的N位的数字信号，其纵坐标为对应的输出的电压范围为VoutLow～VoutHigh的模拟信号。
请参考图5，本申请的低压数模转换电路包括：
至少一个分压单元10，分压单元10包括若干串联在低限电压和高限电压之间的电阻，从电阻的串联节点和高限电压连接端引出的分压输出端。需要指出的是，有些分压单元10的高限电压并没有对应的数字信号，这种情况下，不需要从此分压单元10的高限电压端引出一个分压输出端，而是直接从此分压单元10的电阻的串联节点引出若干分压输出端即可。
选择单元11，分别与各分压单元10的分压输出端连接，选择单元11用于输入数字信号，根据数字信号的控制从分压输出端中选择一个接通，并输出该分压输出端上的待补偿电压信号；选择单元11可以包括传输晶体管阵列，传输晶体管阵列形成的开关电路与各分压单位10的分压输出端一一对应，将分压输出端分别与选择单元11的输出端连通。较优地，分压单位10至少有两个。为了进一步降低各分压单元10被施加的电压，在设计本低压数模转换电路时可以使各分压单元10的低限电压都为零，另外，为了达到更好地效果，在设计各分压单元10时，可以使各 分压单元10的高限电压尽量接近甚至相等。
电压补偿单元12，其与选择单元11相连，用于分别输入选择单元11输出的待补偿电压信号和数字信号，根据数字信号对待补偿电压信号进行补偿，使得补偿后的电压为数字信号所对应的模拟电压。电压补偿单元12根据数字信号和分压单元10的划分规则确定待补偿电压信号的补偿值，将待补偿电压和补偿值相加后输出。
电压补偿单元12有多种实现方式，以下举例说明：
电压补偿单元12包括补偿电压选择模块13和模拟加法模块14。
补偿电压选择模块13，用于根据数字信号和分压单元10的划分规则来输出补偿信号，所述补偿信号用于对待补偿电压信号进行补偿；补偿电压选择模块13可以包括补偿电压端和开关模块，具体地：补偿电压端的数量与分压单元10的数量相同，并且补偿电压端的电压值与各分压单元10的分压输出端上的待补偿电压信号需要补偿的电压值相等；开关模块数量与补偿电压端的数量相同，一个开关模块只与一个补偿电压端相连，开关模块的一端与补偿电压端相连，另一端与模拟加法模块14的一输入端相连，开关模块的控制端用于输入数字信号并在数字信号的控制下导通和断开，以输出补偿信号。
模拟加法模块14，一输入端与选择单元11的输出端相连，另一输入端与补偿电压选择模块13的输出端相连，用于将选择单元11输出的待补偿电压信号与补偿电压选择模块13输出的补偿信号的电压进行相加后输出；模拟加法模块14输出的信号为电压补偿单元12的输出信号。模拟加法模块14有许多种结构，下面试举几种。
第一种，模拟加法模块14包括一放大器和若干输入电容。
请参考图6，具体地，模拟加法模块14包括电容C1、C2和C3，以及一个放大器，其中V100和V200为模拟加法模块14的两输入端，Vout为模拟加法模块14的输出端。其连接方式为：
放大器的正输入端接地，负输入端与输出端之间接有电容C3，电容C3并联有一开关S11；放大器的负输入端还通过一电容C1与一接地开关S22相连，电容C1与此接地开关S22相连的一端还与另一开关S12的一端相连，此开关S12的另一端为所述模拟加法模块14的一输入端；放大器的负输入端还通过一电容C2与一接地开关S21相连，电容C2与此接地开关S21相连的一端还与另一开关S13的一端相连，此开关S13的另一端为所述模拟加法模块14的另一输入端。
模拟加法模块14的工作过程分为两个阶段。
第一阶段，开关S11、S12、S13导通，开关S21、S22断开，此时V100、V200分别耦合到电容C1、C2的第一端，放大器的负输入端与输出端短接，负输入端的电荷可以表示为：
Q1＝(VX-V100)*C1+(VX-V200)*C2。
第二阶段，开关S21、S22导通，开关S11、S12、S13断开，此时电容C1、C2的第一端分别耦合到地。在此过程中，放大器负输入端处于悬浮状态，其电荷保持不变，可以表示为：
Q1＝VX*C1+VX*C2+(VX-Vout)*C3。
根据上述第一阶段和第二阶段放大器负输入端的电荷公式，可以得到：
Vout＝VX+(V100*C1+V200*C2)/C3。
如果C1＝C2＝C3，根据放大器输入端虚短原理，Vref＝VX，可得：
Vout＝Vref+V100+V200。当Vref＝0，可得Vout＝V100+V200，即实现了电压相加的功能。
请参考图7，具体地，模拟加法模块14还可以不包括电容C3，而是包括电容C1和C2，以及一个放大器，其中V100和V200为模拟加法模块14的两输入端，Vout为模拟加法模块14的输出端。其连接方式为：
放大器的正输入端接地，负输入端与输出端之间接有一开关S11；所述放大器的负输入端还与一电容C2的一端相连，电容C2的另一端通过一开关S21连接到所述放大器的输出端；电容C2连有开关S21的一端，还与一开关S13的一端相连，开关S13的另一端为所述模拟加法模块14的一输入端；所述放大器的负输入端还通过一电容C1与一接地开关S22相连，电容C1与接地开关S22相连的一端还与另一开关S12的一端相连，此开关S12的另一端为所述模拟加法模块14的另一输入端。
同样地，模拟加法模块14的工作过程也分为两个阶段。
第一阶段，开关S11、S12、S13导通，开关S21、S22断开，此时V100、V200分别耦合到电容C1、C2的第一端，放大器的负输入端与输出端短接，负输入端的电荷可以表示为：
Q1＝(VX-V100)*C1+(VX-V200)*C2。
第二阶段，S21、S22导通，S11、S12、S13断开，此时电容C1、C2的第一端分别耦合到地和输出端。在此过程中，放大器负输入端处于悬浮状态，其电荷保持不变，可以表示为：Q1＝VX*C1+(VX-Vout)*C2。
根据上述第一阶段和第二阶段放大器负输入端的电荷公式，可以得到：
Vout＝V200+(V100*C1)/C2。
如果C1＝C2，则Vout＝V100+V200，即实现了电压相加的功能。
图6和图7中的开关S11、S12、S13、S21、S22指的是具有开关功能的器件。
第二种，模拟加法模块14包括一放大器和若干输入电阻。
请参考图8，具体地，模拟加法模块14包括四个电阻以及一个放大 器，其中V100和V200为模拟加法模块14的两输入端，Vout为模拟加法模块14的输出端。其连接方式为：
放大器的负输入端与输出端之间连有一电阻R1；所述放大器的负输入端还接有一接地电阻R2；所述放大器的正输入端与一电阻R3的一端相连，电阻R3的另一端为所述模拟加法模块14的一输入端；所述放大器的正输入端与一电阻R4的一端相连，电阻R4的另一端为所述模拟加法模块14的另一输入端，其中电阻R2、R3和R4的阻值相等，均为R；电阻R1的阻值是电阻R2的两倍，为2*R。
电流放大器正输入端的电压的计算公式：(V100-VX)/R＝(VX-V200)/R；可得放大器正输入端的电压VX＝(V100+V200)/2。结合另一计算公式，VX＝(Vout/2R)*R＝Vout/2，可得Vout＝V100+V200，实现了电压相加的功能。
第三种，模拟加法模块14包括电压转电流模块和电流转电压模块。
请参考图9，具体地，模拟加法模块14包括：
两电压转电流模块；一电压转电流模块的输入端为模拟加法模块14的一输入端，用于将选择单元11输出的待补偿电压信号转变成电流信号输出；若选择单元11输出的电压信号为V100，输入到此电压转电流模块后，其输出电流为V100*gm，其中gm为上述电压转电流模块的跨导。另一电压转电流模块的输入端为模拟加法模块14的另一输入端，用于将补偿电压选择模块13输出的补偿信号转变成电流信号输出；若补偿电压选择模块13输出的电压信号为V200，输入到此电压转电流模块后，其输出电流为V200*gm。
一加法节点，用于将所述两电压转电流模块输出的电流信号进行相加后输出，即将V100*gm与V200*gm相加，输出值为(V100+V200)*gm的电流信号。
一电流转电压模块，其输出端为模拟加法模块14的输出端，用于将加法节点输出的电流信号转变成电压信号进行输出，即将输入的值为(V100+V200)*gm的电流信号转变为V100+V200，从而实现了电压相加的功能。由于电流的相加更容易实施，只要将要相加的电流流过同一节点，就可以实现，因此用电压转电流的方法将电压相加的问题转变为电流相加，使方案实施起来变得更加容易。
在本申请提出的低压数模转换电路的基础，本申请还提出一种数据驱动电路，它可以包括：
数据输入模块，用于输入包含图像数据的数字信号；
锁存器，与数据输入模块相连，用于数字信号锁定；
上述的低压数模转换电路，其选择单元11、电压补偿单元12的输入端与锁存器的输出端相连。
进一步地，本申请还提出了一种显示系统，此显示系统包括了上述 的数据驱动电路。
实施例1：
本实施例进一步阐释上述的低压数模转换电路，尤其是各分压单元10连接的低限电压、高限电压以及电压补偿单元12输出的补偿信号的电压值等问题。
请返回参照图4，本申请的低压数模转换电路，输入N位的数字信号，相应地，输出电压范围为VoutLow～VoutHigh的模拟信号。
请返回参考图5，本申请的低压数模转换电路，包括：
k个分压单元10，其中第i个分压单元，一端接一低电压VL(即低限电压)，另一端接电压值为Vi的电压端(即高限电压)，用于输出电压范围为VL～Vi的信号；其中k为一大于1的正整数，i的取值范围为小于或等于k的正整数。换句话说，第1个分压单元10，一端接一低电压VL，另一端接电压值为V1的电压端，用于输出电压范围为VL～V1的信号；第2个分压单元10，一端接一低电压VL，另一端接电压值为V2的电压端，用于输出电压范围为VL～V2的信号，以此类推，第k个分压单元10，一端接一低电压VL，另一端接电压值为Vk的电压端，用于输出电压范围为VL～Vk的信号。另外，图5中分压单元10包括两个串联的电阻，这只是用于示意，并非指每个分压单元10都是包括两个电阻。
选择单元11，用于根据输入的N位数字信号选择某一分压单元的某一电压值的信号进行输出；换句话说，选择单元11的输入端接收N位数字信号，并根据此数字信号选择这k个分压单元10中的某一个分压单元10的输出电压范围的某一值进行电压信号输出，例如，根据数字信号，选择第2个分压单元10输出电压范围VL～V2中的某一值进行电压信号输出。
电压补偿单元12，用于当选择单元11选择第i个分压单元的某一电压值的信号进行输出时，对传输晶体管阵列11的输出信号进行值为Vci电压补偿后输出，这是因为分压单元10的一端接了低电平VL，此时要将电压拉低的部分重新加回去。电压补偿单元12输出的信号为本低压数模转换电路的输出信号，此输出的模拟信号再通过输出缓冲器送到面板上，以实现图像的显示。当选择11选择第1个分压单元的某一电压值的信号进行输出时，电压补偿单元12对选择单元11的输出信号进行值为Vc1的电压补偿后输出；当选择单元11选择第2个分压单元的某一电压值的信号进行输出时，电压补偿单元12对选择单元11的输出信号进行值为Vc2的电压补偿后输出，以此类推，当选择单元11选择第k个分压单元的某一电压值的信号进行输出时，电压补偿单元12对选择单元11的输出信号进行值为Vck的电压补偿后输出。另外，这里对选择单元 11的输出信号进行值为Vci电压补偿，指的是，若选择单元11的输出信号的电压值为Vout，对其进行值为Vci电压补偿后，最终的输出信号的电压值为Vout+Vci。
电压补偿单元12的一种结构中，电压补偿单元12包括补偿电压选择模块13和模拟加法模块14。下面具体说明。
补偿电压选择模块13，用于当选择单元11选择第i个分压单元10的某一电压值的信号进行输出时，输出电压值为Vci的补偿信号。例如，当选择单元11选择第1个分压单元10的某一电压值的信号进行输出时，补偿电压选择模块13输出电压值为Vc1的补偿信号。补偿电压选择模块13可以包括k个补偿电压端和k个开关模块。这k个补偿电压端中，第i个补偿电压端的值为Vci，i的取值为小于或等于k的正整数，即第1个补偿电压端的值为Vc1，第2个补偿电压端的值为Vc2，以此类推，第k个补偿电压端的值为Vck。这k个开关模块，其中第i个开关模块的一端与第i个补偿电压端相连，另一端作为补偿电压选择模块14的输出端，用于当选择单元11选择第i个分压单元10的分压输出端的某一电压值的信号进行输出时，进行导通以输出电压值为Vci的信号。例如，第1个开关模块的一端与第1个补偿电压端相连，另一端作为补偿电压选择模块14的输出端，当选择单元11选择第1个分压单元10的某一电压值的信号进行输出时，第1个开关模块进行导通以将第1个补偿电压端电压值为Vc1的信号输出给模拟加法模块14。这k个开关模块可以根据数字信号和分压单元10的划分规则来进行导通和断开的，可以有多种实现方式，例如，用一个控制器，此控制器在接收到第i个分压单元10所输出的模块信号的区间在Gamma曲线上对应的数字信号的区间里的数字信号时，发出信号，来控制第i个开关模块导通，其余开关模块断开，这里i的取值范围，如上所述为小于或等于k的正整数，即此控制器在接收到第1个分压单元10所输出的模块信号的区间在Gamma曲线上对应的数字信号的区间里的数字信号时，发出信号，来控制第1个开关模块导通，其余开关模块断开；此控制器在接收到第2个分压单元10所输出的模块信号的区间在Gamma曲线上对应的数字信号的区间里的数字信号时，发出信号，来控制第2个开关模块导通，其余开关模块断开，以此类推，不再赘述。
以上详述了本实施的低压数模转换电路的结构，在上述结构中，VL、Vi和Vci被配置为：
VL被配置为一低电平，较优地，VL可为0。
返回再参照图4，在VoutLow～VoutHigh之间取不等于VoutLow、VoutHigh的k-1个不同的电压值，这k-1个电压值由小到大排列的第i个电压值为Vouti，另外，因为i的取值范围为小于或等于k的正整数，所以i可以k 值，所以令Voutk＝VoutHigh，另外为便于叙述，令Vout0＝VoutLow。
所以Vi和Vci被配置为：Vi＝Vouti-Vouti-1+VL，Vci＝Vouti-1-VL。
换句话说：
对于第1个分压单元，V1＝Vout1-Vout0+VL，Vc1＝Vout0-VL；
对于第2个分压单元，V2＝Vout2-Vout1+VL，Vc2＝Vout1-VL；
以此类推，对于最后一个即第k个分压单元，Vk＝Voutk-Voutk-1+VL，Vck＝Voutk-1-VL。
较优地，在VoutLow～VoutHigh之间取不等于VoutLow、VoutHigh的k-1个不同的电压值时，可以让这k-1个值代表的点均分VoutLow～VoutHigh，即VoutLow(Vout0)、Vout1、Vout2、…、Vouti、…、Voutk-1、VoutHigh(Voutk)为一等差数列。
再请参考图4，在纵坐标为取了k-1个点后，纵坐标VoutLow～VoutHigh之间被分为k个区间，相应地，横坐标也被分为k个区间，0～①区间的数字信号对应Vout0～Vout1的模拟信号，①～②区间的数字信号对应Vout1～Vout2的模拟信号，以此类推。这样，在设计分压单元10时，根据每个区间对应的电阻数，可以将原来类似图3中的一个电阻串按要求分成符合需求的若干分压单元10。
为了进一步地说明本实施例，下面以一个实际的例子对本实施例加以补充。
请参考图9，与图4一样，为本低压数模转换电路的Gamma曲线图。图4中k取值为4时，即为图9所示。Gamma曲线被分段成了四部分，纵坐标由大到小，电压值分别为Vout4(VoutHigh)、Vout3、Vout2、Vout1、Vout0(VoutLow)。相应地，横坐标也被分成了四部分，0～①区间、①～②区间、②～③区间、③～2N区间。0～①区间的数字信号对应输出的电压范围是Vout0～Vout1，电压差值为Vout1-Vout0；①～②区间的数字信号对应输出的电压范围是Vout1～Vout2，电压差值为Vout2-Vout1；②～③区间的数字信号对应输出的电压范围是Vout3～Vout2，电压差值为Vout3-Vout2；③～2N区间的数字信号对应输出的电压范围是Vout4～Vout3，电压差值为Vout4-Vout3。图10示出了图9所示分段的一种实现方式。在这种分段方式中，选择单元11可以为传输晶体管阵列，其结构保持不变，即仍与图3中的传输晶体管阵列PTL类似。与图3不同的是，图10不再有一个两端分别接VoutLow、VoutHigh的电阻串，而是将图3中的电阻串分成四段，即分成四个分压单元10，第一个分压单元10的电压范围是0～Vout1-Vout0，即其一端接地，另一端接值为Vout1-Vout0的电压端；第二个分压单元10的电压范围是0～Vout2-Vout1，即其一端接地，另一端接值为Vout2-Vout1的电压端；第三个分压单元10的电压范围是0～Vout3-Vout2，即其一端接地，另一端接值为Vout3-Vout2的电压端；第四个分压单元10的电压范围是 0～Vout4-Vout3，即其一端接地，另一端接值为Vout4-Vout3的电压端。这样，通过对电阻串进行分段，每一个分压单元的输出的起始电压都降到了零，这样可以有效降低每一个分压单元的电压值。因此，虽然选择单元11的电路整体结构不变，还是与图3中的传输晶体管阵列PTL类似，但是由于电阻串进行了分段，每一个分压单元的输出电压降低到一个低的电压范围，因此选择单元11中的相关器件——如当其为传输晶体管阵列时，晶体管也可以采用低压工艺来实现，从而选择单元11成为一个低压器件，具有低功耗，占用面积小的特点。
如上所述，数据输入模块通过N位锁存器模块输入N位的数字信号，选择单元11根据输入的N位数字信号，选择输出一个具有对应电压值的模拟信号。这个电压值并不是原始的显示电压，而是由于电阻串被分段而被拉低到了低电压区域的一个电压值，为了使最终显示信号为原始的显示电压，此时需要将电压值被拉低的部分重新拉回去。这个把电压值重新拉回到原始的显示电压值，可以通过补偿电压选择模块13和模拟加法模块14来实现。
模拟加法模块14至少有两个输入端，其中一个输入端接到选择单元11的输出端，另外一个输入端则接到补偿电压选择模块13，补偿电压选择模块13是输出由于Gamma曲线或者说电阻串分段造成的电压损失。由于Gamma曲线被分成四段，因此共有四种电压值可供选择，分别由开关S1、S2、S3、S4控制，当输入数字信号在0～①区间时，S1导通，其余开关断开；当输入数字信号在①～②区间时，S2导通，其余开关断开，以此类推。这样，模拟加法模块14，被接低的电压信号又得到了恢复。这里的开关S1、S2、S3、S4指是具有开关功能的器件。开关S1、S2、S3、S4，是根据数字信号和分压单元10的划分规则来进行导通和断开的，可以有多种实现方式，比如，用一个控制器，此控制器在接收到在0～①区间的数字信号时，控制S1导通，其余开关断开；在接收到在①～②区间的数字信号时，控制S2导通，其余开关断开；在接收到在②～③区间的数字信号时，控制S3导通，其余开关断开；在接收到在③～2N区间的数字信号时，控制S4导通，其余开关断开。
补充的例子是将电阻串分成了4个分压单元10，即k＝4；在其他实施例中，电阻串如上所述也可以分成k个分压单元10，k越大，每一个的分压单元10输出的电压范围就越小，从而可以用更低的电压来驱动。
需要注意的是，本实施例中，k的取值是大于1的整数，k也可以等于1，即本低压数模转换电路包括一个分压单元10，下面结合图12详细说明。
请参考图12，分压单元10一端接一低电压VL，另一端接电压值为VoutHigh-VoutLow+VL的电压端，用于输出电压范围为VL～VoutHigh-VoutLow+VL 的信号；较优地，VL也可以等于0，此时分压单元10一端接地，另一端接电压值为VoutHigh-VoutLow的电压端。
选择单元11，用于根据输入的数字信号选择分压单元10的某一电压值的信号进行输出。
电压补偿单元12，用于选择单元11选择分压单元10的某一电压值的信号进行输出时，对选择单元11的输出信号进行值为VoutLow-VL的电压补偿后输出，如上所述当VL为零，电压补偿单元12对传输晶体管阵列11的输出信号进行值为VoutLow的补偿。电压补偿单元12可以用一个加法器模块来实现，此加法器模块的一个输入端与传输晶体管阵列11的输出端相连，另一个输入端接入一值为VoutLow的参考电压。
上述的低压数模转换模块除了应用与显示器中的数据驱动电路，也可以应用于其它产品中。
以上应用了具体个例对本发明进行阐述，只是用于帮助理解本发明，并不用以限制本发明。对于本领域的一般技术人员，依据本发明的思想，可以对上述具体实施方式进行变化。

Claims (10)

  1. 低压数字模拟信号转换电路，其特征在于，包括：
    至少一个分压单元(10)，所述分压单元(10)包括：若干串联在低限电压和高限电压之间的电阻，从电阻的串联节点和高限电压连接端引出的分压输出端；
    选择单元(11)，分别与各分压单元(10)的分压输出端连接，所述选择单元(11)用于输入数字信号，根据数字信号的控制从分压输出端中选择一个接通，并输出该分压输出端上的待补偿电压信号；
    电压补偿单元(12)，其与选择单元(11)相连，用于分别输入选择单元输出的待补偿电压信号和数字信号，根据数字信号对待补偿电压信号进行补偿，使得补偿后的电压为数字信号所对应的模拟电压。
  2. 如权利要求1所述的低压数字模拟信号转换电路，其特征在于，所述电压补偿单元(12)根据数字信号和分压单元(10)的划分规则确定待补偿电压信号的补偿值，将待补偿电压和补偿值相加后输出。
  3. 如权利要求2所述的低压数字模拟信号转换电路，其特征在于，所述电压补偿单元(12)包括：
    补偿电压选择模块(13)，用于根据数字信号和分压单元(10)的划分规则来输出补偿信号，所述补偿信号用于对待补偿电压信号进行补偿；
    模拟加法模块(14)，一输入端与所述选择单元(11)的输出端相连，另一输入端与所述补偿电压选择模块(13)的输出端相连，用于将选择单元(11)输出的待补偿电压信号与补偿电压选择模块(13)输出的补偿信号的电压进行相加后输出；模拟加法模块(14)输出的信号为所述电压补偿单元(12)的输出信号。
  4. 如权利要求3所述的低压数字模拟信号转换电路，其特征在于，所述补偿电压选择模块(13)包括：
    补偿电压端，所述补偿电压端的数量与分压单元(10)的数量相同，并且所述补偿电压端的电压值与各分压单元(10)的分压输出端上的待补偿电压信号需要补偿的电压值相等；
    开关模块，所述开关模块数量与补偿电压端的数量相同，一个开关模块与一个补偿电压端相连，所述开关模块的一端与补偿电压端相连，另一端与所述模拟加法模块(14)的一输入端相连，开关模块的控制端用于输入数字信号并在数字信号的控制下导通和断开，以输出所述的补偿信号。
  5. 如权利要求3所述的低压数字模拟信号转换电路，其特征在于，所述模拟加法模块(14)包括：
    两电压转电流模块；一电压转电流模块的输入端为所述模拟加法模块(14)的一输入端，用于将选择单元(11)输出的待补偿电压信号转 变成电流信号输出；另一电压转电流模块的输入端为所述模拟加法模块(14)的另一输入端，用于将补偿电压选择模块(13)输出的补偿信号转变成电流信号输出；
    一加法节点，用于将所述两电压转电流模块输出的电流信号进行相加后输出；
    一电流转电压模块，其输出端为所述模拟加法模块(14)的输出端，用于将加法节点输出的电流信号转变成电压信号进行输出。
  6. 如权利要求3所述的低压数字模拟信号转换电路，其特征在于，所述模拟加法模块(14)包括：
    一放大器，此放大器的正输入端接地，负输入端与输出端之间接有电容C3，电容C3并联有一开关S11；放大器的负输入端还通过一电容C1与一接地开关S22相连，电容C1与此接地开关S22相连的一端还与另一开关S12的一端相连，此开关S12的另一端为所述模拟加法模块(14)的一输入端；放大器的负输入端还通过一电容C2与一接地开关S21相连，电容C2与此接地开关S21相连的一端还与另一开关S13的一端相连，此开关S13的另一端为所述模拟加法模块(14)的另一输入端；
    或者，
    一放大器，此放大器的正输入端接地，负输入端与输出端之间接有一开关S11；所述放大器的负输入端还与一电容C2的一端相连，电容C2的另一端通过一开关S21连接到所述放大器的输出端；电容C2连有开关S21的一端，还与一开关S13的一端相连，开关S13的另一端为所述模拟加法模块(14)的一输入端；所述放大器的负输入端还通过一电容C1与一接地开关S22相连，电容C1与接地开关S22相连的一端还与另一开关S12的一端相连，此开关S12的另一端为所述模拟加法模块(14)的另一输入端；
    或者，
    一放大器，此放大器的负输入端与输出端之间连有一电阻R1；所述放大器的负输入端还接有一接地电阻R2；所述放大器的正输入端与一电阻R3的一端相连，电阻R3的另一端为所述模拟加法模块(14)的一输入端；所述放大器的正输入端与一电阻R4的一端相连，电阻R4的另一端为所述模拟加法模块(14)的另一输入端，其中电阻R2、R3和R4的阻值相等，电阻R1的阻值是电阻R2的两倍。
  7. 如权利要求1所述的低压数字模拟信号转换电路，其特征在于，所述选择单元(11)包括传输晶体管阵列，所述传输晶体管阵列形成的开关电路与各分压单位(10)的分压输出端一一对应，将分压输出端分别与选择单元(11)的输出端连通。
  8. 如权利要求1所述的低压数字模拟信号转换电路，其特征在于， 所述分压单位(10)至少有两个。
  9. 一种数据驱动电路，其特征在于，包括：
    数据输入模块，用于输入包含图像数据的数字信号；
    锁存器，与数据输入模块相连，用于数字信号锁定；
    权利要求1至9中任一项所述的低压数字模拟信号转换电路，其选择单元(11)、电压补偿单元(12)的输入端与锁存器的输出端相连。
  10. 一种显示系统，包括如权利要求10所述的数据驱动电路。
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