CN104143523A - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- CN104143523A CN104143523A CN201310163044.1A CN201310163044A CN104143523A CN 104143523 A CN104143523 A CN 104143523A CN 201310163044 A CN201310163044 A CN 201310163044A CN 104143523 A CN104143523 A CN 104143523A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a manufacturing method for a semiconductor device, and relates to the technical field of semiconductors. The manufacturing method includes the steps that (101), a front end device is provided, and a dielectric layer is formed on the front end device; (102), the dielectric layer is processed in a graphical mode to form a groove structure; (103), the groove structure is cleaned; (104), the groove structure is preprocessed; (105), a diffusion impervious layer is formed in the groove structure. According to the manufacturing method for the semiconductor device, the step of preprocessing the groove structure is added after the step of cleaning the groove structure, residuals generated by the graphical technology are further removed to a certain degree, moisture in the semiconductor device is removed, damage to the dielectric layer in the graphical process can be repaired, the RC delay phenomenon of the semiconductor device is improved, and the performance of the semiconductor device is improved.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of manufacture method of semiconductor device.
Background technology
In technical field of semiconductors, development along with semiconductor technology, people are more and more higher to the requirement of the integrated level of semiconductor device, integrated circuit live width is more and more less, in the back-end process (BEOL) of semiconductor device, metal interconnection layer is more and more, metallic resistance rate is increased, and parasitic capacitance increases, the increase that has finally caused RC to postpone.And along with constantly the dwindling of the process node of semiconductor fabrication, for example, when process node develops into 20nm and following, it is more and more serious that the problems referred to above become.
In order to solve RC delay issue, adoptable feasible program comprises and adopts metal that resistivity is lower as metal level, or adopts dielectric material that dielectric constant is lower as dielectric layer.Because prior art has started extensively to adopt the copper product of resistivity lower (aluminium relatively) as metal level, therefore, along with constantly reducing of process node, people start more and more to pay close attention to the dielectric material that employing dielectric constant (k value) is lower and reduce RC delay as dielectric layer.In the prior art, super low k dielectric (ULK) has been applied among the back-end process of semiconductor device, such as being applied in the BEOL of 20nm process node.
As shown in Figure 1, it shows the indicative flowchart of the manufacture method of semiconductor device of the prior art.In the prior art, apply super low k dielectric as the manufacture method of the semiconductor device of dielectric layer, generally comprise following steps:
Step e 1, provide front end device, on described front end device, form super low k dielectric.
Exemplary, can adopt the methods such as chemical vapour deposition technique or physical vaporous deposition on front end device, to deposit the super low k dielectric of one deck as super low k dielectric.Wherein, front end device refers to the device forming before BEOL, at this, the concrete structure of front end device is not limited.
Step e 2, described super low k dielectric is carried out to graphical treatment, to form patterned super low k dielectric (that is, forming groove structure in super low k dielectric).
Wherein, graphical treatment, is mainly to form groove structure on super low k dielectric,, forms patterned super low k dielectric that is.About the concrete pattern of the groove structure that forms, those skilled in the art can design according to actual needs, at this, does not also limit.Super low k dielectric is carried out to graphical treatment, can adopt variety of way to realize, such as adopting double-pattern technology to carry out composition or utilize the method for integrated etching (All-in-one Etch) to carry out etching etc., at this, do not limit.Wherein, super low k dielectric is carried out to the method for etching, general using plasma dry etching, the method can cause damage to a certain extent to super low k dielectric, causes k value to become to a certain extent large.
Step e 3, this super low k dielectric is cleaned.
Exemplary, the suitable cleaning fluid of the general employing of method of cleaning carries out wet-cleaned (wet clean).
Generally speaking, this super low k dielectric is being carried out to graphical treatment (conventionally adopting the method for etching) afterwards, need to carry out clean to this super low k dielectric, to remove the residue producing in graphical process, the polymer residue producing as etching etc.Yet the process of cleaning generally can produce moisture, and this moisture can affect the performance that finally makes semiconductor device.And if do not cleaned, residue also can affect the performance of semiconductor device.
And, in the manufacture method of this semiconductor device, in the process that super low k dielectric carries out graphically (being mainly etching) and processes and clean to this, generally all can cause damage (can cause the k value of dielectric layer to become large) to low k dielectric, certainly, damage is main from the etching technics in graphical process (such as plasma dry etching).
Although in the technique of follow-up formation barrier layer (barrier layer)/Seed Layer (seed layer), degasification (degas) is processed can alleviate the problems referred to above to a certain extent.Yet, when the time that degasification (degas) is processed is greater than 180 seconds, will cause worse problem, can cause occurring that the problem in cavity (void) is more serious in the metal level of follow-up formation, thereby have a strong impact on the performance of the semiconductor device finally making.Therefore, rely on degasification (degas) to deal with the problems referred to above often also unsatisfactory.
Step e 4, on this super low k dielectric, form diffusion impervious layer (barrier layer).
Wherein, diffusion impervious layer, is called for short diffusion layer, and its effect is mainly to prevent that in the metal level of follow-up formation, metal diffuses into front end device.The material on barrier layer (barrier layer), can select the materials such as tantalum nitride (TaN).
Step e 5, the Seed Layer (seed layer) that forms on diffusion impervious layer (barrier layer).
Wherein, the effect of Seed Layer is to be convenient to follow-up formation metal level.The material of Seed Layer can be metal or alloy.And Seed Layer can be one or more layers.
Step e 6, at the upper metal level that forms of Seed Layer (seed layer).
Wherein, the method for formation metal level can be ECP(electrochemistry galvanoplastic).The material of metal level, can, for aluminium, copper etc., be preferably copper.
General, after step e 6, also comprise step e 7: this metal level is carried out to CMP(chemico-mechanical polishing) process.Wherein, the object of metal level being carried out to CMP is: planarization metal layer, and expose super low k dielectric.
So far, completed and in prior art, used super low k dielectric briefly introducing as the committed step of the manufacture method of the semiconductor device of dielectric layer.From above-mentioned, introduced, in prior art, afterwards, can produce residue super low k dielectric being carried out to graphically (such as etching).For avoiding residue to cause harmful effect to the performance of semiconductor device, generally need after to this, super low k dielectric carries out graphical treatment, this super low k dielectric be cleaned, to remove the residue producing in graphical process.Yet the process of cleaning generally can produce moisture, and this moisture can affect the performance of the semiconductor device finally making.And, in the manufacture method of this semiconductor device, to this, super low k dielectric carries out, in process graphical and that clean, all can causing certain damage to low k dielectric, this can cause k value to become large to a certain extent, increases the weight of the RC delay phenomenon of semiconductor device.Although degasification (degas) treatment process in the technique of follow-up formation diffusion impervious layer (barrier layer)/Seed Layer (seed layer) can be alleviated the problems referred to above to a certain extent, but, when the time that degasification (degas) is processed is greater than 180 seconds, to cause worse problem, can cause occurring in the metal level of follow-up formation that the problem in cavity (void) is more serious, thereby have a strong impact on the performance of the semiconductor device finally making.Certainly, when dielectric layer not adopts super low k dielectric but adopts ordinary dielectric material, also can there are to a certain extent the problems referred to above.
Therefore, be necessary to propose a kind of manufacture method of new semiconductor device, to address the above problem.
Summary of the invention
The manufacture method that the invention provides a kind of semiconductor device, comprising:
Step S101: front end device is provided, forms dielectric layer on described front end device;
Step S102: described dielectric layer is carried out to graphical treatment to form groove structure;
Step S103: described groove structure is cleaned;
Step S104: described groove structure is carried out to preliminary treatment;
Step S105: form diffusion impervious layer in described groove structure.
Further, described dielectric layer is low k dielectric.
Wherein, in described step S102, described dielectric layer is carried out to the integrated etching of method of graphical treatment.
Wherein, in preliminary treatment described in described step S104, be process annealing.
Wherein, described stress relief annealed annealing temperature is 300-400 ℃
Wherein, after described step S105, also comprise step S106: on described diffusion impervious layer, form Seed Layer.
Wherein, after described step S106, also comprise step S107: in described Seed Layer, form metal level.
Wherein, in described step S107, the method that forms described metal level is electrochemistry galvanoplastic.
Wherein, after described step S107, also comprise step S108: described metal level is carried out to chemico-mechanical polishing.
The manufacture method of semiconductor device provided by the invention, by increasing dielectric layer (being mainly groove structure) carried out to pretreated step after the step dielectric layer (being mainly groove structure) is cleaned, can further remove to a certain extent the residue that graphical technique produces, drive away the moisture in semiconductor device, and can repair the damage in graphical process, dielectric layer being caused, improve the RC delay phenomenon of semiconductor device, improve the performance of semiconductor device.
Accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Fig. 1 is the indicative flowchart of the manufacture method of semiconductor device of the prior art;
Fig. 2 is the indicative flowchart of the manufacture method of semiconductor device of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
Should be understood that, the present invention can be with multi-form enforcement, and should not be interpreted as the embodiment that is confined to propose here.On the contrary, provide these embodiment to expose thorough and complete, and scope of the present invention is fully passed to those skilled in the art.In the accompanying drawings, for clear, the size in Ceng He district and relative size may be exaggerated.Same reference numerals represents identical element from start to finish.
Be understood that, when element or layer be called as " ... on ", " with ... adjacent ", " being connected to " or " being coupled to " other element or when layer, its can be directly on other element or layer, with it adjacent, connect or be coupled to other element or layer, or can there is element or layer between two parties.On the contrary, when element be called as " directly exist ... on ", when " with ... direct neighbor ", " being directly connected to " or " being directly coupled to " other element or layer, there is not element or layer between two parties.Although it should be understood that and can use term first, second, third, etc. to describe various elements, parts, district, floor and/or part, these elements, parts, district, floor and/or part should not limited by these terms.These terms are only used for distinguishing an element, parts, district, floor or part and another element, parts, district, floor or part.Therefore, do not departing under the present invention's instruction, the first element discussed below, parts, district, floor or part can be expressed as the second element, parts, district, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... on ", " above " etc., thereby can be used for convenience of description the relation of element shown in description figure or feature and other element or feature here.It should be understood that except the orientation shown in figure, spatial relationship term intention also comprise use and operate in the different orientation of device.For example, if the device in accompanying drawing upset, then, be described as " below other element " or " under it " or " under it " element or feature will be oriented to other element or feature " on ".Therefore, exemplary term " ... below " and " ... under " can comprise upper and lower two orientations.Device can additionally be orientated (90-degree rotation or other orientation) and as used herein spatial description language correspondingly explained.
The object of term is only to describe specific embodiment and not as restriction of the present invention as used herein.When this uses, " " of singulative, " one " and " described/to be somebody's turn to do " also intention comprise plural form, unless the other mode of pointing out known in context.It is also to be understood that term " composition " and/or " comprising ", when using in specification, determine the existence of described feature, integer, step, operation, element and/or parts, but do not get rid of one or more other existence or the interpolations of feature, integer, step, operation, element, parts and/or group.When this uses, term "and/or" comprises any and all combinations of relevant Listed Items.
In order thoroughly to understand the present invention, will detailed step and detailed structure be proposed in following description, so that the manufacture method of the semiconductor device that explaination the present invention proposes.Preferred embodiment of the present invention is described in detail as follows, yet except these are described in detail, the present invention can also have other execution modes.
Below, the manufacture method of the semiconductor device that the embodiment of the present invention proposes is described with reference to Fig. 2.Wherein, Fig. 2 shows the indicative flowchart of the manufacture method of semiconductor device of the present invention.The manufacture method of the semiconductor device of the embodiment of the present invention, comprises the steps:
Steps A 1, provide a front end device, on described front end device, form dielectric layer.
Wherein, this dielectric layer can be metal intermetallic dielectric layer or interlayer dielectric layer; The material of this dielectric layer, can be ordinary dielectric material (formation be common dielectric layer), can low k dielectric (formation be low k dielectric), can be also ultralow k dielectric material (formation be super low k dielectric).In the present embodiment, this dielectric layer preferably adopts super low k dielectric.In particular, when semiconductor device adopting process node is 32nm and following processing procedure, this dielectric layer preferably adopts super low k dielectric.Generally speaking, low k dielectric refers to that dielectric constant (k value) is less than 4 dielectric material, and super low k dielectric refers to that dielectric constant (k value) is less than 2 dielectric material.
In the present embodiment, front end device refers to the device forming before at back-end process (BEOL), at this, the concrete structure of front end device is not limited.The method that forms dielectric layer can be chemical vapour deposition technique or physical vaporous deposition etc.Exemplary, in embodiments of the present invention, adopt chemical vapour deposition technique on front end device, to deposit the super low k dielectric of one deck as dielectric layer (that is, forming super low k dielectric).
Steps A 2, described dielectric layer is carried out to graphical treatment, to form groove structure.
The object that those skilled in the art will appreciate that graphical treatment is to form groove (such as via hole etc.) structure on dielectric layer,, forms patterned dielectric layer that is; About the concrete pattern of the groove structure that forms, those skilled in the art can design according to actual needs, at this, does not also limit.Dielectric layer (for example low k dielectric) is carried out to graphical treatment, can adopt variety of way to realize, such as adopting double-pattern technology to carry out composition or utilize the method for integrated etching (All-in-one Etch) to carry out etching etc., at this, do not limit.Wherein, dielectric layer is carried out to the concrete grammar of etching, general using plasma dry etching, the method can cause certain damage to dielectric layer, causes to a certain extent the k value of dielectric layer to become large, and then causes the RC of semiconductor device to postpone more serious.And, in this dielectric layer being carried out to the process of graphically (etching), tending to produce residue (being generally polymer residue), this residue also can affect the performance of semiconductor device.
Steps A 3, described groove structure is cleaned.
Exemplary, the method for cleaning can be wet-cleaned (wet clean); And those skilled in the art can select adopted cleaning fluid according to actual conditions, does not limit at this.
Wherein, the object of this groove structure being carried out to clean is: remove the residue producing in graphical process, with the performance of the semiconductor device that guarantees finally to make.
Those skilled in the art will appreciate that groove structure is cleaned, be in fact generally whole dielectric layer and Semiconductor substrate etc. are cleaned simultaneously.In the process of cleaning, cleaning fluid generally also can cause certain damage to dielectric layer, causes to a certain extent the k value of dielectric layer to become large, and then causes the RC of semiconductor device to postpone more serious.
Steps A 4, this groove structure is carried out to preliminary treatment.
Wherein, preliminary treatment is for follow-up formation diffusion impervious layer (barrier).And preliminary treatment can realize the processing method of following same or similar technique effect for annealing in process or other.
Exemplary, when preliminary treatment is annealing in process, the method for annealing can be: the front end device that forms this groove structure is put into annealing furnace (furnace) and carry out annealing in process.In the present embodiment, annealing in process is preferably process annealing, to avoid that front end device and dielectric layer are caused to damage.Stress relief annealed temperature, is preferably 300-400 ℃.
In the present embodiment, comprise the preliminary treatment of annealing in process, generally have following technique effect: (1) can further remove the residue of graphical technique to a certain extent, temperature when its reason is annealing in process can make the residue of graphical technique further volatilize and remove; (2) can drive away the moisture in semiconductor device, wherein moisture mainly comes from cleaning step and surrounding environment; (3) can repair the damage in dielectric layer being carried out to graphical and cleaning process, dielectric layer being caused, the k value of dielectric layer is returned to the graphical level before of approaching quilt, this will be conducive to improve the RC delay of the semiconductor device finally making; (4), because annealing in process can be removed the gas in front end device and dielectric layer to a certain extent, the metal level that therefore can reduce follow-up formation produces the probability in cavity (void).Visible, the embodiment of the present invention, by increase the step of annealing in process after cleaning, has improved the performance of the semiconductor device finally making.
Steps A 5, on described groove structure, form diffusion impervious layer (barrier layer).
Wherein, in the present embodiment, on groove structure, form diffusion impervious layer and refer to and on groove structure, form diffusion impervious layer, and whether be formed with diffusion impervious layer for the region outside diffusion impervious layer, do not limit.Generally speaking, the effect of diffusion impervious layer is mainly to prevent that the metal in the metal level of follow-up formation from diffusing into front end device.In the present embodiment, the material of diffusion impervious layer (barrier layer) preferably adopts tantalum nitride (TaN).
Steps A 6, the Seed Layer (seed layer) that forms on diffusion impervious layer (barrier layer).
Wherein, the effect of Seed Layer is to be convenient to follow-up formation metal level.The material of Seed Layer can be metal or alloy.And Seed Layer can be one or more layers.And in embodiments of the present invention, steps A 6 can be omitted.
Steps A 7, at the upper metal level that forms of Seed Layer (seed layer).
Wherein, the method for formation metal level can be ECP(electrochemistry galvanoplastic).The material of metal level, can, for aluminium, copper etc., be preferably copper.Those skilled in the art will appreciate that metal level is directly formed on diffusion impervious layer when omitting steps A 6.
For example, because the embodiment of the present invention has increased the step of preliminary treatment (annealing in process) with respect to prior art, this step can be removed the gas in front end device and dielectric layer to a certain extent, therefore reduced the probability that produces cavity (void) in the metal level that this step forms, that is the empty quantity, having in the unit are of the metal level of the present embodiment will be far less than metal level of the prior art.
Steps A 8, this metal level is carried out to CMP(chemico-mechanical polishing).
Wherein, the object of metal level being carried out to CMP is, planarization metal layer, and expose dielectric layer.
So far, completed the briefly introducing of committed step of manufacture method of the semiconductor device of the embodiment of the present invention.
The manufacture method of the semiconductor device that the embodiment of the present invention provides, for example, by increase the step of dielectric layer being carried out to preliminary treatment (annealing in process) after the step that dielectric layer is cleaned, can further remove to a certain extent the residue of graphical technique, drive away the moisture in semiconductor device, and can repair the damage in graphical process, dielectric layer being caused, improve the RC delay phenomenon of semiconductor device, thereby improved the performance of semiconductor device.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (9)
1. a manufacture method for semiconductor device, is characterized in that, described in comprise:
Step S101: front end device is provided, forms dielectric layer on described front end device;
Step S102: described dielectric layer is carried out to graphical treatment to form groove structure;
Step S103: described groove structure is cleaned;
Step S104: described groove structure is carried out to preliminary treatment;
Step S105: form diffusion impervious layer in described groove structure.
2. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, described dielectric layer is low k dielectric.
3. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, in described step S102, described dielectric layer is carried out to the integrated etching of method of graphical treatment.
4. the manufacture method of semiconductor device as claimed in claim 1, is characterized in that, in preliminary treatment described in described step S104, is process annealing.
5. the manufacture method of semiconductor device as claimed in claim 4, is characterized in that, described stress relief annealed annealing temperature is 300-400 ℃.
6. the manufacture method of the semiconductor device as described in claim 1 to 5 any one, is characterized in that, also comprises step S106: on described diffusion impervious layer, form Seed Layer after described step S105.
7. the manufacture method of semiconductor device as claimed in claim 6, is characterized in that, also comprises step S107: in described Seed Layer, form metal level after described step S106.
8. the manufacture method of semiconductor device as claimed in claim 7, is characterized in that, in described step S107, the method that forms described metal level is electrochemistry galvanoplastic.
9. the manufacture method of semiconductor device as claimed in claim 7, is characterized in that, also comprises step S108: described metal level is carried out to chemico-mechanical polishing after described step S107.
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| CN201310163044.1A CN104143523A (en) | 2013-05-06 | 2013-05-06 | Manufacturing method for semiconductor device |
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| CN201310163044.1A CN104143523A (en) | 2013-05-06 | 2013-05-06 | Manufacturing method for semiconductor device |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020106908A1 (en) * | 1999-09-02 | 2002-08-08 | Applied Materials, Inc. | Precleaning process for metal plug that minimizes damage to low-kappa dielectric |
| US20050045206A1 (en) * | 2003-08-26 | 2005-03-03 | Smith Patricia Beauregard | Post-etch clean process for porous low dielectric constant materials |
| CN1624895A (en) * | 2003-09-19 | 2005-06-08 | 国际商业机器公司 | Formation of low resistance via contacts in interconnect structures |
-
2013
- 2013-05-06 CN CN201310163044.1A patent/CN104143523A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020106908A1 (en) * | 1999-09-02 | 2002-08-08 | Applied Materials, Inc. | Precleaning process for metal plug that minimizes damage to low-kappa dielectric |
| US20050045206A1 (en) * | 2003-08-26 | 2005-03-03 | Smith Patricia Beauregard | Post-etch clean process for porous low dielectric constant materials |
| CN1624895A (en) * | 2003-09-19 | 2005-06-08 | 国际商业机器公司 | Formation of low resistance via contacts in interconnect structures |
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Application publication date: 20141112 |