CN104142666A - Production control device and method for multi-process equipment on basis of state machines - Google Patents
Production control device and method for multi-process equipment on basis of state machines Download PDFInfo
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Abstract
The invention discloses a production control device and method for multi-process equipment on basis of state machines. The production control device comprises an upper computer, an FPGA module connected with the upper computer and ARM modules used for controlling work of all processes, wherein each ARM module is used for controlling the work of one process; the ARM modules used for controlling the work of the processes serve as sub-state machines and are respectively connected with the FPGA module which serves as a main state machine, and the ARM modules and the FPGA module form a star topological structure; the FPGA module is connected with a motor used for shifting workpieces and a sensor used for detecting positions of the workpieces. The FPGA module is connected with the ARM modules through interactive interface modules. The corresponding ARM modules are controlled to be started according to the states of the ARM modules and the positions of the workpieces in production of the multi-process equipment. When customer requirements are changed, the sub-state machines of new processes can be conveniently modified and built. The production control device has the advantages of being high in extendibility, low in cost, high in stability and the like.
Description
Technical field
The present invention relates to a kind of multiple operation device fabrication control device and method, particularly a kind of multiple operation device fabrication control device and method based on state machine.
Background technology
In order to improve the production and processing efficiency of workpiece device and to save production and processing cost, a lot of workpiece devices adopt multiple operation equipment to carry out respective handling in processing process, in every procedure processing procedure, need to reasonably control for time of every procedure and duty etc., the production procedure of existing multiple operation equipment is controlled and is conventionally adopted following several method:
1, adopt high speed industrial computer supervisory controller to write, and realize the input of external signal and output by pci bus data inserting capture card.Utilize the high-speed computation ability of industrial computer, all process steps is managed concentratedly and controlled.Although can control at high speed whole system, have the shortcoming that cost is high.
2,, for cost control problem, the high speed industrial computer in the 1st kind of method of employing PLC replacement and the scheme of data collecting card, utilize PLC is more stable, fan-out capability is stronger output element and input block, directly connects external mechanical devices and control.Although energy workout cost problem, because PLC performance is relatively poor, still there is shortcomings such as cannot moving advanced algorithm, poor expandability in scheme.
3, adopt multi-disc embedded Control board, control respectively each procedure, control panel piece intercommunication is coordinated the process control of whole flow process.This scheme has solved Cost Problems well, and along with embedded technology development, arithmetic capability and the resource of a lot of embedded chips are improved.But, there is the shortcoming of total tune difficulty in this distributed control thought.When needs increase operation, need to revise the information between each board, extensibility is poor.
Summary of the invention
The shortcoming that the object of the invention is to overcome prior art, with not enough, provides the multiple operation device fabrication control device based on state machine that a kind of cost is low, extensibility is strong and stability is high.
The multiple operation device fabrication control method that provides a kind of said apparatus to realize is provided.
The first object of the present invention is achieved through the following technical solutions: a kind of multiple operation device fabrication control device based on state machine, the FPGA that comprise host computer, is connected with host computer (Field Programmable Gate Array, field programmable gate array) module and for controlling the ARM module of each procedure work, the wherein wherein work of a procedure of each ARM module controls; Described for the ARM module of controlling each procedure work as sub-state machine, be connected with the FPGA module as host state machine respectively, form stelliform connection topology configuration with FPGA module; Described FPGA module connects for shifting the motor of workpiece and for detection of the sensor of the location of workpiece.
Preferably, described FPGA module is also connected with fault display module and fault recovery module, shows the fault of sub-state machine ARM module by fault display module, by fault recovery module, the sub-state machine of fault is resetted.
Preferably, described FPGA module is connected with a plurality of interactive interface array modules, by each interactive interface array module, is connected with each ARM module, and wherein each interactive interface array module comprises control interface, state interface and data transmission interface; Described control interface and state interface adopt high speed photo coupling to do parallel transmission, and described data transmission interface adopts RS232 agreement.
Preferably, in FPGA module and ARM module, be all connected with motor control module and I/O port module; Described FPGA module by the motor control module that connects on it with for shifting the motor of workpiece, be connected, FPGA module is connected with the sensor for detection of the location of workpiece by the I/O port module of connection on it;
The described I/O port module being connected with ARM module with FPGA module is exported as signal by MOSFET driving circuit, by high speed photo coupling, receives outer signals input; The described motor control module being connected with ARM module with FPGA module comprises pwm pulse speed governing output unit and encoder feedback input block two parts.
Preferably, described FPGA inside modules comprises serial ports transceiver module and arbitrated logic module, and wherein arbitrated logic module comprises frame status recognition machine, the comparer of tabling look-up, FIFO buffer area and UART change-over switch array; Wherein host computer serial ports is connected with the serial ports transceiver module of FPGA module, the serial ports transceiver module of FPGA module connects frame status recognition machine, frame status recognition machine is connected with UART change-over switch array by the comparer of tabling look-up, and frame status recognition machine is also connected with UART change-over switch array by FIFO buffer area and serial ports transceiver module; FPGA module is connected with each ARM module by UART change-over switch array;
In described FPGA module, dispose the State_Byte register of connected each ARM module, for the current state of each ARM module of tracing record.
The second object of the present invention is achieved through the following technical solutions: a kind of control method of the multiple operation device fabrication control device based on state machine, comprises the following steps:
S1, host computer send packet by serial ports to FPGA module, and FPGA receives and identifies packet;
S2, FPGA module receive packet from host computer serial ports, received packet is analyzed and processed, according to the packet receiving from host computer, corresponding ARM module is carried out to corresponding parameter setting, and control all ARM modules and reset;
S3, FPGA module are monitored state and the position of workpiece in multiple operation device fabrication of each ARM module, after in operation, workpiece puts in place and after ARM module resetted, start the ARM module of workpiece place operation, the work of the corresponding operation of ARM module controls by workpiece place operation;
S4, after certain procedure work completes, the ARM module of this procedure is to FPGA module transmission work settling signal, this procedure of notice FPGA module is finished the work;
S5, treat that FPGA module receives the work settling signal that current started each ARM module sends, control in multiple operation device fabrication for shifting the machine operation of workpiece, workpiece in a upper procedure is transferred in next process respectively, and supplemented workpiece to first operation; After workpiece transfer completes, ARM module automatically resets, and waits for startup next time, then gets back to step S3, completes the multiple operation production and processing of each workpiece.
The frame format of the packet that preferably, in described step S1, host computer sends to FPGA module is: comprise the data frame head of two bytes, the function of byte number, the length of byte, the data of the operation number of byte, length byte, the data postamble of the check code of byte and two bytes.
Further, in described step S2, FPGA module is as follows to receive packet post analysis and processing procedure from host computer:
The serial data bag of S2-1, host computer enters the serial ports transceiver module of FPGA inside modules after by MAX3232 level conversion, by serial ports transceiver module, the packet receiving is carried out to data recombination, and sends the frame status recognition machine of FPGA inside modules to;
S2-2, frame status recognition machine judge that whether the current packet receiving is effective; If so, leave the current packet receiving in FIFO buffer area;
S2-3, according to predetermined menu, the comparer of tabling look-up by FPGA inside modules carries out look-up table comparison to the function of the packet of FIFO buffer area number, the parameter setting function that will realize according to comparative result judgement packet;
S2-4, FPGA module find according to the operation number receiving data packet frame form from host computer the ARM module that will carry out parameter setting, then this ARM module are carried out to corresponding parameter setting.
Preferably, also comprise the following step that reports an error:
S6-1, when the corresponding operation of ARM module breaks down, produce an Error signal, to report an error to FPGA module; When the interface of FPGA module by itself and ARM collects Error signal, learn the sub-state machine of ARM module reporting an error, enter alarm condition;
S6-2, FPGA module collect after Error signal, from its with the interface of ARM module of reporting an error read the state number that reports an error of ARM state machine, by the sub-state plane No. of the ARM module reporting an error and the state that reports an error number by showing on fault display module; And suspend the operation of the ARM module reporting an error;
S6-3, user locate by the state plane No. showing on fault display module and the state number that reports an error operation and the corresponding actions breaking down, and the operation breaking down is carried out to malfunction elimination, after pending fault is eliminated, the fault recovery module connecting by FPGA module is to FPGA module transmitted signal;
S6-4, FPGA module receive after the signal of fault recovery module transmission, send reset signal to the ARM module reporting an error, and the ARM module that occurs reporting an error is resetted;
After S6-5, the ARM module reporting an error reset, send reset settling signal to FPGA module, FPGA module exits alarm condition.
The state of each ARM module that further, FPGA module is monitored comprises run mode, completes state, standing-by state and middle off-state; The signal of communicating by letter between FPGA module and each ARM module port comprises Vaild signal, Over signal, ARM module operating state signal, Error signal, RXD signal and TXD signal;
When in described step S3, FPGA module starts ARM module, FPGA module transmits Vaild signal to the ARM module being activated, and when ARM module listens to after Valid signal, enters run mode, controls the work of corresponding operation;
After in described step S4, certain procedure work completes, the ARM module of this procedure sends an Over signal to FPGA module, and ARM module has entered state, and the corresponding operation of ARM module controls quits work;
When in described step S3, FPGA module listens to each ARM module and resetted but do not had workpiece in corresponding operation, ARM module enters into standing-by state;
When in described step S6, ARM reports an error, FPGA collects Error signal; The FPGA module controls ARM module operation suspension that reports an error, ARM module enters interruption status;
In FPGA module, the State_Byte register standing-by state zone bit of ARM module sets high after system powers on back initial point or after workpiece transfer completes and while workpiece not detected in the corresponding operation of ARM module, receives zero clearing after the Vaild signal of FPGA module in this ARM module; When the State_Byte of ARM module register standing-by state zone bit sets high, this ARM module is standing-by state;
After the Vaild signal of the FPGA module that in FPGA module, the State_Byte register run mode zone bit of ARM module receives in this ARM module, set high zero clearing after this ARM module receives Over signal; When the State_Byte of ARM module register run mode zone bit sets high, this ARM module is run mode;
In FPGA module, the State_Byte register of ARM module is set high after completing the Over signal that state zone bit receives in this ARM module, zero clearing after the workpiece of the corresponding operation of this ARM module is transferred; When the State_Byte of ARM module register completes state zone bit and sets high, this ARM module is for completing state;
In FPGA module, the State_Byte register interrupts state zone bit of ARM module sets high when this ARM module sends Error signal to FPGA module or while receiving the hang-up instruction of RXD serial data, when the State_Byte of ARM module register interrupts state zone bit sets high, this ARM module is middle off-state.
The present invention has following advantage and effect with respect to prior art:
(1) in the present invention FPGA module as host state machine, the independent ARM module of controlling each operation work is as sub-state machine, the needs that FPGA module is produced according to processing apparatus are controlled corresponding ARM module and are started operation, thereby coordinate and manage the sub-state machine of each ARM module, the embedded scheme of carrying multi-disc ARM module by monolithic FPGA module realizes the control to multiple operation device fabrication, have advantages of that cost is low, during production run is controlled, required practical operation abstract package is state interface, reduced the degree of coupling of inter process, strengthened the system expandability, maintainability and independence, when customer demand is changed, can revise more easily and set up the sub-state machine of new process, have advantages of that extensibility is strong.FPGA module of the present invention after in operation being detected, workpiece puts in place and ARM module just open corresponding ARM module after having resetted, and complete after control work in all ARM modules that start, just workpiece is shifted, can guarantee that workpiece is orderly and processed accurately, avoid occurring the situations such as workpiece accumulation.
(2) the present invention adopts monolithic FPGA module as host state machine, multi-disc ARM module is as the double-deck state machine control structure of sub-state machine, and connect by star topology, while making device fabrication operation, when the makeing mistakes an of procedure wherein, can be in the situation that not affecting other operations operations, by FPGA host state machine, suspend and the operation of makeing mistakes that resets, strengthen stability and reliability that production run is controlled.
(3) reporting an error of ARM of the present invention, can know the operation that breaks down and the corresponding actions of operation, has the accurate advantage that reports an error.
Accompanying drawing explanation
Fig. 1 is the structure composition frame chart of control device of the present invention.
Fig. 2 is that the periphery of FPGA module in control device of the present invention connects block diagram.
Fig. 3 is that the periphery of each ARM module in control device of the present invention connects block diagram.
Fig. 4 is the interior serial ports transmitting-receiving of FPGA module and arbitrated logic module diagram in the present invention.
Fig. 5 be in the present invention the sub-state machine of ARM module when run mode, the sequential schematic diagram of communicating by letter of FPGA module and ARM module.
Fig. 6 is the sub-state machine of ARM module of the present invention while being out of order, the sequential schematic diagram of communicating by letter of FPGA module and ARM module.
Fig. 7 is FPGA module host state machine redirect schematic diagram in the present invention.
Fig. 8 is the sub-state machine redirect schematic diagram of injecting glue operation exemplary module.
Embodiment
Below in conjunction with embodiment and accompanying drawing, the present invention is described in further detail, but embodiments of the present invention are not limited to this.
Embodiment
As shown in Figure 1, the present embodiment discloses a kind of multiple operation device fabrication control device based on state machine, the FPGA module that comprise host computer PC, is connected with host computer and for controlling the ARM module of each procedure work; The ARM module that is used for controlling each procedure work is as sub-state machine, be connected with the FPGA module as host state machine respectively, form stelliform connection topology configuration with FPGA module, wherein in ARM module, comprise the logical operation of carrying out work for controlling corresponding operation, the wherein work of a procedure of independent control respectively of each ARM module; FPGA module with for shifting the motor of workpiece and being connected for detection of the sensor of the location of workpiece.Wherein the FPGA module in the present embodiment is the XC3S500 of SPARTAN-3E series, the STM32F103ZET8 of ARM module WeiST company.
As shown in Figure 2, the FPGA module of the present embodiment is connected with serial ports transceiver module, motor control module, fault display module, fault recovery module, I/O port module, interactive interface array module, basic power circuit, reset circuit, crystal oscillating circuit and configuration circuit.As shown in Figure 3, the ARM module of the present embodiment is connected with motor control module, I/O port module, interactive interface module, basic power circuit, reset circuit and crystal oscillating circuit.The motor control module that FPGA module is connected with ARM module comprises pwm pulse speed governing output unit and encoder feedback input block two parts.Wherein between motor control module and motor, pass through high speed photo coupling decoupling zero, by high speed photo coupling, FPGA module and motor are carried out the isolation of signal, avoid the impact of motor side signal on FPGA module.The I/O port module that FPGA module is connected with ARM module is exported as signal by MOSFET driving circuit, by high speed photo coupling, receive outer signals input, high speed photo coupling is isolated the signal of FPGA module and extraneous input, avoids the impact of extraneous input signal on FPGA module.The MOSFET pipe model adopting in the present embodiment is IRF540, and high speed photo coupling model is 6N137.
The motor control module of FPGA module connects for shifting the motor of workpiece by high speed photo coupling, controls the work of motor; FPGA module connects the sensor for detection of the location of workpiece by I/O port module, and the signal sending by the high speed photo coupling receiving sensor in I/O port module, to learn the position of workpiece.The present embodiment FPGA module and ARM module are also connected with the devices such as solenoid valve by the I/O port module on it in addition, and for controlling the work of corresponding pneumatic device, I/O port module passes through MOSFET driving circuit output signal in the devices such as solenoid valve.ARM module is connected with the motor in operation by motor control module, controls the corresponding actions in operation.
The connection fault display module of the present embodiment FPGA module, for showing the sub-state machine of ARM module that reports an error and the working procedure states number of fault, after the Failure elimination of operation, resets to the sub-state machine of fault by fault recovery module.Make FPGA module exit alarm condition.Fault display module in the present embodiment is two four eight sections of LED charactrons, and fault recovery module is finger-impu system.Certainly fault display module and the fault recovery module of the present embodiment also can directly realize by host computer.
The present embodiment FPGA module is connected with host computer by serial ports transceiver module, by serial ports transceiver module, receives the packet that host computer serial ports sends.It is as shown in table 1 that wherein host computer sends to the data packet frame form of FPGA module, comprise the data frame head of two bytes, the function of byte number, the length of byte, the data of the operation number of byte, length byte, the data postamble of the check code of byte and two bytes;
Table 1
| Data frame head | Function number | Length | Operation number | Data | Check code | Data postamble |
Between the present embodiment FPGA module and each ARM module, by interactive interface module, connect; Wherein the signal distributions of each interactive interface module is as shown in table 2;
Table 2
Known by upper table, Bit0, Bit1 and the Bit7 of each interactive interface array module of the present embodiment are control interfaces, transmit respectively Vaild signal, Over signal and Error signal; Bit2 to Bit6 is state interface, transmits the operating state signal of ARM module to FPGA module, and FPGA module, by the operating state signal of ARM module in interactive interface module, is known the state of the current operation of ARM; Bit8 and Bit9 are data transmission interface, and FPGA module can realize the setting to ARM module correlation parameter by data transmission interface.Bit0 to Bit7 corresponding interface adopts high speed optoelectronic isolated port to do parallel transmission, and described Bit8 and Bit9 data transmission interface adopt RS232 agreement to receive data, and serial ports main control chip model is MAX3232.
As shown in Figure 4, in the present embodiment, FPGA inside modules comprises serial ports transceiver module and arbitrated logic module, and arbitrated logic module comprises frame status recognition machine, the comparer of tabling look-up, FIFO buffer area and UART change-over switch array; Host computer serial ports is connected with the serial ports transceiver module of FPGA module, the serial ports transceiver module of FPGA module connects frame status recognition machine, frame status recognition machine is connected with UART change-over switch array by the comparer of tabling look-up, and frame status recognition machine is also connected with UART change-over switch array by FIFO buffer area and serial ports transceiver module; FPGA module is connected with each interactive interface module by UART change-over switch array; UART change-over switch array, according to the operation number in packet, finds the corresponding ARM module that will start, and to control respective switch closure, packet is sent to corresponding interactive interface module.Wherein FPGA inside modules serial ports transceiver module is RS232 protocol module.
In the FPGA module of the present embodiment, also dispose the State_Byte register of connected each ARM module, for the current state of each ARM module of tracing record.Wherein as shown in table 3, in the present embodiment, according to the working condition of each ARM module, be divided into standing-by state, run mode, complete state and middle off-state, State_Byte register comprises the zone bit of each state of ARM module, FPGA module judges the state of ARM module by the 1st to 4 bit flag positions of State_Byte register, the 1st bit flag position bit0 is run mode zone bit, the 2nd bit flag position bit1 is for completing state zone bit, the 3rd bit flag position bit2 is standing-by state zone bit, and the 4th bit flag position bit3 is middle off-state zone bit.Wherein the 5th of register the to the 8th bit flag position retains stand-by.When zone bit is 1, represent that this ARM module is for state corresponding to this zone bit.
Table 3
When ARM module is standing-by state, represent that this ARM module do not do any action, start waiting for; When ARM module is run mode, represent that ARM module is in the corresponding operation work of control; When ARM module is when completing state, represent that ARM module completes operation job control; When ARM module is middle off-state, represent that ARM module is interrupted current control work.
In the present embodiment, also disclose a kind of multiple operation device fabrication control method based on state machine, comprised the following steps:
S1, host computer send packet by serial ports to FPGA module, and FPGA receives and identifies packet; The frame format of the packet that host computer sends to FPGA module is as shown in table 1: comprise the data frame head of two bytes, the function of byte number, the length of byte, the data of the operation number of byte, length byte, the data postamble of the check code of byte and two bytes.
S2, FPGA module receive packet from host computer serial ports, received packet is analyzed and processed, according to the packet receiving from host computer, corresponding ARM module is carried out to corresponding parameter setting, and controlling all ARM modules resets, make each ARM module before operation is started working all in holding state, wherein in this step, FPGA module is as follows to receive packet post analysis and processing procedure from host computer:
The serial data bag of S2-1, host computer enters the RS232 protocol module of FPGA inside modules after by MAX3232 level conversion, by RS232 protocol module, the packet receiving is carried out to data recombination, and send the frame status recognition machine of FPGA inside modules to;
S2-2, frame status recognition machine judge that whether the current packet receiving is effective; If so, leave the current packet receiving in FIFO buffer area, otherwise just abandon;
For example to send to the packet of FPGA module be 0x40 0x40 0x01 0x020x03 0x04 0x05 0x0F 0x23 0x23 to the present embodiment host computer, and whether effectively detailed process is as follows for the data that in the present embodiment, the judgement of frame status recognition machine receives:
If S2-2-1, first if FPGA module serial ports sending and receiving end receives 0x40, when this frame head of 0x40 0x40, enter the data receiver stage of step S2-2-2, otherwise be considered as invalid data, abandon receiving, continue to wait for the arrival of frame head.
S2-2-2, after receiving data packet frame head, receive successively the function number (being 0x01) of 1 byte, the length (being 0x02) of a byte, the data of the operation number of a byte (being 0x03), length byte (learn that by length byte data length is 2, so receiving the data of two bytes (is 0x04, whether the check code that 0x05)) and the check code of a byte (being 0x0F), then relatively FPGA inside modules is calculated conforms to the check code receiving; If meet, continue to receive data postamble below, otherwise be considered as invalid data, the data that before received are all abandoned, and continue to wait for frame head.FPGA inside modules calculation check code in the following manner wherein: the low byte of function number, length markings, operation number and data summation SUM, i.e. check code=0x01+0x02+0x03+0x04+0x05=0x0F.
S2-2-3, after receiving frame head 0x40 0x40, interval after 1+1+1+Len+1 byte, will require to receive the postamble (being 0x23 0x23) of packet, if the postamble receiving is not 0x23 0x23, the data that receive before directly abandoning in this frame, are considered as invalid data.
Wherein above-mentioned steps all judges packet at reception frame head, verification and reception postamble three phases, to guarantee to receive active data.
S2-3, according to predetermined menu, the comparer of tabling look-up by FPGA inside modules carries out look-up table comparison to the function of the packet of FIFO buffer area number, the corresponding parameter setting function that will realize according to comparative result judgement packet; By the function number of packet, obtain the parameter setting function that packet is corresponding.
S2-4, FPGA module find according to the operation number receiving data packet frame form from host computer the ARM module that will carry out parameter setting, then this ARM module are carried out to corresponding parameter setting.The present embodiment has shown the ARM module of which operation to carry out parameter setting by the operation number in packet.
For example the function of certain packet number corresponding function is the setting of motor acceleration parameter, and operation number corresponds to the 3rd action of first operation,, by above-mentioned steps, the motor of the 3rd action of first operation is carried out to acceleration parameter setting.
S3, FPGA module is monitored state and the position of workpiece in multiple operation device fabrication of each ARM module, the sensor wherein connecting by FPGA module in the present embodiment detects the position of workpiece in multiple operation device fabrication, when FPGA module listens to after each ARM module has resetted and the position of workpiece in multiple operation device fabrication all puts in place, start the ARM module of workpiece place operation, as shown in Figure 5 simultaneously, FPGA module transmits high level Vaild signal to the ARM module being activated, when ARM module listens to after high level Valid signal, enter run mode, by the logical operation of workpiece place operation ARM inside modules, control the work of corresponding operation, in corresponding StateByte register, run mode zone bit sets high.When FPGA module listens to each ARM module and resetted but do not had workpiece in corresponding operation, ARM module enters into standing-by state in this step, and in corresponding StateByte register, standing-by state zone bit sets high;
S4, after certain procedure work completes, as shown in Figure 5, the ARM module of this procedure sends the high level pulse Over signal of 1 second to FPGA module, adopt Over signal as the work settling signal of ARM module, this procedure of notice FPGA module is finished the work, ARM module has entered state, and the corresponding operation of ARM module controls quits work, and completes state zone bit and set high in corresponding StateByte register.
S5, treat that FPGA module receives the work settling signal that current started each ARM module sends, the ARM module when all current startups has all entered state, the ARM module not being activated is all when standing-by state, in the device fabrication of FPGA module controls multiple operation for shifting the component working of workpiece, workpiece in a upper procedure is transferred to respectively in next process, the workpiece transfer of last procedure is taken in storehouse to workpiece, and supplement workpiece to first operation, after workpiece transfer completes, ARM module automatically resets and waits for startup next time; Then get back to step S3, complete the multiple operation production and processing of each workpiece.
When the multiple operation device fabrication control device of the present embodiment based on state machine is in control procedure, when operation breaks down, the present embodiment is controlled by the following method:
S6-1, when the corresponding operation of ARM module breaks down, can produce the high level pulse Error signal of 1 second, it is Error signal rising edge saltus step in interactive interface module, to report an error to FPGA module, when FPGA module collects the rising saltus step of Error signal, learn the ARM module reporting an error, enter alarm condition;
When S6-2, FPGA module collect Error signal, according to the information of Error signal, find the ARM module reporting an error, from its with the bit2～bit6 of interactive interface module State of the ARM module that reports an error read the state number that reports an error of ARM state machine, by the sub-state plane No. of the ARM module reporting an error and the state that reports an error number by showing on fault display module, as shown in table 4, the front two charactron of fault display module shows sub-state plane No., and rear six charactrons show the state number that reports an error; As shown in Figure 6, the Valid signal in interactive interface module is dragged down simultaneously, suspend the operation of the ARM module that reports an error, now, when the ARM module reporting an error wants to skip the current state that reports an error, while carrying out next operation, owing to listening to Valid signal, dragged down, and stoped.
Table 4
SEG0 to SEG7 represents respectively the demonstration in two four eight sections of LED charactrons in fault display module.
S6-3, user learn by the state plane No. showing on fault display module the operation breaking down, by the state of reporting an error number, draw out of order concrete action in operation, and the operation breaking down is carried out to malfunction elimination, after pending fault is eliminated, the fault recovery module of FPGA module connection is crossed to FPGA module transmitted signal in general family.
S6-4, FPGA module receive after the signal of fault recovery module transmission, send reset signal to the ARM module reporting an error, and the ARM module reporting an error is resetted.
After S6-5, the ARM module reporting an error reset, send the high level pulse Over signal of 1 second to FPGA module, FPGA module receives after Over signal, exits alarm condition.
From the foregoing, when the ARM module of the present embodiment method procedure reports an error, FPGA only suspends the work of this procedure, other operations still can continue normal work, when the fault of this procedure repaired before the current task of other operations completes, the production of processing apparatus will do not affected completely.
In the present embodiment, not only can to ARM module, carry out reset processing by FPGA module, also can control by host computer PC end the reset of corresponding ARM module, when the packet that receives host computer when FPGA module is reset instruction, FPGA module sends reset instruction to all ARM modules, each ARM module is carried out and resetted, and confirm that by the Over signal of interactive interface module each ARM module resets successfully.In the present embodiment, can be by time-out and the recovery of host computer PC end production control: when host computer PC end sends pause instruction, FPGA module receives and resolves after instruction, drag down all Valid signals in interactive interface array, because ARM module must check that in redirect and while carrying out next state Valid is that high level just can next step operation.When Valid being detected and be low level, all sub-state machines, in the middle of time delay circulation, recover instruction until PC sends, and when FPGA module is drawn high the Valid signal in interactive interface array, each sub-state machine could continue execution.
In the present embodiment, in FPGA module, the State_Byte register standing-by state zone bit of ARM module sets high after system powers on back initial point or after workpiece transfer completes and while workpiece not detected in the corresponding operation of ARM module, receives zero clearing after the high level Vaild signal of FPGA module in this ARM module; When the State_Byte of ARM module register standing-by state zone bit sets high, this ARM module is standing-by state.
After the high level Vaild signal of the FPGA module that in the present embodiment, in FPGA module, the State_Byte register run mode zone bit of ARM module receives in this ARM module, set high, in this ARM module, received zero clearing after the high level pulse Over signal of 1 second; When the State_Byte of ARM module register run mode zone bit sets high, this ARM module is run mode;
The State_Byte register of having implemented ARM module in FPGA module this year completes one that state zone bit receives in this ARM module and after high level pulse Over signal, is set high for 1 second, zero clearing after the workpiece of the corresponding operation of this ARM module is transferred; When the State_Byte of ARM module register completes state zone bit and sets high, this ARM module is for completing state;
In FPGA module, the State_Byte register interrupts state zone bit of ARM module sets high when this ARM module sends high level Error signal to FPGA module or while receiving the hang-up instruction of RXD serial data, when the State_Byte of ARM module register interrupts state zone bit sets high, this ARM module is middle off-state.
Known by said method, when the present embodiment workpiece transfer, each ARM module is that each state machine meets the following conditions, as shown in table 5:
Table 5
As can be seen from Table 5, when the present embodiment control device is under normal operation, in production work in earlier stage, not all sub-state machine was all activated, and along with the transfer of workpiece, the quantity that each sub-state machine starts increases with the relation of arithmetic progression at every turn; After certain multiple working procedure is finished the work, front m sub-state machine is in completing state, and rear N-m sub-state machine, when standing-by state, now can meet workpiece transfer condition, and FPGA module shifts workpiece under this condition.In the stationary phase of production run, all sub-state machines were all activated, and after certain multiple working procedure is finished the work, the individual sub-state machine of N all, when completing state, now can meet workpiece transfer condition, and FPAG module shifts workpiece under this condition.In the later stage of production run, workpiece no longer carries out supplementary period, after certain multiple working procedure is finished the work, front m sub-state machine is in standing-by state, rear N-m sub-state machine, when completing state, now can meet workpiece transfer condition, and FPGA module shifts workpiece under this condition.
Be illustrated in figure 7 the state of FPGA module in the present embodiment, when FPGA module has transmitted after all data, start to enter in the middle of host state machine operation.When host computer sends after enabled instruction, FPGA module enters run mode, and in the middle of run mode, FPGA module is by monitoring interactive interface array and IO port module, scheduling and each sub-state machine of start and stop.When each sub-state machine is after completing state, FPGA module enters transmitting state, and workpiece is shifted, and is about to workpiece and transfers to next process by motor control module.After transfer finishes, the state of again resuming operation.If while at this moment receiving the pause instruction that PC end sends, FPGA module is transferred to pending state from run mode, in off-state, until receive recovery instruction.Equally, at run mode, carry out in process, when a certain sub-state machine occurs reporting an error after signal, FPGA module enters warning state, shows fault, after troubleshooting, enters troubleshooting state malfunction machine is resetted, and after having resetted, state again puts into operation.
Be illustrated in figure 8 the present embodiment apparatus and method are applied to the constitutional diagram in the injecting glue operation of a high-power LED encapsulation equipment, when FPGA module sends after enabled instruction, the sub-state machine of corresponding ARM module is activated, first FPGA module is lifted to by LED substrate the position that this injecting glue operation is suitable by motor control module, and monitor the sensor signal in I/O port module, if now find, LED substrate cannot arrive assigned address, FPGA module enters warning state, and workpiece is put back to initial point; If not, jump to next state, start the sub-state machine of ARM module of injecting glue operation, by the sub-state machine of ARM module of this operation, control gum-filling mechanism and aim at LED encapsulation mouthful, after aligning, utilize the MOSFT pipe output control level of ARM module I/O port, opens solenoid valve, open gum-filling mechanism, by the sub-state machine starter motor fixed point of this operation screw extrusion injecting glue, after injecting glue completes, sub-state machine is controlled colloid-injecting gun and is returned initial point, LED substrate is got back on travelling belt initial point, waits for the workpiece transfer of FPGA module.
Above-described embodiment is preferably embodiment of the present invention; but embodiments of the present invention are not restricted to the described embodiments; other any do not deviate from change, the modification done under Spirit Essence of the present invention and principle, substitutes, combination, simplify; all should be equivalent substitute mode, within being included in protection scope of the present invention.
Claims (10)
1. the multiple operation device fabrication control device based on state machine, is characterized in that, the FPGA module that comprise host computer, is connected with host computer and for controlling the ARM module of each procedure work, the wherein wherein work of a procedure of each ARM module controls; Described for the ARM module of controlling each procedure work as sub-state machine, be connected with the FPGA module as host state machine respectively, form stelliform connection topology configuration with FPGA module; Described FPGA module connects for shifting the motor of workpiece and for detection of the sensor of the location of workpiece.
2. the multiple operation device fabrication control device based on state machine according to claim 1, it is characterized in that, described FPGA module is also connected with fault display module and fault recovery module, the fault that shows sub-state machine ARM module by fault display module, resets to the sub-state machine of fault by fault recovery module.
3. the multiple operation device fabrication control device based on state machine according to claim 1, it is characterized in that, described FPGA module is connected with a plurality of interactive interface array modules, by each interactive interface array module, be connected with each ARM module, wherein each interactive interface array module comprises control interface, state interface and data transmission interface; Described control interface and state interface adopt high speed photo coupling to do parallel transmission, and described data transmission interface adopts RS232 agreement.
4. the multiple operation device fabrication control device based on state machine according to claim 1, is characterized in that, is all connected with motor control module and I/O port module in FPGA module and ARM module; Described FPGA module by the motor control module that connects on it with for shifting the motor of workpiece, be connected, FPGA module is connected with the sensor for detection of the location of workpiece by the I/O port module of connection on it;
The described I/O port module being connected with ARM module with FPGA module is exported as signal by MOSFET driving circuit, by high speed photo coupling, receives outer signals input; The described motor control module being connected with ARM module with FPGA module comprises pwm pulse speed governing output unit and encoder feedback input block two parts.
5. the multiple operation device fabrication control device based on state machine according to claim 1, it is characterized in that, described FPGA inside modules comprises serial ports transceiver module and arbitrated logic module, and wherein arbitrated logic module comprises frame status recognition machine, the comparer of tabling look-up, FIFO buffer area and UART change-over switch array; Wherein host computer serial ports is connected with the serial ports transceiver module of FPGA module, the serial ports transceiver module of FPGA module connects frame status recognition machine, frame status recognition machine is connected with UART change-over switch array by the comparer of tabling look-up, and frame status recognition machine is also connected with UART change-over switch array by FIFO buffer area and serial ports transceiver module; FPGA module is connected with each ARM module by UART change-over switch array;
In described FPGA module, dispose the State_Byte register of connected each ARM module, for the current state of each ARM module of tracing record.
6. the control method based on the multiple operation device fabrication control device based on state machine claimed in claim 1, is characterized in that, comprises the following steps:
S1, host computer send packet by serial ports to FPGA module, and FPGA receives and identifies packet;
S2, FPGA module receive packet from host computer serial ports, received packet is analyzed and processed, according to the packet receiving from host computer, corresponding ARM module is carried out to corresponding parameter setting, and control all ARM modules and reset;
S3, FPGA module are monitored state and the position of workpiece in multiple operation device fabrication of each ARM module, after in operation, workpiece puts in place and after ARM module resetted, start the ARM module of workpiece place operation, the work of the corresponding operation of ARM module controls by workpiece place operation;
S4, after certain procedure work completes, the ARM module of this procedure is to FPGA module transmission work settling signal, this procedure of notice FPGA module is finished the work;
S5, treat that FPGA module receives the work settling signal that current started each ARM module sends, control in multiple operation device fabrication for shifting the machine operation of workpiece, workpiece in a upper procedure is transferred in next process respectively, and supplemented workpiece to first operation; After workpiece transfer completes, ARM module automatically resets, and waits for startup next time, then gets back to step S3, completes the multiple operation production and processing of each workpiece.
7. the multiple operation device fabrication control method based on state machine according to claim 6, it is characterized in that, the frame format of the packet that in described step S1, host computer sends to FPGA module is: comprise the data frame head of two bytes, the function of byte number, the length of byte, the data of the operation number of byte, length byte, the data postamble of the check code of byte and two bytes.
8. the multiple operation device fabrication control method based on state machine according to claim 7, is characterized in that, in described step S2, FPGA module is as follows to receive packet post analysis and processing procedure from host computer:
The serial data bag of S2-1, host computer enters the serial ports transceiver module of FPGA inside modules, by serial ports transceiver module, the packet receiving is carried out to data recombination, and sends the frame status recognition machine of FPGA inside modules to;
S2-2, frame status recognition machine judge that whether the current packet receiving is effective; If so, leave the current packet receiving in FIFO buffer area;
S2-3, according to predetermined menu, the comparer of tabling look-up by FPGA inside modules carries out look-up table comparison to the function of the packet of FIFO buffer area number, the parameter setting function that will realize according to comparative result judgement packet;
S2-4, FPGA module find according to the operation number receiving data packet frame form from host computer the ARM module that will carry out parameter setting, then this ARM module are carried out to corresponding parameter setting.
9. the multiple operation device fabrication control method based on state machine according to claim 6, is characterized in that, further comprising the steps of:
S6-1, when the corresponding operation of ARM module breaks down, produce an Error signal, to report an error to FPGA module; When the interface of FPGA module by itself and ARM collects Error signal, learn the sub-state machine of ARM module reporting an error, enter alarm condition;
S6-2, FPGA module collect after Error signal, from its with the interface of ARM module of reporting an error read the state number that reports an error of ARM state machine, by the sub-state plane No. of the ARM module reporting an error and the state that reports an error number by showing on fault display module; And suspend the operation of the ARM module reporting an error;
S6-3, user locate by the state plane No. showing on fault display module and the state number that reports an error operation and the corresponding actions breaking down, and the operation breaking down is carried out to malfunction elimination, after pending fault is eliminated, the fault recovery module connecting by FPGA module is to FPGA module transmitted signal;
S6-4, FPGA module receive after the signal of fault recovery module transmission, send reset signal to the ARM module reporting an error, and the ARM module that occurs reporting an error is resetted;
After S6-5, the ARM module reporting an error reset, send reset settling signal to FPGA module, FPGA module exits alarm condition.
10. the multiple operation device fabrication control method based on state machine according to claim 9, is characterized in that, the state of each ARM module that FPGA module is monitored comprises run mode, completes state, standing-by state and middle off-state; The signal of communicating by letter between FPGA module and each ARM module port comprises Vaild signal, Over signal, ARM module operating state signal, Error signal, RXD signal and TXD signal;
When in described step S3, FPGA module starts ARM module, FPGA module transmits Vaild signal to the ARM module being activated, and when ARM module listens to after Valid signal, enters run mode, controls the work of corresponding operation;
After in described step S4, certain procedure work completes, the ARM module of this procedure sends an Over signal to FPGA module, and ARM module has entered state, and the corresponding operation of ARM module controls quits work;
When in described step S3, FPGA module listens to each ARM module and resetted but do not had workpiece in corresponding operation, ARM module enters into standing-by state;
When in described step S6, ARM reports an error, FPGA collects Error signal; The FPGA module controls ARM module operation suspension that reports an error, ARM module enters interruption status;
In FPGA module, the State_Byte register standing-by state zone bit of ARM module sets high after system powers on back initial point or after workpiece transfer completes and while workpiece not detected in the corresponding operation of ARM module, receives zero clearing after the Vaild signal of FPGA module in this ARM module; When the State_Byte of ARM module register standing-by state zone bit sets high, this ARM module is standing-by state;
After the Vaild signal of the FPGA module that in FPGA module, the State_Byte register run mode zone bit of ARM module receives in this ARM module, set high zero clearing after this ARM module receives Over signal; When the State_Byte of ARM module register run mode zone bit sets high, this ARM module is run mode;
In FPGA module, the State_Byte register of ARM module is set high after completing the Over signal that state zone bit receives in this ARM module, zero clearing after the workpiece of the corresponding operation of this ARM module is transferred; When the State_Byte of ARM module register completes state zone bit and sets high, this ARM module is for completing state;
In FPGA module, the State_Byte register interrupts state zone bit of ARM module sets high when this ARM module sends Error signal to FPGA module or while receiving the hang-up instruction of RXD serial data, when the State_Byte of ARM module register interrupts state zone bit sets high, this ARM module is middle off-state.
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