CN104133346A - Real-time focusing detection and adjustment method suitable for projection photoetching machine - Google Patents

Abstract

The invention provides a real-time focusing detection and adjustment method suitable for a projection photoetching machine. The method comprises the steps of allowing a light source (1) to become a parallel beam by a collimating lens and to become a slit by a projection diaphragm (3), imaging the slit on the surface of a silicon wafer (6) by an imaging lens (4), imaging a beam reflected from the surface of the silicon wafer on a linear array CCD (Charge Coupled Device) (13) by imaging lenses (10 and 11), allowing a workpiece table (7) to carry the silicon wafer (6) by a vacuum chuck (8) to move up and down in a Z direction, allowing a slit image to generate delta X displacement on the linear array CCD (13) by delta Z displacement on the surface of the silicon wafer, allowing the linear array CCD to transmit image information to an image acquisition control card (15) by a Cameralink transmission line (14), allowing the image processing acquisition card (15) to perform sub pixel processing on the image information, computing the defocusing amount, controlling motion of the workpiece table, and detecting the defocusing amount in real time until the defocusing amount meets an accuracy requirement. The image acquisition control card (15) is communicated with a computer (17) by an RS232 (Recommend Standard 232) serial port (16), so that initial setting and debugging can be performed.

Description

A kind of real-time focusing test focus adjustment method that is applicable to projection mask aligner

Technical field

The present invention relates to the CCD focusing test technology in projection lithography apparatus field, is specifically related to a kind of real-time focusing test focus adjustment method that is applicable to projection mask aligner, and application the method is controlled work stage motion and adjusted defocusing amount, can realize real-time high-precision automatic focusing.

Background technology

Projection mask aligner is the main flow equipment that large scale integrated circuit is produced, and the figure on mask plate can be projected on silicon chip by a certain percentage by imaging exposure device.By Rayleigh equation R=k ₁λ/NA and depth of focus formula DOF=k ₂λ/NA ²can know, the raising of resolving power can be by increasing numerical aperture of objective NA and shortening exposure wavelength lambda and realize, and depth of focus DOF will reduce like this, and particularly the increase of NA will cause sharply reducing of DOF.If actual focal does not reach the desired depth of focus tolerance limit of photoetching technique technique, the yield rate of exposure lines quality and integrated circuit production will be had a strong impact on.Accurately focusing test focusing is drive on boldly and is played a crucial role to high resolution more projection lithography technology.

Three indexs of evaluating litho machine performance are resolving power, alignment precision and production efficiency.The real-time of focusing test focusing is by the final production efficiency of impact.Current focusing test focus adjustment method mostly is photoelectric measurement method, all needs to use image processing method.And existing image processing algorithm operates in non-real time operating system mostly on personal computer, by instruction serial, carry out.

Summary of the invention

In view of this, the invention provides a kind of real-time focusing test focus adjustment method that is applicable to projection mask aligner, can accurately locate in a short period of time position of silicon wafer, and control work stage and complete focusing.

For achieving the above object, a kind of real-time focusing test focus adjustment method that is applicable to projection mask aligner of the present invention, comprises that step is as follows:

Step (1), light source 1 become parallel beam through collimation lens, through catoptron 2, are irradiated to projection diaphragm 3.Parallel beam becomes one slit beam after projection diaphragm 3, through image-forming objective lens group 4 and catoptron 5, with larger incident angle (90-γ), is imaged on silicon chip surface 6.Slit beam from silicon chip surface 6 reflections, through catoptron 9, by imaging lens group 10,11, then passes through catoptron 12, is imaged on line array CCD 13;

Step (2), line array CCD 13 are passed to image acquisition control card 15 by Cameralink transmission line 14 by image information.Image acquisition control card carries out sub-pix processing to image, obtains the center of slit image, according to default optimal focal plane position calculation, goes out defocusing amount.

Step (3), image acquisition control card 15, according to defocusing amount, are controlled Z direction motor rotation direction and the speed of work stage 7.Vacuum cup 8 holds silicon chip 6, is carried the movement of doing vertical Z direction by work stage 7.The displacement that produces Δ Z in Z direction will make the picture of slit beam on linear array CCD13, produce the displacement of Δ X, thereby changes defocusing amount, until defocusing amount meets accuracy requirement.

Wherein, described line array CCD 13 adopts high sensitivity low noise black and white line scanning ccd sensor, there are 2048 valid pixels, Pixel Dimensions 14 μ m * 14 μ m, carry AD, have the configurable output data precision of 8bit/10bit/12bit, 16 high precision arrange integral time, there is improved camera configuration serial communication protocol, the maximum data rate 25MHz, highest line is 11.7KHz frequently;

Wherein, described image acquisition control card 15 comprises CPU module 201, Cameralink interface 202, LVDS to28bit module 203, SRAM module 204, reseting module 205, serial port module 206, motor drive module 207, display module 208, optoelectronic switch module 209, preset value module 210, JTAG configuration module 211, communication module 212, power module 213, clock module 214;

Wherein, described CPU module 201 adopts FPGA to realize, and utilizes the high-speed parallel of FPGA, improves the real-time of whole focusing test focusing.Described Cameralink interface 202 adopts the MDR26 interface of standard; Between Cameralink interface and LVDS to28bit203 and communication module 212, by differential lines, be connected, video image information is transferred to LVDS to28bit203 with 5 tunnel serial low-voltage differential signals (LVDS), owing to only having used the Base pattern of Cameralink agreement, only export 8 bit parallel signals, 1 row is synchronous and 1 cameralink clock signal to CPU module; Simultaneously, communication module 212 is comprised of a LVDS Driver/Receiver and 4 tunnel differential lines drivers, LVDS Driver/Receiver is responsible for the serial order transmitting-receiving between FPGA and Cameralink, and 4 tunnel differential lines drivers are responsible for the camera control signal of 4 road FPGA to convert low-voltage differential signal to Camerlink.

Wherein, described preset value module 210 is comprised of 11 toggle switchs, and FPGA is read as 11 2 system numbers of 0～2047, as the calibration value of optimal focal plane; Whether described optoelectronic switch module 209 has arrived range in Z direction for detection of silicon chip, if it is allows motor stop in time or antiport; Two 47 segment numeral pipes of display module 208 use form, and show respectively optimal focal plane calibration value and current silicon face position;

Wherein, the image processing algorithm adopting.First the imagery exploitation gradient operator through gaussian filtering is obtained to its corresponding gradient image; Then try to achieve gradient maximum value and be the marginal point of image, then carry out quadratic interpolation near putting by edge, try to achieve the position, image edge of sub-pixel, finally go its mean value to be the center of slit bright rays.

The beneficial effect that the present invention has is:

1), the present invention makes full use of the high-speed parallel of FPGA, effectively raise the real-time of focusing test focusing, thereby enhance productivity.

2), the image acquisition control card that adopts of the present invention can carry Presentation Function, after debug checking, can be independent of personal computer completely and carry out focusing test focusing, thus minimizing litho machine complete machine cost.

3), image processing algorithm of the present invention after gaussian filtering, by the method for gradient image segmentation, carry out edge detection, finally try to achieve slit image center, there is the resolution of sub-pix, can accurately locate.

Accompanying drawing explanation

Fig. 1 is a kind of real-time focusing test focus adjustment method focusing test schematic diagram that is applicable to projection mask aligner of the present invention.

Fig. 2 is image acquisition control card block diagram.

Fig. 3 is image processing algorithm FB(flow block).

Embodiment

For making the object, technical solutions and advantages of the present invention clearer and more definite, below in conjunction with accompanying drawing, be further described.

A real-time focusing test focus adjustment method that is applicable to projection mask aligner, concrete steps are as follows:

Step (1), light source 1 become parallel beam through collimation lens, through catoptron 2, are irradiated to projection diaphragm 3.Parallel beam becomes one slit beam after projection diaphragm 3, through image-forming objective lens group 4 and catoptron 5, with larger incident angle (90-γ), is imaged on silicon chip surface 6.Slit beam from silicon chip surface 6 reflections, through catoptron 9, by imaging lens group 10,11, then passes through catoptron 12, is imaged on line array CCD 13; Wherein, described line array CCD 13 adopts high sensitivity low noise black and white line scanning ccd sensor, there are 2048 valid pixels, Pixel Dimensions 14 μ m * 14 μ m, carry AD, have the configurable output data precision of 8bit/10bit/12bit, 16 high precision arrange integral time, there is improved camera configuration serial communication protocol, the maximum data rate 25MHz, highest line is 11.7KHz frequently.

Step (2), line array CCD 13 are passed to image acquisition control card 15 by Cameralink transmission line 14 by image information.Image acquisition control card carries out sub-pix processing to image, obtains the center of slit image, according to default optimal focal plane position calculation, goes out defocusing amount.Wherein, described image acquisition control card 15 comprises CPU module 201, Cameralink interface 202, LVDS to28bit module 203, SRAM module 204, reseting module 205, serial port module 206, motor drive module 207, display module 208, optoelectronic switch module 209, preset value module 210, JTAG configuration module 211, communication module 212, power module 213, clock module 214; Wherein, described CPU module 201 adopts FPGA to realize, and utilizes the high-speed parallel of FPGA, improves the real-time of whole focusing test focusing.Described Cameralink interface 202 adopts the MDR26 interface of standard; Between Cameralink interface and LVDS to28bit203 and communication module 212, by differential lines, be connected, video image information is transferred to LVDS to28bit203 with 5 tunnel serial low-voltage differential signals (LVDS), owing to only having used the Base pattern of Cameralink agreement, only export 8 bit parallel signals, 1 row is synchronous and 1 cameralink clock signal to CPU module; Simultaneously, communication module 212 is comprised of a LVDS Driver/Receiver and 4 tunnel differential lines drivers, LVDS Driver/Receiver is responsible for the serial order transmitting-receiving between FPGA and Cameralink, and 4 tunnel differential lines drivers are responsible for the camera control signal of 4 road FPGA to convert low-voltage differential signal to Camerlink.Wherein, described preset value module 210 is comprised of 11 toggle switchs, and FPGA is read as 11 2 system numbers of 0～2047, as the calibration value of optimal focal plane; Whether described optoelectronic switch module 209 has arrived range in Z direction for detection of silicon chip, if it is allows motor stop in time or antiport; Two 47 segment numeral pipes of display module 208 use form, and show respectively optimal focal plane calibration value and current silicon face position.

Step (3), image acquisition control card 15, according to defocusing amount, are controlled Z direction motor rotation direction and the speed of work stage 7.Vacuum cup 8 holds silicon chip 6, is carried the movement of doing vertical Z direction by work stage 7.The displacement that produces Δ Z in Z direction will make the picture of slit beam on linear array CCD13, produce the displacement of Δ X, thereby changes defocusing amount, until defocusing amount meets accuracy requirement.Wherein, the image processing algorithm adopting.First the imagery exploitation gradient operator through gaussian filtering is obtained to its corresponding gradient image; Then try to achieve gradient maximum value and be the marginal point of image, then carry out quadratic interpolation near putting by edge, try to achieve the position, image edge of sub-pixel, finally go its mean value to be the center of slit bright rays.

Fig. 1 is the schematic diagram that utilizes line array CCD to carry out focusing test focusing, and the pass that can obtain between true defocusing amount Δ Z and image displacement Δ X according to Fig. 1 is:

ΔX＝2aΔZcosγ (1)

The imaging system enlargement ratio that imaging lens group 10,11 forms can be accomplished a=20 doubly, the pel spacing d=14 μ m of line array CCD, and total number of pixels n=2048, γ=15 °, the CCD pixel-shift amount that above-mentioned defocusing amount Δ Z is corresponding is:

$\mathrm{\Δn}=\frac{2\mathrm{a\Δ}Z\cos \mathrm{\γ}}{d}=2.76\mathrm{\ΔZ}---\left(2\right)$

As long as than 1 resolution that pixel is high, just can obtain the location resolving power of sub-micron.

Fundamental purpose of the present invention, in order to improve the real-time of focusing test focusing, can be worked from hardware and algorithm two aspects.Fig. 2 is the structured flowchart of image acquisition control card 15.The present invention adopts line array CCD as imageing sensor, has at a high speed, cheaply advantage compared with area array CCD.Between image acquisition control card and line array CCD, by standard C ameralink interface, be connected, adopt difference wiring transmission LVDS signal.Consider image algorithm uncomplicated, FPGA can have the function of image acquisition and processing concurrently, and because FPGA is from being in essence hardware realization, its high-speed parallel has improved the speed of image acquisition and processing greatly, and reduced image transmitting link, be equipped with high-speed SRAM, can make the present invention there is good real-time, improve photoetching production efficiency.

For image processing algorithm, adopt the Subpixel edge detection algorithm based on polynomial interpolation, ask two edges mid point as slit image mid point, its process flow diagram as shown in Figure 3, can be divided into following steps:

Step S1: gather image information with line array CCD, send image acquisition control card to by Cameralink transmission line.

Step S2: with Gaussian filter, gradation of image information is carried out to low-pass filtering, reduce the impact that noise edge detects.

Step S3: ask gradient image maximum value, find edge pixel.If entered the gradation of image function of gaussian filtering, be f (i), wherein, i=0,1,2 ... 2047.Then f (i) is asked to gradient, gradient image R (i)=| f (i+1)-f (i) |, i=0,1 ..., 2046, when meeting:

R(i)≥R(i+1)＞R(i+2) (3)

R(i)≥R(i-1)＞R(i-2) (4)

E (i)=R (i), otherwise E (i)=0.Get two maximum position i of E (i), j is as pixel level marginal point.

Step S4: at i, 3 quadratic polynomial interpolation are carried out to gradient image in j position.Gradient image R (i) is got to 3 R (i), R (i-1), R (i+1) is as interpolation point.Quadratic interpolation function can be expressed as:

$P\left(x\right)=\frac{(x-x_1)(x-x_2)}{(x_0-x_1)(x_0-x_2)}R(i-1)+\frac{(x-x_0)(x-x_2)}{(x_1-x_0)(x_1-x_2)}R\left(i\right)+\frac{(x-x_0)(x-x_1)}{(x_2-x_0)(x_2-x_1)}R(i+1)---\left(5\right)$

Wherein, x ₀=i-d, x ₁=i, x ₂=i+d, d is line array CCD pixel spacing.

Step S5: to P (x) differentiate, and to make derivative be 0, can obtain:

${\mathrm{edge}}_i=i+\frac{R(i-1)-R(i+1)}{R(i-1)-2R\left(i\right)+R(i+1)}\·\frac{d}{2}---\left(6\right)$

In like manner can be in the hope of edge corresponding to j point _j, both mid points and calibration point n ₀difference be defocusing amount:

$\mathrm{\Δn}=n_0-\frac{{\mathrm{edge}}_i+{\mathrm{edge}}_j}{2}---\left(7\right)$

Step S6: judge whether defocusing amount meets photoetching index, satisfied finish focusing, otherwise control work stage towards the direction motion that reduces defocusing amount, and get back to step S1, continue focusing test.

The content that the present invention does not elaborate adopts the known technology of this area.

Although above the illustrative embodiment of the present invention is described; so that the technician of this technology neck understands the present invention; but should be clear; the invention is not restricted to the scope of embodiment; to those skilled in the art; as long as various variations appended claim limit and definite the spirit and scope of the present invention in, these variations are apparent, all utilize innovation and creation that the present invention conceives all at the row of protection.

Claims (6)

1. a real-time focusing test focus adjustment method that is applicable to projection mask aligner, is characterized in that step is as follows:

Step (1), light source (1) become parallel beam through collimation lens, through catoptron (2), be irradiated to projection diaphragm (3), parallel beam becomes slit beam one after projection diaphragm (3), through image-forming objective lens group (4) and catoptron (5), with larger incident angle (90-γ), be imaged on silicon chip surface (6), slit beam from silicon chip surface (6) reflection, through catoptron (9), by imaging lens group (10,11), pass through again catoptron (12), be imaged on line array CCD (13);

Step (2), line array CCD (13) are passed to image acquisition control card (15) by Cameralink transmission line (14) by image information, image acquisition control card carries out sub-pix processing to image, obtain the center of slit image, according to default optimal focal plane position calculation, go out defocusing amount;

Step (3), image acquisition control card (15) are according to defocusing amount, control work stage (7) Z direction motor rotation direction and speed, vacuum cup (8) holds silicon chip (6), by work stage (7), carry the movement of doing vertical Z direction, the displacement that produces Δ Z in Z direction will make the picture of slit beam in the upper displacement that produces Δ X of line array CCD (13), thereby change defocusing amount, until defocusing amount meets accuracy requirement.

2. be applicable to according to claim 1 the real-time focusing test focus adjustment method of projection mask aligner, it is characterized in that described line array CCD (13) adopts high sensitivity low noise black and white line scanning ccd sensor, there are 2048 valid pixels, Pixel Dimensions 14 μ m * 14 μ m, carry AD, have the configurable output data precision of 8bit/10bit/12bit, 16 high precision arrange integral time, there is improved camera configuration serial communication protocol, the maximum data rate 25MHz, highest line is 11.7KHz frequently.

3. be applicable to according to claim 1 the real-time focusing test focus adjustment method of projection mask aligner, it is characterized in that described image acquisition control card (15) comprises CPU module (201), Cameralink interface (202), LVDS to28bit module (203), SRAM module (204), reseting module (205), serial port module (206), motor drive module (207), display module (208), optoelectronic switch module (209), preset value module (210), JTAG configuration module (211), communication module (212), power module (213), clock module (214).

4. according to the real-time focusing test focus adjustment method that is applicable to projection mask aligner described in claim 1 or 3, it is characterized in that described CPU module (201) adopts FPGA to realize, utilize the high-speed parallel of FPGA, the real-time that improves whole focusing test focusing, described Cameralink interface (202) adopts the MDR26 interface of standard; Between Cameralink interface and LVDS to28bit (203) and communication module (212), by differential lines, be connected, video image information is transferred to LVDS to28bit (203) with 5 tunnel serial low-voltage differential signals (LVDS), owing to only having used the Base pattern of Cameralink agreement, only export 8 bit parallel signals, 1 row is synchronous and 1 cameralink clock signal to CPU module; Simultaneously, communication module (212) is comprised of a LVDS Driver/Receiver and 4 tunnel differential lines drivers, LVDS Driver/Receiver is responsible for the serial order transmitting-receiving between FPGA and Cameralink, and 4 tunnel differential lines drivers are responsible for the camera control signal of 4 road FPGA to convert low-voltage differential signal to Camerlink.

5. according to the real-time focusing test focus adjustment method that is applicable to projection mask aligner described in claim 1 or 3, it is characterized in that described preset value module (210) is comprised of 11 toggle switchs, FPGA is read as 11 2 system numbers of 0～2047, as the calibration value of optimal focal plane; Whether described optoelectronic switch module (209) has arrived range in Z direction for detection of silicon chip, if it is allows motor stop in time or antiport; Display module (208) forms with two 47 segment numeral pipes, shows respectively optimal focal plane calibration value and current silicon face position.

6. according to the real-time focusing test focus adjustment method that is applicable to projection mask aligner described in claim 1 or 3, it is characterized in that adopted image processing algorithm, first the imagery exploitation gradient operator through gaussian filtering is obtained to its corresponding gradient image; Then try to achieve gradient maximum value and be the marginal point of image, then carry out quadratic interpolation near putting by edge, try to achieve the position, image edge of sub-pixel, finally go its mean value to be the center of slit bright rays.