CN104124160B - Method, semi-conductor device manufacturing method - Google Patents
Method, semi-conductor device manufacturing method Download PDFInfo
- Publication number
- CN104124160B CN104124160B CN201310143802.3A CN201310143802A CN104124160B CN 104124160 B CN104124160 B CN 104124160B CN 201310143802 A CN201310143802 A CN 201310143802A CN 104124160 B CN104124160 B CN 104124160B
- Authority
- CN
- China
- Prior art keywords
- ring
- type
- communicated
- semi
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 238000002955 isolation Methods 0.000 claims abstract description 13
- 238000010586 diagram Methods 0.000 claims abstract description 7
- 238000005516 engineering process Methods 0.000 claims abstract description 6
- 230000007704 transition Effects 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 77
- 239000000463 material Substances 0.000 claims description 44
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 11
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 11
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 11
- 238000001259 photo etching Methods 0.000 claims description 9
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 238000011049 filling Methods 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims 1
- 241000555293 Bassariscus astutus Species 0.000 abstract description 3
- 230000011218 segmentation Effects 0.000 abstract description 3
- 125000004122 cyclic group Chemical group 0.000 description 21
- 229910052751 metal Inorganic materials 0.000 description 16
- 239000002184 metal Substances 0.000 description 16
- 230000008569 process Effects 0.000 description 9
- 230000008020 evaporation Effects 0.000 description 8
- 238000001704 evaporation Methods 0.000 description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 8
- 238000004528 spin coating Methods 0.000 description 8
- 238000004544 sputter deposition Methods 0.000 description 8
- 239000000126 substance Substances 0.000 description 8
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 238000000231 atomic layer deposition Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 6
- 238000001451 molecular beam epitaxy Methods 0.000 description 6
- 125000006850 spacer group Chemical group 0.000 description 6
- 239000011435 rock Substances 0.000 description 5
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 229910021419 crystalline silicon Inorganic materials 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- 229910052735 hafnium Inorganic materials 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 239000005360 phosphosilicate glass Substances 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000012212 insulator Substances 0.000 description 3
- 229910001092 metal group alloy Inorganic materials 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 229910002244 LaAlO3 Inorganic materials 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 229910052593 corundum Inorganic materials 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 2
- 125000004430 oxygen atom Chemical group O* 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052761 rare earth metal Inorganic materials 0.000 description 2
- 150000002910 rare earth metals Chemical class 0.000 description 2
- 229910052715 tantalum Inorganic materials 0.000 description 2
- 229910001845 yogo sapphire Inorganic materials 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- 229910052693 Europium Inorganic materials 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910005898 GeSn Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910016285 MxNy Inorganic materials 0.000 description 1
- 229910016310 MxSiy Inorganic materials 0.000 description 1
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910020328 SiSn Inorganic materials 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- TZHYBRCGYCPGBQ-UHFFFAOYSA-N [B].[N] Chemical compound [B].[N] TZHYBRCGYCPGBQ-UHFFFAOYSA-N 0.000 description 1
- CKUAXEQHGKSLHN-UHFFFAOYSA-N [C].[N] Chemical compound [C].[N] CKUAXEQHGKSLHN-UHFFFAOYSA-N 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 150000001335 aliphatic alkanes Chemical class 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 125000003118 aryl group Chemical group 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000002041 carbon nanotube Substances 0.000 description 1
- 229910021393 carbon nanotube Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000006392 deoxygenation reaction Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000007687 exposure technique Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000002070 nanowire Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000011253 protective coating Substances 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 238000000101 transmission high energy electron diffraction Methods 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
Abstract
Ring-type or other attachment structures communicated and groove are formed by side wall transition diagram technology on substrate the invention discloses a kind of；Shallow trench isolation is formed between ring-type or other attachment structures communicated；False grid lines are formed on substrate, cover multiple separate fin channel areas of ring-type or other attachment structures communicated, thus separate influence of the fin structure to different components that be connected.Method, semi-conductor device manufacturing method according to the present invention, ultra-fine silicon fin is formed using side wall transition diagram, while forms raceway groove ring in the plane, false grid are formed on ring tail or other positions, thus automatic segmentation forms different raceway grooves, simplifies technique, improves the device accuracy of manufacture.
Description
Technical field
The present invention relates to a kind of semiconductor devices and its manufacture method, more particularly to a kind of energy simple and efficient cutting isolation
Three-dimensional multi-gate FinFET manufacture method.
Background technology
In current sub- 20nm technologies, three-dimensional multi-gate device（FinFET or Tri-gate）It is main device architecture,
This structure enhances grid control ability, inhibits electric leakage and short-channel effect.
For example, the MOSFET of double gate SOI structure can suppress short compared with traditional single grid body Si or SOI MOSFET
Channelling effect（SCE）And leakage causes induced barrier to reduce（DIBL）Effect, there is lower junction capacity, can realize that raceway groove is gently mixed
It is miscellaneous, it can obtain about 2 times of driving current by setting the work function of metal gates come adjusting threshold voltage, reduce
For effective gate oxide thickness（EOT）Requirement.And tri-gate devices are compared with double-gated devices, grid enclose channel region top surface and
Two sides, grid control ability are stronger.Further, loopful is more advantageous around nano wire multi-gate device.
Existing FinFET structure and manufacture method generally employ the secondary figure exposure technique of autoregistration（SADP）, bag
Include：Hard mask layer and sacrifice layer and graphical are formed on body Si or SOI substrate, ring-type is formed in sacrifice layer side periphery
（Generally rectangular frame）The first side wall, remove sacrifice layer, the first side wall of ring-type left on substrate；Spin coating photoresist layer,
The first side wall core is covered, the afterbody of ring-type side wall is only exposed, in order to cut fin；Using photoresist layer as mask, carve
Etching off is except the side wall afterbody of exposure, so as to leave the multiple side wall lines extended in a first direction on substrate；With side wall lines
For mask, etched substrate forms fin and groove.Hereafter, filling is dielectrically separated from medium and forms shallow trench isolation in the trench, and
Doping forms source-drain area in fin, and gate stack is formed across fin.
The process of the above-mentioned multiple fins of composition is required to corresponding photoresist at least once when forming each fin
Mask lithography, to cut the afterbody of side wall ring so that the different components for the fin structure that is connected realize electric isolation, hence in so that work
Skill is complicated, cost increase.In addition, when circuit layout complexity improves, multiple fins are connected when forming complicated circuit, photoresist
Being respectively aligned to the precision of respective active area figure turns into one of factor that constraint device integrated level improves.
Therefore, it is necessary to which a kind of simple, efficient cutting forms the process that fin forms different components.
The content of the invention
From the above mentioned, it is an object of the invention to overcome above-mentioned technical difficulty, a kind of new FinFET manufacture methods are proposed,
It can realize that simple, efficiently cutting forms fin and forms different components with this by simplifying technique.
Therefore, the invention provides a kind of method, semi-conductor device manufacturing method, including：Pass through side wall transition diagram on substrate
Technology forms ring-type or other attachment structures communicated and groove；Formed between ring-type or other attachment structures communicated shallow
Trench isolations；False grid lines are formed on substrate, cover ring-type or other attachment structures communicated it is multiple independently of each other
Fin channel area, thus separate influence of the fin structure to different components of being connected.
Wherein, formed ring-type or it is other communicate attachment structure the step of further comprise：Sacrifice layer is formed on substrate
Figure；Sacrificing the side wall of formation ring-type or other connection shapes communicated around layer pattern；Remove and sacrifice layer pattern, in substrate
On leave the side wall of ring-type or other connection shapes communicated；Using the side wall of ring-type or other connection shapes communicated as mask,
Etched substrate forms ring-type or other connection shape and structures and groove communicated.
Wherein, sacrifice layer pattern material include silica, silicon nitride, non-crystalline silicon, polysilicon, silicon oxynitride, amorphous carbon,
DLC, photoresist and combinations thereof.
Wherein, formed before sacrificing layer pattern and further comprise forming hard mask on substrate.
Wherein, the step of forming shallow trench isolation further comprises：Ring-type or other connection shape and structures communicated it
Between groove in filling be dielectrically separated from medium；Return and be dielectrically separated from medium at quarter, with expose portion ring-type or other connection shapes communicated
Shape structure.
Wherein, formed after shallow trench isolation further comprise in ring-type or other connection shape and structures communicated and/
Or break-through barrier layer is formed on bottom.
Wherein, the step of forming false grid lines further comprises：False grid stack layer is formed on substrate；In false grid
Photoetching offset plate figure is formed on stack layer, it is overlapping with some of ring-type or other connection shape and structures communicated；With photoresist
Figure is mask, and etching removes uncovered false grid stack layer, leaves and covers ring-type or other connection shapes communicated
The false grid lines of some of structure.
Wherein, false grid lines cover ring-type or the stem and/or afterbody of other connection shape and structures communicated.
Wherein, false grid lines cover the middle part of ring-type or other connection shape and structures communicated.
Wherein, ring-type or other connection shape and structures communicated are rectangle frame, circular frame, polygon frame.
Wherein, further comprise：Grid curb wall and source-drain area are formed on the fin of false grid lines both sides；On device
Form interlayer dielectric layer；False grid lines are removed, gate trench is left in interlayer dielectric layer；Grid is formed in gate trench
Stack.
According to the method, semi-conductor device manufacturing method of the present invention, ultra-fine silicon fin is formed using side wall transition diagram, while
Raceway groove ring is formed in plane, false grid are formed on ring tail or other positions, thus automatic segmentation forms different raceway grooves, simplifies work
Skill, improve the device accuracy of manufacture.
Brief description of the drawings
Describe technical scheme in detail referring to the drawings, wherein：
Fig. 1 to Figure 14 is the diagrammatic cross-section according to each step of FinFET manufacture methods of the present invention；
Figure 15 is the indicative flowchart according to the FinFET manufacture methods of the present invention.
Embodiment
Referring to the drawings and schematical embodiment is combined to describe the feature of technical solution of the present invention and its skill in detail
Art effect, the FinFET manufacture methods to form fin can simply, efficiently be cut by disclosing.It is pointed out that similar is attached
Icon note represents similar structure, and term use herein " first ", " second ", " on ", " under " etc. can be used for modifying
Various device architectures or manufacturing process.These modifications do not imply that modified device architecture or manufacturing process unless stated otherwise
Space, order or hierarchical relationship.
It is worth noting that, following each accompanying drawing middle and upper part part be device in the first direction（Fin bearing of trend, source and drain
Bearing of trend）Sectional view, low portion be device top view.Herein for simplicity by borrow below this specification
" cyclic structure " come refer to " attachment structure communicated " and preferably refer to " ring-type and other（Such as square frame, round frame, ellipse
Frame, polygon frame etc.）The attachment structure communicated ", but ring-type will be clearly used in claim and Summary
And/or other attachment structures for communicating（As summary, these structures 1P is referred to using " attachment structure communicated "）Come
State schematical structure 1P in figure.
As shown in figure 1, hard mask layer 2 is formed on substrate 1.Substrate 1 is provided, substrate 1 needs and closed according to device application
Reason selection, it may include monocrystalline silicon（Si）, monocrystal germanium（Ge）, strained silicon（Strained Si）, germanium silicon（SiGe）, or change
Compound semi-conducting material, such as gallium nitride（GaN）, GaAs（GaAs）, indium phosphide (InP), indium antimonide（InSb）, and it is carbon-based
Semiconductor such as graphene, SiC, carbon nanotube etc..For the consideration compatible with CMOS technology, substrate 1 is preferably body Si.It is excellent
Selection of land, hard mask 2 is formed by process deposits such as LPCVD, PECVD to protect substrate during subsequent etching on substrate 1
To reduce surface defect, material is, for example, silica, silicon nitride, silicon oxynitride and combinations thereof on surface.Naturally, when precise controlling is carved
When losing parameter to reduce over etching, hard mask 2 can also actually be omitted.As shown in the lower part of Figure 1, hard mask 2 is now covered completely
The surface of substrate 1 is covered.
As shown in Fig. 2 sacrifice layer 3 and multiple photoetching offset plate figures 4 are formed in hard mask 2.By LPCVD, PECVD,
The techniques such as HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, sputtering, thermal oxide, chemical oxidation, spin coating, sacrifice layer 3 is formed,
To control the spacing between fin later.The material of sacrifice layer 3 such as silica, silicon nitride, non-crystalline silicon, polysilicon, nitrogen oxidation
Silicon, amorphous carbon, DLC, photoresist and other low k or high-g value and combinations thereof.As shown in Fig. 2 sacrifice layer 3 is completely covered
Hard mask 2 and substrate 1.The spin coating photoresist layer and exposure/photoetching process known to using forms photoresist on sacrifice layer 3
Figure 4.The width of figure 4 is equal to will form groove width or fin spacing later.It is worth noting that, accompanying drawing of the present invention is only
A figure 4 is diagrammatically illustrated, actually needs there may be multiple figures 4 according to device layout, these photoetching offset plate figures 4
Size shape can be with identical or different, can be with parallel, intersecting or connected.As shown in Fig. 2 figure 4 has longer a pair
Side, its bearing of trend are referred to as first direction, and the bearing of trend of a shorter opposite side is then referred to as second direction, and second direction is hung down
Directly in first direction.
As shown in figure 3, being mask with photoetching offset plate figure 4, etching sacrificial layer 3, formed and sacrifice layer pattern 3P.Etching is preferably adopted
With anisotropic lithographic method, such as plasma dry etch, reactive ion etching（RIE）, anisotropic wet method carves
Erosion（Such as TMAH is directed to Si base material matter）.The sacrifice layer pattern 3P of formation is identical with the width of photoetching offset plate figure 4, is to want shape later
There is certain distance into groove width or fin spacing, and apart from the border of substrate 1 or hard mask 2.Advantageously, then,
Photoetching offset plate figure 4 is removed using wet processing.
As shown in figure 4, spacer material layer 5 is formed on whole device.By LPCVD, PECVD, HDPCVD, UHVCVD,
The techniques such as MOCVD, MBE, ALD, evaporation, sputtering, thermal oxide, chemical oxidation, spin coating, spacer material layer 5 is formed on device, is covered
Cover the top of hard mask 2, sacrifice layer pattern 3P side and top.Spacer material layer 5 can be silica, silicon nitride, nitrogen
Silica, amorphous carbon, DLC amorphous carbon（DLC）Deng and combinations thereof.Preferably, the material of spacer material layer 5 and sacrifice layer
Figure 3P and hard mask 2, which are compared, has higher Etch selectivity, such as three's material is different.As shown in the lower part of Figure 4, side
The walling bed of material 5 completely covers device, therefore sacrifice layer pattern 3P below is shown as dotted line frame.
As shown in figure 5, etching spacer material layer 5, the side wall 5S of ring-type is formd around sacrifice layer pattern 3P.It is preferred that etc.
Gas ions dry etching or RIE, the layer 5 at the top of the layer 5 and sacrifice layer pattern 3P in hard mask 2 is substantially completely eliminated,
The side wall 5S of a loop is only left in sacrifice layer pattern 3P sides.Side wall 5S top view diagram shape is according to sacrifice layer pattern 3P
It is in an embodiment of the invention single rectangle frame to determine, can is that multiple frames combine to be formed in other embodiments
Annular polygonal frame.Side wall 5S thickness is the width of fin later, needs and sets according to device electric property, such as 10
~100nm and preferably 10~30nm.
As shown in fig. 6, selective removal sacrifices layer pattern 3P.It is preferred that wet etching, corrosive liquid is according to sacrifice layer pattern 3P
Material and adjacent side wall 5S materials select.Silicon nitride material is removed for example with hot phosphoric acid, HF base corrosive liquids go deoxygenation
SiClx material, hydrogen peroxide or deionized water ozoniferous remove amorphous carbon, DLC, TMAH remove polysilicon, non-crystalline silicon etc..Remove
After sacrifice layer pattern 3P, the side wall 5S of ring-type is only left in hard mask 2.
As shown in fig. 7, the hard mask 2 that selective removal is not covered by side wall 5S, until exposure substrate 1.With step shown in Fig. 6
It is rapid similar, it is preferred to use wet etching removes hard mask 2, and the hard mask figure 2 for being similarly ring-type is only left below side wall 5S,
Hard mask figure 2 has the opening for exposing substrate 1 with side wall 5.
As shown in figure 8, being mask with side wall 5S and hard mask figure 2, etched substrate 1, multiple rings are formd in substrate 1
Corresponding groove 1G between shape structure 1P and cyclic structure.In an embodiment of the invention, cyclic structure 1P is rectangle
Hollow barrel wall, namely horizontal profile is rectangle frame in top view.In other embodiments of the present invention, structure 1P is according to former figures
4 difference and can be other attachment structures communicated, such as lines are tortuous, closing, being open, square-section, more
Side tee section, circular cross-section, oval cross section etc. and combinations thereof.
As shown in figure 9, filling is dielectrically separated from medium in groove 1G, shallow trench isolation is formed（STI）6.In whole device
It is upper to pass through LPCVD, PECVD, HDPCVD, UHVCVD, MOCVD, MBE, ALD, evaporation, sputtering, thermal oxide, chemical oxidation, spin coating
Medium is dielectrically separated from etc. process deposits, such as including silica, silicon nitride, silicon oxynitride, low-k materials and combinations thereof, wherein low k
Material includes but is not limited to organic low-k materials（Such as the organic polymer containing aryl or more yuan of rings）, inorganic low-k material（Example
Such as amorphous carbon nitrogen film, polycrystalline boron nitrogen film, fluorine silica glass, BSG, PSG, BPSG）, porous low k material（Such as the oxygen of two silicon three
Alkane（SSQ）Quito hole low-k materials, porous silica, porous SiOCH, C silica is mixed, the porous amorphous carbon of F is mixed, is porous
Diamond, porous organic polymer）.Subsequent cmp planarization is dielectrically separated from medium until exposure hard mask layer 2 or cyclic structure
At the top of 1P.Further, quarter is returned（etch-back）Etching is dielectrically separated from medium to expose a cyclic structure 1P part and again
Form multiple groove 1G, the 1/3~2/3 of gash depth such as its cyclic structure 1P height, leave between cyclic structure 1P exhausted
Edge spacer medium constitutes STI6.
Preferably, before or after STI6 is formed, by ion implanting and activation of annealing, or deposit doped layer and move back
Fire diffusion so that STI6 top planes have been formed about doped layer or insulating barrier 1S in cyclic structure 1P, for isolating future
Channel region can be referred to as channel punchthrough barrier layer to avoid ghost effect or leakage current（PTSL）.Inject or diffusion
Impurity can be including C, F, N, O, B, P, As, Ge, Ga, Sn, In, Si etc. and combinations thereof, doped layer can include borosilicate
Sour glass（BSG）, phosphosilicate glass（PSG）, boron phosphosilicate glass（BPSG）, doped silicon oxide, doping spin-coating glass
（SOG）, doped silicon nitride（SiNx）, doped amorphous silicon, DOPOS doped polycrystalline silicon, doping amorphous carbon, doping low-k materials（low-k）Deng
And combinations thereof.Preferably, the doped layer position of injection depth or selection deposition is further improved so that cyclic structure 1P bottoms
The STI break-through barrier layer of similar or like material is also formed with the interface of substrate 1（It is not shown）.Break-through barrier layer can be
High doping semiconductor area with above-mentioned impurity, or the insulating materials of the oxidation silicon substrate with above-mentioned impurity.
Preferably, polish and clean at the top of exposed cyclic structure 1P, to reduce its surface defect.
As shown in Figure 10, false grid stack layer 7 is formed on device.Such as by LPCVD, PECVD, HDPCVD,
The methods of UHVCVD, MOCVD, MBE, ALD, evaporation, sputtering, thermal oxide, chemical oxidation, forms false grid insulating barrier 7A, false grid
Pole material layer 7B and preferably false grid cap rock 7C.False grid insulating barrier 7A is, for example, silica, silicon oxynitride or high k materials
Material, high-g value include but is not limited to include being selected from HfO2、HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、
HfLaSiOxHafnium sill（Wherein, each material is different according to multi-element metal component proportion and chemical valence, oxygen atom content x
Can Reasonable adjustment, such as can be 1~6 and be not limited to integer）, or including selected from ZrO2、La2O3、LaAlO3、TiO2、Y2O3's
Rare-earth-based high K dielectric material, or including Al2O3, with the composite bed of its above-mentioned material.False grid material layer 7B is, for example, polycrystalline
Silicon, non-crystalline silicon, amorphous germanium, amorphous carbon, DLC and combinations thereof.False grid cap rock 7C preferably harder materials are to realize hard mask layer
Or the effect of protective coating, its material is such as silicon nitride, DLC and combinations thereof.As shown in the lower part of Figure 10, false grid stack layer
7 completely covers whole device plane, therefore the cyclic structure 1P of lower section is represented with dotted line frame.
As shown in figure 11,7 are stacked in false grid（False grid cap rock 7C）False grid mask graph 7P is formed on top.Using
The photoresist spin coating known, exposure, developing process, false grid mask graph 7P is formed, figure 7P extends in a second direction, second party
To perpendicular to first direction.Wherein as shown in the lower part of Figure 11, the false grid mask graph 7P of photoresist and cyclic structure（Second
On direction）Side coincidence or overlapping, and preferably at least cover cyclic structure 1P stem（head）Or afterbody（tail）,
Such as in top view rectangle frame it is shorter（In second direction）Relative side.In addition, figure 7P also covers cyclic structure
1P middle part, such as the center line of rectangle frame.Wherein, the figure 7P of stem or afterbody is used to define false grid lines, and in
The 7P in portion is then used for the final or true grid lines for defining future device.
As shown in figure 12, using false grid mask graph 7P as mask, etching false grid stacks 7（7C、7B、7A）, until sudden and violent
Dew is not by figure 7P（And layer 7C/7B/7A below）At the top of the cyclic structure 1P of covering and at the top of STI6.Etching for example with
Anisotropic dry etch, or select wet etching for the characteristics of adjacent structure material difference.Herein, false grid lines
（Stem or afterbody）With true grid lines（Middle part）Etch simultaneously, false grid lines（Stem or afterbody）Automated shade its
The cyclic structure 1P of lower section stem or afterbody, namely surface trimming or at least two fin 1F are separated by, without follow-up
Technique further handles cyclic structure or fin structure.The part that cyclic structure 1P exposes can be described as fin structure 1F, be edge
Multiple parallel lines of first direction extension, erect on substrate 1.After removing figure 7P, left on substrate along first party
To multiple parallel false grid lines 7C/7B/7A of extension, respectively positioned at cyclic structure 1P stem or afterbody（Second direction
Shorter lateral sides）And middle part（In the middle part of the long side of first direction）.
As shown in figure 13, grid curb wall 8 and source-drain area 9 are formed in the side in the first direction of false grid lines.Pass through
The already known processes such as deposition, etching form the grid curb wall 8 of the materials such as silicon nitride, DLC, amorphous carbon, positioned at the edge of false grid lines
The side of first direction.It is mask with grid curb wall 8, in the fin 1F extended along the first defence line（Column structure 1P longer side
Side）Source-drain area 9 is formed on top.Source-drain area 9 can be the doped region of injection, or the lifting source and drain being epitaxially formed.Lifting source
Leaking material can be identical with substrate 1, fin 1F, such as is Si, can also material it is different, such as with more heavily stressed
SiGe、Si:C、Si:H、SiSn、GeSn、SiGe:C etc. and combinations thereof.Further, it is possible to forming the advance one of grid curb wall 8
Step is lightly doped injection and forms LDD structures（It is not shown）.
As shown in figure 14, final grid structure is formed.The inter-level dielectric of spin coating or deposition low-k materials on whole device
Layer（ILD, it is not shown）；Selective etch removes false grid lines, and the gate trench extended in a second direction is formed in ILD；
In gate trench deposition filling gate insulator 10A and grid conducting layer 10B, method be, for example, LPCVD, PECVD,
HDPCVD, UHVCVD, MOCVD, MBE, ALD, thermal oxide, chemical oxidation, evaporation, sputtering.Gate insulator 10A is high-g value,
Including but not limited to include being selected from HfO2、HfSiOx、HfSiON、HfAlOx、HfTaOx、HfLaOx、HfAlSiOx、HfLaSiOx's
Hafnium sill（Wherein, each material is different according to multi-element metal component proportion and chemical valence, oxygen atom content x can Reasonable adjustment,
Such as it can be 1~6 and be not limited to integer）, or including selected from ZrO2、La2O3、LaAlO3、TiO2、Y2O3The high K of rare-earth-based be situated between
Material, or including Al2O3, with the composite bed of its above-mentioned material.Grid conducting layer 10B then can be polysilicon, poly-SiGe,
Or metal, wherein metal may include Co, Ni, Cu, Al, Pd, Pt, Ru, Re, Mo, Ta, Ti, Hf, Zr, W, Ir, Eu, Nd, Er, La
Deng metal simple-substance or the nitride of the alloy of these metals and these metals, in grid conducting layer 10B can also doped with C, F,
N, the element such as O, B, P, As is to adjust work function.Between grid conducting layer 10B and gate insulator 10A further preferably by PVD,
The conventional methods such as CVD, ALD form the barrier layer of nitride（It is not shown）, barrier layer material is MxNy、MxSiyNz、MxAlyNz、
MaAlxSiyNz, wherein M is Ta, Ti, Hf, Zr, Mo, W or other element.
Hereafter, device manufacture can be further completed using rear grid technique（Following part is not shown）.For example, using
The techniques such as PECVD, evaporation, sputtering formed silicon nitride cap rock, and use CMP, return carve the methods of planarized gate stacking 10 with
And cap rock, until exposure ILD.The 2nd ILD is formed on device, and etches the source and drain contact that the 2nd ILD forms exposed source-drain area
Hole.Evaporation, sputtering, MOCVD, MBE, ALD form metal level in the contact hole（It is not shown）, its material such as Ni, Pt, Co, Ti,
The metals such as W and metal alloy.Anneal 1ms~10min under 250~1000 degrees Celsius so that metal or metal alloy and source
Contained Si element reactions form metal silicide in drain region, to reduce contact resistance.Pass through PECVD, MOCVD, evaporation, sputtering
Etc. technique, form metal, metal alloy and its metal nitride in the contact hole, wherein metal can include W, Al, Ti, Au,
Ag, Mo, Cu and combinations thereof.Each layer metal is planarized until the 2nd ILD of exposure, forms contact plug.
For device in practical work process, the true grid in the middle part of top view will apply suitable control voltage, make
Channel region transoid below or enhancing and connect the source-drain area of both sides.But in top view up and down（On both sides of the middle,
On the outside of source-drain area）It is virtual（dummy）Although grid and employing metal-high k stacked structures, in Butut wiring process
In do not form external connector, therefore the false gate electrode no power in device operation, realize device by raceway groove is closed
Electric isolation（Namely the cyclic structure 1P below cold false grid, structure 1P herein do not possess source and drain（Transoid）
It is highly doped, therefore electric isolation is realized by PN junction or PIN junction）, therefore prior art different from the past, nothing of the present invention
The cyclic structure 1P parts below removal false grid need to be etched completely, simplify technique.
According to the method, semi-conductor device manufacturing method of the present invention, ultra-fine silicon fin is formed using side wall transition diagram, while
Raceway groove ring is formed in plane, false grid are formed on ring tail or other positions, thus automatic segmentation forms different raceway grooves, simplifies work
Skill, improve the device accuracy of manufacture.
Although illustrating the present invention with reference to one or more exemplary embodiments, those skilled in the art could be aware that need not
Depart from the scope of the invention and various suitable changes and equivalents are made to device architecture.In addition, can by disclosed teaching
The modification of particular condition or material can be can be adapted to without departing from the scope of the invention by making many.Therefore, the purpose of the present invention does not exist
In being limited to as realizing the preferred forms of the present invention and disclosed specific embodiment, and disclosed device architecture
And its manufacture method is by all embodiments including falling within the scope of the present invention.
Claims (9)
1. a kind of method, semi-conductor device manufacturing method, including：
Ring-type or other attachment structures communicated and groove are formed by side wall transition diagram technology on substrate；
Shallow trench isolation is formed between ring-type or other attachment structures communicated；
False grid lines are formed on substrate, cover multiple separate fins of ring-type or other attachment structures communicated
Channel region, thus separate influence of the fin structure to different components of being connected, and false grid lines cover ring-type or other communicated
Connect the stem and/or afterbody of shape and structure.
2. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, formed ring-type or it is other communicate attachment structure the step of
Further comprise：
Formed on substrate and sacrifice layer pattern；
Sacrificing the side wall of formation ring-type or other connection shapes communicated around layer pattern；
Remove and sacrifice layer pattern, the side wall of ring-type or other connection shapes communicated is left on substrate；
Using the side wall of ring-type or other connection shapes communicated as mask, etched substrate forms ring-type or other connection shapes communicated
Shape structure and groove.
3. method, semi-conductor device manufacturing method as claimed in claim 2, wherein, sacrificing layer pattern material includes silica, silicon nitride, non-
Crystal silicon, polysilicon, silicon oxynitride, amorphous carbon, DLC, photoresist and combinations thereof.
4. method, semi-conductor device manufacturing method as claimed in claim 2, wherein, formed before sacrificing layer pattern and further comprised in substrate
Upper formation hard mask.
5. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, the step of forming shallow trench isolation, further comprises：
Filling is dielectrically separated from medium in groove between ring-type or other connection shape and structures communicated；
Return and be dielectrically separated from medium at quarter, with expose portion ring-type or other connection shape and structures communicated.
6. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, form shallow trench isolation and further comprise afterwards in ring-type
Or break-through barrier layer is formed in other connection shape and structures communicated and/or bottom.
7. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, the step of forming false grid lines, further comprises：
False grid stack layer is formed on substrate；
Photoetching offset plate figure is formed on false grid stack layer, with ring-type or some weights of other connection shape and structures communicated
It is folded；
Using photoetching offset plate figure as mask, etching removes uncovered false grid stack layer, leaves and covers ring-type or other phases
The false grid lines of some of logical connection shape and structure.
8. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, ring-type or other connection shape and structures communicated are rectangle
Frame, circular frame, polygon frame.
9. method, semi-conductor device manufacturing method as claimed in claim 1, wherein, further comprise：
Grid curb wall and source-drain area are formed on the fin of false grid lines both sides；
Interlayer dielectric layer is formed on device；
False grid lines are removed, gate trench is left in interlayer dielectric layer；
Gate stack is formed in gate trench.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310143802.3A CN104124160B (en) | 2013-04-23 | 2013-04-23 | Method, semi-conductor device manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310143802.3A CN104124160B (en) | 2013-04-23 | 2013-04-23 | Method, semi-conductor device manufacturing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104124160A CN104124160A (en) | 2014-10-29 |
| CN104124160B true CN104124160B (en) | 2018-03-30 |
Family
ID=51769529
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310143802.3A Active CN104124160B (en) | 2013-04-23 | 2013-04-23 | Method, semi-conductor device manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104124160B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10438948B2 (en) | 2016-01-29 | 2019-10-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and device of preventing merging of resist-protection-oxide (RPO) between adjacent structures |
| CN107492571A (en) * | 2016-06-13 | 2017-12-19 | 格科微电子（上海）有限公司 | Double fin-shaped field effect transistors of cmos image sensor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6943405B2 (en) * | 2003-07-01 | 2005-09-13 | International Business Machines Corporation | Integrated circuit having pairs of parallel complementary FinFETs |
| US7265059B2 (en) * | 2005-09-30 | 2007-09-04 | Freescale Semiconductor, Inc. | Multiple fin formation |
| US8334184B2 (en) * | 2009-12-23 | 2012-12-18 | Intel Corporation | Polish to remove topography in sacrificial gate layer prior to gate patterning |
-
2013
- 2013-04-23 CN CN201310143802.3A patent/CN104124160B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN104124160A (en) | 2014-10-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101769216B1 (en) | Semiconductor device and manufacturing method thereof | |
| US10964823B2 (en) | Semiconductor structure and method for forming same | |
| CN106252350B (en) | FinFET and forming method | |
| KR101795870B1 (en) | Fets and methods of forming fets | |
| CN106952956A (en) | Semiconductor devices and its manufacture method | |
| CN104112665B (en) | Semiconductor devices and its manufacturing method | |
| CN106158864A (en) | Method and structure for FinFET isolation | |
| CN105470133B (en) | Method, semi-conductor device manufacturing method | |
| CN104112667B (en) | Semiconductor devices and its manufacturing method | |
| CN103531455B (en) | Semiconductor devices and its manufacture method | |
| CN104167393B (en) | Method, semi-conductor device manufacturing method | |
| CN104124164B (en) | Semiconductor devices and its manufacturing method | |
| CN104124198B (en) | Semiconductor devices and its manufacturing method | |
| CN106298934A (en) | A kind of vertical nano-wire device of sheaths channel structure and preparation method thereof | |
| CN104167357B (en) | Semiconductor devices and its manufacture method | |
| CN103839819A (en) | Semiconductor device and manufacture method thereof | |
| CN106549054A (en) | FET and preparation method thereof | |
| CN106531632A (en) | Manufacturing method of stacked nanowire MOS transistor | |
| CN104124160B (en) | Method, semi-conductor device manufacturing method | |
| CN103579315B (en) | Semiconductor device and its manufacture method | |
| CN104112668B (en) | Semiconductor devices and its manufacturing method | |
| CN104103506B (en) | Method, semi-conductor device manufacturing method | |
| CN107369621A (en) | Fin formula field effect transistor and forming method thereof | |
| CN105336787B (en) | Semiconductor devices and its manufacturing method | |
| CN109300838A (en) | Semiconductor structure and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |