CN109300838A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109300838A CN109300838A CN201710614901.3A CN201710614901A CN109300838A CN 109300838 A CN109300838 A CN 109300838A CN 201710614901 A CN201710614901 A CN 201710614901A CN 109300838 A CN109300838 A CN 109300838A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
Abstract
A kind of semiconductor structure and forming method thereof, forming method includes: to form substrate, the substrate includes substrate, the gate structure on the substrate and the etching stop layer between neighboring gate structures on substrate, and the etching stop layer also extends on the side wall of the gate structure；Form protective layer, the etching stop layer between the protective layer covering neighboring gate structures, and the etching stop layer on gate structure sidewall described in exposed portion；It is formed after the protective layer, reduction processing is carried out to the etching stop layer of exposing.By before reduction processing; form the protective layer; under the premise of guaranteeing the etching stop layer thickness; expand the width in gap between neighboring gate structures; it reduces interlayer dielectric layer fill process difficulty and expands taking into account for contact hole process window; the raising for being conducive to yield is conducive to the raising of formed semiconductor structure performance.
Description
Technical field
The present invention relates to field of semiconductor manufacture, in particular to a kind of semiconductor structure and forming method thereof.
Background technique
With the continuous development of ic manufacturing technology, requirement of the people to the integrated level and performance of integrated circuit becomes
It is higher and higher.In order to improve integrated level, cost is reduced, the critical size of component constantly becomes smaller, the circuit of IC interior
Density is increasing, and this development is so that crystal column surface can not provide enough areas to make required interconnection line.
In order to meet the interconnection needs after critical dimension reduction, at present difference semiconductor structures between and semiconductor junction
It is to be electrically connected by the interconnection architecture realization being made of plug and interconnection line between structure and circuit.And in the structure of plug
Multiple functions film layer is also introduced, to reach the purpose of reducing contact resistance, preventing metal from spreading.
With the continuous reduction of size, prior art is formed, and there is the semiconductor structure of plug to be often easy window mistake
Problem small, yield is too low or performance is bad.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, to expand process window, improve
Yield improves the performance of semiconductor structure.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising: substrate is formed, it is described
Substrate includes substrate, the gate structure on the substrate and the etching stopping between neighboring gate structures on substrate
Layer, the etching stop layer also extend on the side wall of the gate structure；Protective layer is formed, the protective layer covers adjacent gate
Etching stop layer between the structure of pole, and the etching stop layer on gate structure sidewall described in exposed portion；Form the protection
After layer, reduction processing is carried out to the etching stop layer of exposing.
Correspondingly, the present invention also provides a kind of semiconductor structures, comprising: substrate, the substrate include substrate, positioned at described
Gate structure on substrate and the etching stop layer being located at least between neighboring gate structures on substrate；Interlayer dielectric layer, until
It is filled between neighboring gate structures less, width of the interlayer dielectric layer between neighboring gate structures far from the substrate side is big
The width of interlayer dielectric layer between neighboring gate structures close to the substrate side.
Compared with prior art, technical solution of the present invention has the advantage that
Since the reduction processing carries out after protective layer formation, so during reduction processing, the guarantor
Sheath can play the etching stop layer between protection neighboring gate structures on substrate, prevent the etching stop layer impaired, from
And can effectively expand the process window for being subsequently formed interlayer dielectric layer and contact hole, be conducive to the raising of yield；Therefore pass through
The setting of the protective layer and the progress of the reduction processing can guarantee etching stop layer thickness between neighboring gate structures
Under the premise of, effectively expand the width in gap between neighboring gate structures, so that filling out for subsequent interlayer dielectric layer can either be reduced
Technology difficulty is filled, the formation quality of interlayer dielectric layer is improved, additionally it is possible to guarantee the process window that subsequent touch hole is formed, be conducive to
The raising of yield is conducive to the raising of formed semiconductor structure performance.
Detailed description of the invention
Fig. 1 to Fig. 4 is a kind of the schematic diagram of the section structure of each step of method for forming semiconductor structure；
Fig. 5 to Figure 10 is the corresponding cross-section structure signal of each step of one embodiment of method for forming semiconductor structure of the present invention
Figure；
Figure 11 to Figure 15 is the corresponding cross-section structure of each step of another embodiment of method for forming semiconductor structure of the present invention
Schematic diagram.
Specific embodiment
Being formed it can be seen from background technology that, the prior art, there is the semiconductor structure of plug often to have that window is too small, yield
Too low or bad performance problem.Now in conjunction with a kind of semiconductor structure forming process analyze its window is too small, yield is too low,
The reason of performance bad problem:
Referring to figs. 1 to Fig. 4, a kind of the schematic diagram of the section structure of each step of method for forming semiconductor structure is shown.
With reference to Fig. 1, substrate is formed, the substrate includes substrate 11 and the fin 12 on the substrate 11.The fin
There is pseudo- grid structure 13 in portion 12, there are stressor layers 14 in the fin 12 between dummy gate structure 13；In the stressor layers 14
With etching stop layer 15, the etching stop layer 15 is also extended on the side wall of adjacent pseudo- grid structure 13.
In conjunction with reference Fig. 2, dielectric layer 16 is formed on the substrate 11 that dummy gate structure 13 is exposed, the dielectric layer 16 covers
Lid dummy gate structure 13.
With reference to Fig. 3, planarization process is carried out to exposing dummy gate structure 13 (as shown in Figure 1) to the dielectric layer 16；
Later, dummy gate structure 13 is removed, forms gate openings (not indicating in figure) in the dielectric layer 16；It is opened in the grid
Metal gate structure 17 is formed in mouthful.
With reference to Fig. 4, contact hole 18 is formed between adjacent metal gate structure 17, the contact hole is situated between through the interlayer
Matter layer 16 exposes the etching stop layer 15 on 14 surface of stressor layers.
With the reduction of device size, the distance between adjacent transistor is smaller and smaller, distance between neighboring gate structures
Also smaller and smaller, i.e., it is adjacent as shown in Figure 1, the width in gap 20 (as shown in Figure 1) is smaller and smaller between adjacent puppet grid structure 13
The depth-to-width ratio in gap 20 increases with it between pseudo- grid structure 13.The increase of 20 depth-to-width ratio of gap can increase between adjacent puppet grid structure 13
The filling difficulty of the big dielectric layer 16 is easy to appear cavity 21 (such as Fig. 2 institute in the dielectric layer 16 between adjacent puppet grid structure 13
Show), to affect the performance of the dielectric layer 16, it is likely to result in the reduction of formed semiconductor structure yield, performance
It degenerates.
In order to reduce the depth-to-width ratio in gap 20 between adjacent pseudo- grid structure 13, a kind of method is to reduce etching stop layer 15
Thickness, even if the thickness of etching stop layer 15 reduces on 13 side wall of dummy gate structure, thus expand adjacent pseudo- grid structure 13 it
Between gap 20 width, and then achieve the purpose that reduce depth-to-width ratio.
But the whole of 15 thickness of etching stop layer reduces, and can make the thickness of etching stop layer 15 in stressor layers 14 also therewith
Reduce；The reduction of 15 thickness of etching stop layer in stressor layers 14, can weaken the etching stopping ability of the etching stop layer 15, from
And the window of contact hole 18 (as shown in Figure 3) formation process can be reduced, it may during forming the contact hole 18
It is impaired to make the stressor layers 14, and then the loss of yield may also be caused, the degeneration of device performance.
To solve the technical problem, the present invention provides a kind of forming method of semiconductor structure, by reduction processing
Before, the protective layer for forming etching stop layer between covering neighboring gate structures, before guaranteeing the etching stop layer thickness
It puts, expands the width in gap between neighboring gate structures, so that reaching reduces interlayer dielectric layer fill process difficulty and expansion
Contact hole process window is taken into account, and the raising of yield is conducive to, and is conducive to the raising of formed semiconductor structure performance.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
With reference to Fig. 5 to Figure 10, show that each step of one embodiment of method for forming semiconductor structure of the present invention is corresponding to be cutd open
Face structural schematic diagram.
With reference to Fig. 5, form substrate, the substrate include substrate 110, the gate structure on the substrate 110 and
Etching stop layer 150 between neighboring gate structures on substrate 110, the etching stop layer 150 also extend to the grid
On the side wall of pole structure.
In the present embodiment, being formed by semiconductor structure is transistor, so the substrate further includes with stressor layers 140
Source and drain doping area, on the substrate 110 of gate structure two sides.
The substrate is used to provide Process ba- sis for Subsequent semiconductor step.In the present embodiment, formed semiconductor structure
For fin formula field effect transistor, so the substrate includes substrate 110 and discrete fin 120 on the substrate 110.This
In invention other embodiments, formed semiconductor structure may be planar transistor, and the substrate can also only include plane
Substrate.
The substrate 110 provides technological operation platform to be subsequently formed semiconductor structure；The ditch of formed semiconductor structure
Road is located in the fin 120.In the present embodiment, 110 material of substrate is monocrystalline silicon.In other embodiments of the invention, institute
State substrate material be also selected from polysilicon, amorphous silicon or germanium, germanium, SiGe, silicon carbide, GaAs or gallium indium etc. its
His material.In other embodiments of the invention, the substrate can also be the silicon substrate on insulator, the germanium substrate on insulator
Or the other kinds of substrate such as glass substrate.The material of the substrate can be the material for being suitable for process requirement or being easily integrated
Material.
In the present embodiment, it is all monocrystalline silicon that the material of the fin 120 is identical as the material of the substrate 110.The present invention
In other embodiments, the material of the fin can also be different from the material of the substrate.The material of the fin may be
The other materials such as germanium, germanium, SiGe, silicon carbide, GaAs or gallium indium.
In the present embodiment, the substrate 110 and the fin 120 can be formed simultaneously, and form the substrate 110 and described
The step of fin 120 includes: offer initial substrate；Patterned fin mask layer is formed (in figure in the initial substrate surface
It is not shown)；Using the fin mask layer as exposure mask, the initial substrate is etched, remove the part initial substrate, described in formation
Substrate 110 and the fin 120 for being raised in 110 surface of substrate.
In the present embodiment, the high-K metal gate structure that there is formed semiconductor structure rear grid technique to be formed, so described
Gate structure is pseudo- grid structure 130, for taking up space position for the formation of subsequent high-K metal gate structure.But it is of the invention
In other embodiments, the gate structure is also possible to the gate structure of formed semiconductor structure, forms half for controlling
The conducting and truncation of conductor structure channel.
Specifically, dummy gate structure 130 is single layer structure, (in figure not including the dummy grid on the fin 120
Mark).In the present embodiment, the material of the dummy grid is polysilicon.In other embodiments of the invention, the material of the dummy grid
It can also be the other materials such as silica, silicon nitride, silicon oxynitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride or amorphous carbon.
In other embodiments of the invention, dummy gate structure can also be laminated construction, including pseudo- oxide layer and be located at institute
State the dummy grid in pseudo- oxide layer.The material of the puppet oxide layer can be silica or silicon oxynitride；The material of the dummy grid
Material can for polysilicon, silica, silicon nitride, silicon oxynitride, silicon carbide, carbonitride of silicium, carbon silicon oxynitride or amorphous carbon etc. its
His material.
Specifically, the step of forming dummy gate structure 130 includes: to be formed on the substrate 110 and the fin 120
Pseudo- gate material layer；Gate mask layer (not shown) is formed in the pseudo- gate material layer；It is to cover with the gate mask layer
Film etches the pseudo- gate material layer to the fin 120 is exposed, forms the dummy grid, the dummy grid is across the fin
120 and be located at 120 atop part of fin and partial sidewall on.
It should be noted that being formed after the gate structure, the forming method further include: in the gate structure
Side wall (not indicating in figure) is formed on side wall, to protect the gate structure and define the position in subsequent formed source and drain doping area
It sets.In the present embodiment, the side wall is located on the side wall of dummy gate structure 130.
In the present embodiment, the side wall is the silicon nitride of single layer structure.In other embodiments of the invention, the side wall may be used also
Think laminated construction.In other embodiments of the invention, the material of the side wall can also for silica, silicon carbide, carbonitride of silicium,
One of carbon silicon oxynitride, silicon oxynitride, boron nitride or boron carbonitrides are a variety of.
The source and drain doping area is used to form source region or the drain region of the semiconductor structure.Specifically, forming the source and drain
The step of doped region includes: the formation stressor layers 140 in the fin 120 of the gate structure two sides；To the stressor layers 140 into
Row doping is to form the source and drain doping area.
It should be noted that sharing same source and drain doping area in the present embodiment, between adjacent transistor, that is to say, that institute
Source and drain doping area is stated on the substrate 110 between neighboring gate structures, therefore the stressor layers 140 are located at adjacent pseudo- grid structure
On substrate 110 between 130.
When formed semiconductor structure is used to form PMOS device, the material of the stressor layers 140 is the germanium silicon of p-type doping
Or silicon, Doped ions can be B, Ga or In；When formed semiconductor structure is used to form NMOS device, the stressor layers 140
Material be n-type doping carbon silicon or silicon, Doped ions can be P, As or Sb.
The etching stop layer 150 plays etching stopping in the forming process in subsequent touch hole, to reach guarantor
Protect the purpose in the source and drain doping area.The source and drain doping area is between neighboring gate structures, therefore the etching stop layer
150 are located at least on the substrate 110 between neighboring gate structures.And in the present embodiment, the source and drain doping area has stress
Layer 140, so the etching stop layer 150 at least covers the stressor layers 140 between adjacent pseudo- grid structure 130.
Since technique limits, the etching stop layer 150 is not only located on the substrate 110 between neighboring gate structures, also
It extends on the side wall of the gate structure, i.e., the described etching stop layer 150 also covers the side wall.It is described in the present embodiment
Etching stop layer 150 is located in the stressor layers 140 and dummy gate structure 130.In addition, in the present embodiment, the grid knot
Also there is side wall, so the etching stop layer 150 also covers the surface of the side wall on structure side wall.
In the present embodiment, the material of the etching stop layer 150 is silicon nitride, can by way of atomic layer deposition shape
At.In other embodiments of the invention, the material of the etching stop layer can also be the other materials such as silicon oxynitride, can also lead to
The other modes such as chemical vapor deposition or physical vapour deposition (PVD) are crossed to be formed.
With reference to Fig. 6, protective layer 161 is formed, the protective layer 161 covers the etching stop layer 150 between gate structure, and
Etching stop layer 150 on gate structure sidewall described in exposed portion.
The protective layer 161 is used to protect the etching stop layer 150 between gate structure, prevents the etching stop layer
150 are influenced by subsequent technique.
In the present embodiment, the protective layer 161 is bottom anti-reflection layer.In other embodiments of the invention, the protective layer
It can also be polysilicon layer, organic dielectric layer, spun-on carbon layer or amorphous carbon layer.In other embodiments of the invention, the protection
The material of layer can also be the fluid or semi-fluid materials that can be used as interlayer dielectric layer after solidifying.
In the present embodiment, the thickness of the protective layer 161 is greater thanThe thickness of the protective layer 161 should not be too small.Institute
If the thickness for stating protective layer is too small, the protective layer 161 may be will affect to etching stop layer between neighboring gate structures
150 protective capability is unfavorable for preventing the etching stop layer 150 impaired.
Specifically, the step of forming protective layer 161 includes: to form protected material bed of material (not shown), the guarantor
Protective material layer is filled between neighboring gate structures, and covers the gate structure；It returns and carves the protected material bed of material, exposed portion
Etching stop layer 150 on the gate structure sidewall.
The protected material bed of material is used to provide basis for the formation of the protective layer.The step of forming the protected material bed of material
It include: that the protected material bed of material is formed by way of spin coating.Due to the reduction with device size, between neighboring gate structures
Gap width is smaller and smaller；As shown in fig. 6, the width in gap 181 is smaller and smaller between adjacent puppet grid structure 130.So passing through
Spin coating mode forms the protected material bed of material, can reduce gap between the adjacent pseudo- grid structure 130 of the protected material bed of material filling
181 difficulty is conducive to the gap 181 between the adjacent pseudo- grid structure 130 of the protected material bed of material filling full phase.
The step of carving the protected material bed of material is returned, for making the top of formed protective layer 161 lower than the gate structure
Top, thus expose on the gate structure sidewall far from 110 side of substrate partial etching stop-layer 150, after being
The reduction processing of continuous exposed etching stop layer 150 provides artistic face.
In the present embodiment, returns and carve the protected material bed of material to reduce the height at the top of the protective layer protected material bed of material, reveal
Partial etching stop-layer 150 on 130 side wall of dummy gate structure out.Specifically, can be returned by way of wet etching quarter
The protected material bed of material.
Return carve the protected material bed of material depth should not it is too big also should not be too small.Return the depth of the quarter protected material bed of material such as
Fruit is too big, then the thickness of remaining formed protective layer 161 is too small, may will affect the protective layer 161 to neighboring gate structures
Between on substrate etching stop layer 150 protective capability, the possibility that the etching stop layer 150 is damaged may be will increase,
It is unfavorable for expanding the process window in subsequent touch hole, is unfavorable for the raising of yield；If returning the depth for carving the protected material bed of material
Too small, then the thickness of remaining formed protective layer 161 is too big, exposes the face of etching stop layer 150 on the gate structure sidewall
Product is very little, may will affect subsequent being thinned to the etching stop layer 150 exposed, be unfavorable between the neighboring gate structures of gap
The depth-to-width ratio in gap 181 is unfavorable for reducing the filling difficulty of subsequent interlayer dielectric layer.
Specifically, 181 depth of gap between depth and neighboring gate structures is carved in returning for the protected material bed of material in the present embodiment
The ratio of degree in 20:100 to 95:100 range, that is, return carve after the protective layer 161 with a thickness of between neighboring gate structures
In 5% to 80% range of 181 depth of gap.
It with reference to Fig. 7, is formed after the protective layer 161, reduction processing is carried out to the etching stop layer 150 of exposing
162。
The reduction processing 162 is for removing separate 110 side of substrate, etching stopping on the gate structure sidewall
The segment thickness of layer 150, thus expand opening size of the gap 181 far from 110 side of substrate between neighboring gate structures,
And then reduce the depth-to-width ratio in gap 181 between neighboring gate structures, reduce the technology difficulty of subsequent filling interlayer dielectric layer.
Due to being covered with the protective layer 161 on the etching stop layer 150 between neighboring gate structures, so described be thinned
Processing 162 can only remove the partial etching stop-layer 150 that the protective layer 161 exposes and carry out, and will not influence neighboring gates
The thickness of partial etching stop-layer 150 between structure on substrate 110 will not influence between neighboring gate structures on substrate 110
The etching stopping ability of partial etching stop-layer 150.
Specifically, the protective layer 161 is located in the stressor layers 140 between adjacent pseudo- grid structure 130 in the present embodiment,
So the reduction processing 162 can only carry out the partial etching stop-layer 150 on 130 side wall of dummy gate structure, not
It will affect the partial etching stop-layer 150 between the protective layer 161 and the stressor layers 140.
In the present embodiment, the material of the etching stop layer 150 is silicon nitride, so the reduction processing 162 can lead to
The mode for crossing plasma etching carries out.Specifically, the plasma pair including at least one of C-F base and HBr can be passed through
The etching stop layer 150 carries out the reduction processing 162.
In other embodiments of the invention, the reduction processing can also be carried out by way of wet etching.Specifically, subtracting
Used etching solution is the mixed solution (HF/ of phosphoric acid, hydrofluoric acid (HF) or hydrofluoric acid and ethylene glycol during thin processing
DG one of) or a variety of.
The etch amount of the reduction processing 162 should not it is too big also should not be too small.If the etch amount of the reduction processing 162
It is too big, then the gate structure may be impacted, will increase the impaired possibility of the gate structure, be unfavorable for yield
It improves；If the etch amount of the reduction processing is too small, it may will affect and expand 181 width of gap between neighboring gate structures
Effect, be unfavorable for expand neighboring gate structures between gap 181 depth-to-width ratio, be unfavorable for reducing filling out for subsequent interlayer dielectric layer
Fill technology difficulty.Specifically, the etch amount of the reduction processing 162 exists in the present embodimentIt arrivesRange.
It should be noted that according to the concrete technology ability and formed semiconductor structure that form the semiconductor structure
Specific design, set the etch amount of the reduction processing 162, thus reach interlayer dielectric layer filling capacity improve and protection
Gate structure is taken into account.
In the present embodiment, the protective layer 161 be bottom anti-reflection layer, can not subsequent realization adjacent semiconductor constructs it
Between, the electrical isolation between adjacent metal, therefore refer to Fig. 8, the forming method further include: the reduction processing 162 it
Afterwards, formed before interlayer dielectric layer, remove the protective layer 162, with prevent the protective layer 162 influence subsequent technique into
Row, prevents performance degradation caused by the presence of the protective layer 162.Specifically, the protective layer 161 is bottom anti-reflective
Layer, it is possible to remove the protective layer by way of ashing or wet etching.
But in other embodiments of the invention, the protective layer can also be the stream that can be used as interlayer dielectric layer after solidifying
Body or semi-fluid materials.When can be used as the fluid or semi-fluid materials of interlayer dielectric layer after the protective layer is to solidify,
The protective layer can not be removed, makes the protective layer as a part of the interlayer dielectric layer.
In conjunction with reference Fig. 9, after the reduction processing 162 (as shown in Figure 7), formation be filled in neighboring gate structures it
Between interlayer dielectric layer 170.
The interlayer dielectric layer 170 fills the gap 181 between full neighboring gate structures, for realizing adjacent semiconductor knot
Electric isolution between structure, between adjacent metal.In addition, formed semiconductor structure has rear grid technique shape in the present embodiment
At high-K metal gate structure, so the interlayer dielectric layer 170 is also used to define the ruler of formed high-K metal gate structure
Very little and position.
Since the etching stop layer 150 on gate structure sidewall is through reduction processing 162, so for the gate structure side
For etching stop layer 150 on wall, the thickness far from 110 side of substrate is smaller, the thickness close to 110 side of substrate
Spend it is larger, i.e., far from the size on the vertical gate structure sidewall direction of etching stop layer 150 described in 110 side of substrate
Less than the size on the vertical gate structure sidewall direction of etching stop layer 150 described in 110 side of substrate.And
Etching stop layer 150 on the gate structure sidewall is ladder-like in single layer towards the surface of neighboring gate structures.
Specifically, in the present embodiment, etching stop layer 150 on pseudo- grid structure 130 (as shown in Figure 8) side wall, far from institute
Processing of the part of substrate 110 by the reduction processing 162 is stated, so that thickness is smaller；Close to the substrate 110 part with
And the part between adjacent pseudo- grid structure 130 in stressor layers 140, since the protection by the protective layer 162 is (such as Fig. 7 institute
Show), so that thickness is larger；Therefore gap 181 is greater than far from the width of 110 side of substrate between adjacent pseudo- grid structure 130
Width close to 110 side of substrate, and the side wall in gap 181 is in that single layer is ladder-like between adjacent pseudo- grid structure 130.
Due between adjacent pseudo- grid structure 130 gap 181 far from the 110 side width of substrate larger, adjacent puppet
The depth-to-width ratio in gap 181 is smaller between grid structure 130, can be effectively reduced and fills out in gap 181 between adjacent pseudo- grid structure 130
The technology difficulty for filling interlayer dielectric layer 170 reduces the probability that cavity generates in the interlayer dielectric layer 170, improves inter-level dielectric
The formation quality of layer 170 improves the yield for forming the semiconductor structure, improves the performance of formed semiconductor structure.
In the present embodiment, the interlayer dielectric layer 170 includes the first medium layer between adjacent neighboring gate structures
171 and the second dielectric layer 172 on the first medium layer 171.Specifically, forming the step of the interlayer dielectric layer 170
Suddenly includes: to form first medium layer 171, the first medium layer 171 fill the adjacent pseudo- grid structure 130 (as shown in Figure 8) of full phase it
Between gap, and cover described pseudo- grid structure 130；Planarization process is carried out to exposing the puppet to the first medium layer 171
Grid structure 130；Dummy gate structure 130 is removed, (is not shown in figure with forming gate openings in the first medium layer 171
Out)；Metal gate structure 180 is formed in the gate openings；In the first medium layer 171 and the metal gate structure
Second dielectric layer 172 is formed on 180.
In the present embodiment, there is formed semiconductor structure rear grid technique to be formed by high-K metal gate structure, so institute
State a part that first medium layer 171 serves not only as interlayer dielectric layer 170, for realizing between neighboring gate structures, adjacent half
Electric isolution between conductor structure；And the first medium layer 171 only planarized exposes dummy gate structure 130, so described
First medium layer 171 is also used to define size and the position of high-K metal gate structure.The material of the first medium layer 171 is
Silica.In other embodiments of the invention, the material of the first medium layer can also be silicon nitride or silicon oxynitride etc. other
Insulating materials.
The gate openings are used to provide operating space for the formation of the metal gate structure 180.In the present embodiment, institute
Stating substrate 100 includes the substrate 110 and the fin 120, and dummy gate structure 130 is across the fin 120 and covering institute
State 120 atop part of fin and partial sidewall surface, thus the gate openings bottom expose 120 atop part of fin and
Partial sidewall surface.
The metal gate structure 180 by formation semiconductor structure gate structure, for controlling formed semiconductor
The conducting and truncation of structure channel.The step of forming metal gate structure 180 includes: to expose in the gate openings bottom
Fin 120 on form the gate dielectric layer (not indicating in figure)；Metal gate electrode is formed on the gate dielectric layer.
The gate dielectric layer is for realizing the electric isolution between the metal gate structure 180 and channel.The gate medium
The material of layer is high K dielectric material.Wherein, high K dielectric material refers to that relative dielectric constant is greater than silica relative dielectric constant
Dielectric material.In the present embodiment, the material of the gate dielectric layer is HfO2.In other embodiments of the invention, the gate medium
The material of layer is also selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3Deng.
The gate dielectric layer can be formed by way of atomic layer deposition.In other embodiments of the invention, the grid are situated between
Matter layer other film deposition modes can also be formed by chemical vapor deposition or physical vapour deposition (PVD) etc..The metal gate electrode
It is used as electrode, realization is electrically connected with external circuit.In the present embodiment, the material of the metal gate electrode is W.The present invention its
In his embodiment, the material of the metal gate electrode can also be Al, Cu, Ag, Au, Pt, Ni or Ti etc..
The a part of the second dielectric layer 172 as the interlayer dielectric layer 170, for realizing adjacent metal, phase
Electric isolution between adjacent semiconductor structure.The material of the second dielectric layer 172 is silica.In other embodiments of the invention,
The material of the first medium layer can also be other insulating materials such as silicon nitride or silicon oxynitride.
It should be noted that forming contact hole (Self-Aligned subsequently through self-registered technology in the present embodiment
Contact, SAC), so the forming method further include: formed after the metal gate structure 180, form described second
Before dielectric layer 172, the mask layer (not indicating in figure) being located on the metal-gate structures 180 is formed.
Specifically, the material of the mask layer is silicon nitride in the present embodiment.The step of forming the mask layer include:
The metal gate structure 180 for removing segment thickness, forms groove in the first medium layer 171；In the groove
Form the mask layer.
It should be noted that in the present embodiment, passing through fluid to improve the filling capacity of the first medium layer 171
The mode of chemical vapor deposition forms the first medium layer 171；In order to improve the surfacing of the second dielectric layer 172
Degree provides preferable technological operation surface for subsequent technique, in the present embodiment, is formed by way of fluid chemistry vapor deposition
The second dielectric layer 172.So the technique for forming the interlayer dielectric layer 170 includes: fluid chemistry gas phase in the present embodiment
Deposition.The interlayer dielectric layer 170 is formed in such a way that fluid chemistry is vapor-deposited, the inter-level dielectric can be effectively improved
The filling effect of layer 170, effectively improves the surface smoothness of the interlayer dielectric layer 170, is conducive to the raising of yield, is conducive to
The improvement of performance.
With reference to Fig. 9 and Figure 10, the contact hole 180 for running through the interlayer dielectric layer 170 is formed between neighboring gate structures.
The contact hole 180 is used to provide space and basis to be subsequently formed plug.In the present embodiment, pass through autoregistration work
Skill forms the contact hole 180, so the step of forming contact hole 180 includes: as shown in figure 9, in the inter-level dielectric
Contact hole mask layer 191 is formed on layer 170；Hard mask layer 192 is formed on the contact hole mask layer 191；It is covered firmly described
Graph layer 193 is formed in film layer 192, and there is figure opening (not indicating in figure) in the graph layer 193, the figure opening
Gap is corresponding between position and adjacent metal gate structure 180, and the width of figure opening is greater than adjacent metal grid
The width in gap between structure 180；As shown in Figure 10, it is exposure mask with the graph layer 193, is sequentially etched the hard mask layer
192, the contact hole mask layer 191 and the second dielectric layer 172 form the first opening in the second dielectric layer 172,
First open bottom exposes the first medium layer 171 and the metal gates knot between adjacent metal gate structure 180
Mask layer on structure 180；It is exposure mask with the metal gate structure 180, etches exposed first medium layer 171, forms institute
State contact hole 180.
During etching forms the contact hole 180, with the etching stop layer between neighboring gate structures on substrate 110
150 be stop-layer, i.e., in the present embodiment, with the etching stop layer 150 between adjacent metal gate structure 180 in stressor layers 140
It is performed etching for stop-layer.Due to reduction processing 162 (as shown in Figure 7), there is protection on substrate 110 between neighboring gate structures
161 (as shown in Figure 7) of layer, therefore the etching stop layer 150 does not receive the influence of the reduction processing 162, the etch-stop
Only the thickness of layer 150 is larger；The biggish thickness of the etching stop layer 150, can effectively expand to form the contact hole 180
Process window can effectively reduce the probability that the stressor layers 140 incur loss, be conducive to the raising of yield, be conducive to improve
The performance of formed semiconductor structure.
With reference to figures 11 to Figure 15, it is corresponding to show each step of another embodiment of method for forming semiconductor structure of the present invention
The schematic diagram of the section structure.
The present embodiment and previous embodiment something in common, details are not described herein by the present invention.The present embodiment and previous embodiment
The difference is that the forming process of the protective layer, the interlayer dielectric layer and the contact hole is different.
It with reference to Figure 11 and Figure 12, is formed protective layer 261 (as shown in figure 12), the protective layer 261 covers neighboring gates knot
Etching stop layer 250 between structure, and the etching stop layer 250. on gate structure sidewall described in exposed portion
As shown in figure 11, in the present embodiment, the substrate further include: filled media layer 263 is filled in neighboring gate structures
Between and the covering gate structure；So as shown in figure 11, the step of forming protective layer 261 include: back carve described in fill out
Filling medium layer 263 (as shown in figure 11), the etching stop layer 250 on gate structure sidewall described in exposed portion, remaining filling
Dielectric layer is used to be used as the protective layer 261.
Specifically, there is the semiconductor structure rear grid technique to be formed by high-K metal gate structure, so the grid
Structure is pseudo- grid structure 230；So the etching stop layer 250 is located on the substrate 210 between adjacent pseudo- grid structure 230, and
It extends on the side wall of dummy gate structure 230, the filled media layer 263 is filled between adjacent pseudo- grid structure 230.
In the present embodiment, the filled media layer 263 is used to provide basis for the formation of the protective layer 261；And institute
State filled media layer 263 also as a part of interlayer dielectric layer, for realizing between neighboring gate structures, adjacent semiconductor knot
Electric isolution between structure；In addition, the filled media layer 263 is also used to be formed in high-K metal gate structure in the present embodiment
Size and the position of high-K metal gate structure are defined together with first medium layer with subsequent be formed by journey.
Due to the subsequent a part as the interlayer dielectric layer of the filled media layer 263, so the filled media
Layer 263 is identical as the subsequent material for being formed by first medium layer.In the present embodiment, the material of the filled media layer 263 can
Think the dielectric layer materials such as silica, silicon oxynitride.
Specifically, improving the protection of subsequent formed protective layer to improve the gap filling ability of the filled media layer 263
Ability in the present embodiment, forms the filled media layer 263 in such a way that fluid chemistry is vapor-deposited.So the filling
Dielectric layer 263 can pass through shape after the cured processing such as trimethyl silicane alkanamine (Trisilylamine, TSA) or polysilane material
At.
It with reference to Figure 13, is formed after the protective layer 261, reduction processing 262 is carried out to the etching stop layer 250 of exposing.
In the present embodiment, the substrate further include: side wall 231 is located on the gate structure sidewall；The etching stopping
The 250 covering side wall 231 of layer.The side wall 231 is for protecting the gate structure and defining formed source and drain doping area
Position.In the present embodiment, the side wall is located on the side wall of dummy gate structure 130.
In the present embodiment, the side wall 231 is the silicon nitride of single layer structure.In other embodiments of the invention, the side wall
It can also be laminated construction.In other embodiments of the invention, the material of the side wall can also be silica, silicon carbide, carbon nitrogen
One of SiClx, carbon silicon oxynitride, silicon oxynitride, boron nitride or boron carbonitrides are a variety of.
In the present embodiment, the reduction processing 262 also removes the segment thickness of the side wall 231, to expand neighboring gates
The width in gap between structure, reduces the depth-to-width ratio in gap between neighboring gate structures, expands process window to reach, reduces
The purpose of technology difficulty.
Since the etching stop layer 250 covers the side wall 231, and the reduction processing 262 also removes the side
The segment thickness of wall 231, therefore as shown in figure 13, the reduction processing 262 is revealed on removal 230 side wall of dummy gate structure
After etching stop layer 250 out, to expose the side wall 231, being thinned to the side wall 231 is realized.
With reference to Figure 14, after the reduction processing 262, formation be filled in adjacent pseudo- grid structure 230 (as shown in figure 13) it
Between first medium layer 271；Remove dummy gate structure 230, the shape in the first medium layer 271 and the protective layer 261
At gate openings；Metal gate structure 280 is formed in the gate openings；In the metal gate structure 280 and described
Second dielectric layer 272, the second dielectric layer 272, the first medium layer 271 and the guarantor are formed on one dielectric layer 271
Sheath 261 is for constituting the interlayer dielectric layer 270.
Since the protective layer 261 for remaining filled media layer 263 (as shown in figure 11) by forming, the filling is situated between
The material of matter layer 263 is identical as 271 material of first medium layer；Therefore the material of the protective layer 261 and described first is situated between
The material of matter layer 271 is identical, so the protective layer 261 is not necessarily to removal, it can be as one of the interlayer dielectric layer 270
Point, to realize the electric isolution between neighboring gate structures, adjacent semiconductor constructs.Retain the protective layer 261 using as described
A part of interlayer dielectric layer 270, this way can simplify processing step, reduce technology difficulty, be conducive to mentioning for yield
Height is conducive to the improvement of device performance.
With reference to Figure 14 and Figure 15, is formed after the interlayer dielectric layer 270, form contact hole between neighboring gate structures
280, the contact hole 280 runs through the interlayer dielectric layer 270.
In the present embodiment, the contact hole 280 sequentially passes through described between adjacent metal gate structure 280
The etching stop layer 250 is exposed in second medium layer 272, the first medium layer 271 and the protective layer 261, bottom.
In the present embodiment, the contact hole 280 is formed by non-self-aligned technique (Non-SAC).So as shown in figure 14,
It is formed after the interlayer dielectric layer 270, forms contact hole mask layer 291 on the interlayer dielectric layer 270；In the contact
Hard mask layer 292 is formed on hole mask layer 291；Graph layer 293 is formed on the hard mask layer 292, in the graph layer 293
It is open (not indicated in figure) with figure, gap is opposite between the position and adjacent metal gate structure 280 of the figure opening
It answers, and the width of figure opening is less than the width in gap between adjacent metal gate structure 280；As shown in figure 15, with institute
Stating graph layer 293 is exposure mask, is sequentially etched the hard mask layer 292, the contact hole mask layer 291, the second dielectric layer
272, the first medium layer 171 and the protective layer 261 form the contact hole 280.
Correspondingly, the present invention also provides a kind of semiconductor structures.With reference to Fig. 9, it is real to show semiconductor structure one of the present invention
Apply the schematic diagram of the section structure of example.The semiconductor structure includes: substrate, and the substrate includes substrate, is located on the substrate
Gate structure and the etching stop layer that is located at least between neighboring gate structures on substrate；Interlayer dielectric layer is at least filled
Between neighboring gate structures, the interlayer dielectric layer between neighboring gate structures is greater than adjacent far from the width of the substrate side
The width of interlayer dielectric layer between gate structure close to the substrate side.It should be noted that in the present embodiment, described half
Conductor structure has high-K metal gate structure, so the gate structure is metal gate structure 180.
In addition, being formed by semiconductor structure is fin formula field effect transistor, and the substrate includes substrate in the present embodiment
110, fin 120 discrete on the substrate 110 and the source and drain doping in gate structure two sides fin 120
Area, the source and drain doping area include the stressor layers 140 of doping,
Same source and drain doping area is shared and in the present embodiment, between adjacent transistor, that is to say, that the source and drain doping
Area is on the substrate 110 between neighboring gate structures, therefore the stressor layers 140 are located between adjacent pseudo- grid structure 130
In fin 120.
The etching stop layer 150 plays etching stopping in the forming process in subsequent touch hole, to reach guarantor
Protect the purpose in the source and drain doping area.The source and drain doping area is between neighboring gate structures, therefore the etching stop layer
150 are located at least on the substrate 110 between adjacent metal gate structure 180.And in the present embodiment, the source and drain doping area tool
There are stressor layers 140, so the etching stop layer 150 at least covers the stressor layers 140 between adjacent metal gate structure 180.
In the present embodiment, the semiconductor structure is formed by method for forming semiconductor structure of the invention.Therefore described
Etching stop layer 150 also extends on the side wall of at least partly described gate structure；Positioned at 180 side wall of metal gate structure
On etching stop layer 150 through reduction processing, so being located at etching stop layer 150 on 180 side wall of metal gate structure
Surface is ladder-like in single layer, and the thickness far from one side section of substrate is less than the thickness close to one side section of substrate
Degree reduces the depth-to-width ratio in gap between neighboring gate structures, has so as to expand the width in gap between neighboring gate structures
Conducive to the formation process difficulty for reducing the interlayer dielectric layer 170, manufacturing yield is improved.
In the present embodiment, the material of the etching stop layer 150 is silicon nitride.In other embodiments of the invention, the quarter
The material for losing stop-layer 150 can also be the other materials such as silicon oxynitride.
Specifically, being located at the etching stop layer 150 on 180 side wall of metal gate structure, far from the substrate side
The difference of segment thickness and close substrate side segment thickness existsIt arrivesRange.Far from one side of substrate
If the difference of point thickness and close substrate side segment thickness is too big, it is unfavorable for the metal gate structure 180
Protection, it is possible that the phenomenon that metal gate structure 180 is impaired, is unfavorable for the promotion of manufacturing yield and structural behaviour；Far
If too small from substrate side segment thickness and the difference close to substrate side segment thickness, it is unfavorable for expanding phase
The width in gap between adjacent gate structure is unfavorable for reducing the depth-to-width ratio in gap between neighboring gate structures, is likely to result in institute
State the problem of 170 fill process difficulty of interlayer dielectric layer increases, manufacturing yield reduces.
The interlayer dielectric layer 170 fills the gap 181 (as shown in Figure 8) between full neighboring gate structures, for realizing
Electric isolution between adjacent semiconductor constructs, between adjacent metal.As shown in figure 9, in the present embodiment, the etching stop layer
150 extend between the interlayer dielectric layer 170 and the metal gate structure 180, and due to being located at the metal gates
Etching stop layer 150 on 180 side wall of structure is in single layer backwards to the surface of the metal gate structure 180 through reduction processing
Ladder-like, the thickness far from one side section of substrate is less than the thickness close to one side section of substrate, therefore neighboring gates
The side wall in gap is ladder-like in single layer between structure, and the width far from one side section of substrate is greater than close to the substrate one
The width of side, so the side wall of the interlayer dielectric layer being filled between neighboring gate structures towards the gate structure is in single layer rank
Scalariform, and the width far from one side section of substrate is greater than the width close to one side section of substrate.
In the present embodiment, the interlayer dielectric layer 170 includes first between adjacent adjacent metal gate structure 180
Dielectric layer 171 and the second dielectric layer 172 on the first medium layer 171.The side wall of the first medium layer 171 is in single
Layer is ladder-like, and the width far from 110 1 side section of substrate is greater than the width close to 110 1 side section of substrate.
Since the side wall of the first medium layer 171 is ladder-like in single layer, and the width far from 110 1 side section of substrate
Degree is greater than the width close to 110 1 side section of substrate, therefore the fill process difficulty of the first medium layer 171 is lower,
Be conducive to the improvement of manufacturing yield and structural behaviour.
Due to the etching stop layer 150 being located on 180 side wall of metal gate structure, far from one side section of substrate
The difference of thickness and close substrate side segment thickness existsIt arrivesRange.So between neighboring gate structures
Interlayer dielectric layer 170 exist far from substrate side width and close to the difference of substrate side widthIt arrivesIn range, i.e., the described first medium layer 171 is far from substrate side width and close to substrate side width
Difference existsIt arrivesIn range.
The first medium layer 171 and the second dielectric layer 172 are for constituting the interlayer dielectric layer 170.This implementation
In example, the material of the first medium layer 171 and the second dielectric layer 172 is silica.In other embodiments of the invention, institute
State first medium layer 171 and the second dielectric layer 172 material can also selected from silica, silicon nitride and silicon oxynitride etc. its
One of his dielectric material is a variety of.
With reference to Figure 14, the schematic diagram of the section structure of another embodiment of semiconductor structure of the present invention is shown.
Details are not described herein by the present embodiment and the previous embodiment something in common present invention.The present embodiment and previous embodiment are not
It is with place, in the present embodiment, the etching stop layer 250 extends to the interlayer dielectric layer 270 and close to the substrate
Part of grid pole structure between, expose far from the substrate part of grid pole structure.
In the present embodiment, the semiconductor structure further include: mixed for protecting the gate structure and defining the source and drain
The side wall 231 of miscellaneous zone position, the side wall are located at the etching stop layer 250 and the interlayer dielectric layer 270 and the grid
Between structure.
In the present embodiment, the side wall 231 is the silicon nitride of single layer structure.In other embodiments of the invention, the side wall
It can also be laminated construction.In other embodiments of the invention, the material of the side wall can also be silica, silicon carbide, carbon nitrogen
One of SiClx, carbon silicon oxynitride, silicon oxynitride, boron nitride or boron carbonitrides are a variety of.
In the present embodiment, to the reduction processing of the etching stop layer 250, not only reduces and carved far from the substrate side
The thickness for losing stop-layer also removes the segment thickness far from side wall 261 described in the substrate side, so the side wall 231
It is ladder-like in single layer towards the surface of the interlayer dielectric layer 270, and thickness of the side wall 231 far from described substrate one end is small
In the thickness close to described substrate one end, to reach the width for expanding gap between neighboring gate structures, reduce neighboring gates
The depth-to-width ratio purpose in gap between structure.
In the present embodiment, the interlayer dielectric layer includes: the protective layer between neighboring gate structures on substrate 210
261 and the first medium layer 271 on the protective layer 261 and be located at the first medium layer 271 and the grid knot
Second dielectric layer 272 on structure.
The protective layer 261 is used to protect the etching stop layer 250 between neighboring gate structures during reduction processing,
Prevent the etching stop layer 250 impaired.
Due to the protective layer 261 is also used to constitute interlayer dielectric layer 270 to realize between neighboring gate structures, adjacent half
Electric isolution between conductor structure is so the material of the protective layer 261 is identical as the material of the first medium layer 271
Silica.Specifically, the protective layer 261 after the cured processing such as trimethyl silicane alkanamine or polysilane material by forming
Dielectric material.In other embodiments of the invention, the material of the protective layer 261 may be silica, silicon nitride nitrogen oxides
One of equal dielectric materials are a variety of.
In the present embodiment, the thickness of the protective layer 261 is greater thanThe thickness of the protective layer 261 should not be too small.Institute
If the thickness for stating protective layer is too small, the protective layer 261 may be will affect to etching stop layer between neighboring gate structures
250 protective capability is unfavorable for preventing the etching stop layer 250 impaired.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor structure characterized by comprising
Formed substrate, the substrate include substrate, the gate structure on the substrate and be located at neighboring gate structures it
Between etching stop layer on substrate, the etching stop layer also extends on the side wall of the gate structure；
Form protective layer, the etching stop layer between the protective layer covering neighboring gate structures, and grid described in exposed portion
Etching stop layer in structure side wall；
It is formed after the protective layer, reduction processing is carried out to the etching stop layer of exposing.
2. forming method as described in claim 1, which is characterized in that the thickness of the protective layer is greater than
3. forming method as described in claim 1, which is characterized in that the step of forming the protective layer include:
The protected material bed of material is formed, the protected material bed of material is filled between neighboring gate structures, and covers the gate structure；
It returns and carves the protected material bed of material, the etching stop layer on gate structure sidewall described in exposed portion.
4. forming method as described in claim 1, which is characterized in that the protective layer be polysilicon layer, bottom anti-reflection layer,
Organic dielectric layer, spun-on carbon layer or amorphous carbon layer.
5. forming method as described in claim 1, which is characterized in that the substrate further include: filled media layer is filled in phase
Between adjacent gate structure and cover the gate structure；
The step of forming protective layer, which includes: back, carves the filled media layer, the etching on gate structure sidewall described in exposed portion
Stop-layer, remaining filled media layer are used to be used as the protective layer.
6. forming method as described in claim 1, which is characterized in that the material of the etching stop layer is silicon nitride.
7. forming method as described in claim 1, which is characterized in that by way of plasma etching or wet etching
Carry out the reduction processing.
8. forming method as described in claim 1, which is characterized in that the substrate further include: side wall is located at the grid knot
On structure side wall；The etching stop layer covers the side wall；
The reduction processing also removes the segment thickness of the side wall.
9. forming method as claimed in claim 1 or 8, which is characterized in that the etch amount of the reduction processing existsIt arrivesIn range.
10. forming method as described in claim 1, which is characterized in that the forming method further include:
After the reduction processing, the interlayer dielectric layer being filled between neighboring gate structures is formed；
The contact hole for running through the interlayer dielectric layer is formed between neighboring gate structures.
11. forming method as claimed in claim 10, which is characterized in that the technique for forming the interlayer dielectric layer includes: stream
Body chemical vapor phase growing.
12. forming method as claimed in claim 10, which is characterized in that the forming method further include: at the thinned place
After reason, is formed before interlayer dielectric layer, remove the protective layer.
13. forming method as claimed in claim 12, which is characterized in that remove institute by way of wet etching or ashing
State protective layer.
14. a kind of semiconductor structure characterized by comprising
Substrate, the substrate include substrate, the gate structure on the substrate and be located at least in neighboring gate structures it
Between etching stop layer on substrate；
Interlayer dielectric layer is at least filled between neighboring gate structures, and the interlayer dielectric layer between neighboring gate structures is far from institute
The width for stating substrate side is greater than the interlayer dielectric layer between neighboring gate structures close to the width of the substrate side.
15. semiconductor structure as claimed in claim 14, which is characterized in that the interlayer dielectric layer between neighboring gate structures is remote
Exist from substrate side width and close to the difference of substrate side widthIt arrivesIn range.
16. semiconductor structure as claimed in claim 14, which is characterized in that the interlayer dielectric layer court between neighboring gate structures
It is ladder-like in single layer to the side wall of the gate structure.
17. semiconductor structure as claimed in claim 14, which is characterized in that the etching stop layer also extends to the interlayer
Between dielectric layer and at least partly gate structure.
18. semiconductor structure as claimed in claim 17, which is characterized in that the etching stop layer extends to the interlayer and is situated between
Between matter layer and the part of grid pole structure of the close substrate, expose the part of grid pole structure far from the substrate.
19. semiconductor structure as claimed in claim 17, which is characterized in that the substrate further include: side wall is located at the quarter
It loses between stop-layer and the interlayer dielectric layer and the gate structure.
20. semiconductor structure as claimed in claim 19, which is characterized in that thickness of the side wall far from described substrate one end
Less than the thickness close to described substrate one end.
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