CN104122491A - Method for predicting negative bias temperature instability (NBTI) dynamic variation at the end of service life of semiconductor device - Google Patents

Abstract

A method for predicting negative bias temperature instability (NBTI) dynamic variation at the end of service life of a semiconductor device includes acquiring an invalidation rate at the end of service life of the semiconductor device by testing the semiconductor device; acquiring a feature invalidation rate corresponding to some work voltage V<G> by testing a plurality of semiconductor devices; calculating a variance of a mean value of degeneration amount delta V<th> of threshold voltage at the end of service life under different V<G> among different devices, a variance of a variance of the delta V<th> among different devices, and feature invalidation rates corresponding to different V<G>, wherein the work voltage V<G> corresponding to the feature invalidation rates larger than or equal to 0 and smaller than 1 meets work voltage VDD of 10-year service life of the semiconductor device, so that the NBTI dynamic variation at the end of service life of the semiconductor device can be represented. The method for predicting NBTI dynamic variation at the end of service life of the nanoscale semiconductor device is effective.

Description

The method of the dynamic fluctuation of NBTI when prediction semiconductor devices end of life

Technical field

The invention belongs to Reliability Issues of Microelectronics Devices field, the Forecasting Methodology of the dynamic fluctuation of NBTI while relating to nanoscale semiconductor devices end of life.

Background technology

In nanoscale semiconductor devices, the dynamic fluctuation meeting that negative bias thermal instability NBTI (Negative Bias Temperature Instability) introduces directly affects the stability of circuit, and presents the trend increasing gradually along with dwindling of dimensions of semiconductor devices.On the other hand, aging along with semiconductor devices, especially, in the time of the terminal in semiconductor devices life-span, the generation of gate oxide trap, causes the impact of the dynamic fluctuation of NBTI more and more significant.Therefore, the dynamic fluctuation of NBTI under research end of life, and (the Device-to-device variation of the fluctuation between semiconductor devices and semiconductor devices, and fluctuation (the Cycle-to-cycle variation of semiconductor devices between different operating circulation DDV), CCV) all take into account, there is great importance for the circuit design under nanoscale.Still the relevant evaluation method that is not applicable at present nanoscale semiconductor devices proposes, and therefore needs the method for the dynamic fluctuation of NBTI when proposition is a kind of evaluates nanoscale semiconductor devices end of life badly.

Summary of the invention

Term agreement: the end of life occurring herein all refers to the semiconductor devices life-span of the 10th year.

The object of the present invention is to provide a kind of Forecasting Methodology that is applicable to the dynamic fluctuation of NBTI in the time of end of life of nanoscale semiconductor devices.

Under nanoscale, the present invention proposes the dynamic fluctuation of the NBTI of semiconductor devices in the time of end of life and must treat by three-dimensional viewpoint.Due to the impact of CCV and DDV, the normal working voltage VDD that nanoscale semiconductor devices can meet 10 year life-span is no longer definite value, has numerous VDD all can meet the semiconductor devices life requirements of 10 years.The dynamic fluctuation of three-dimensional NBTI during for end of life, a dimension is VDD, under each VDD, the dynamic fluctuation of NBTI when end of life is two-dimensional problems: the fluctuation of the average that dimension is each device degradation between device, another dimension is the fluctuation between device of the variance of each device degradation.

Technical scheme of the present invention is as follows:

A method for the dynamic fluctuation of NBTI while predicting semiconductor devices end of life, is applied to the semiconductor devices of nanoscale, it is characterized in that, first, by the source voltage V of semiconductor devices _swith bulk voltage V _ball the time be set to 0, then, carry out following testing procedure:

The first step, applies voltage V at semiconductor device gate end _gmeasure, drain terminal applies voltage V _dmeasure, the drain terminal electric current I of semiconductor devices before measurement stress _d0; Then apply primary stress voltage V at grid end _{gstress_1}, drain terminal is in zero offset, and stress time is Δ t, applies in process at stress, and gate voltage is at V _{gstress_1}and V _gmeasurebetween cycling jump, simultaneously drain voltage is 0 and V _dmeasurebetween cycling jump; In each circulation, gate voltage is V _{gstress_1}time t ₀maximal value be less than 10ms; When gate voltage is V _gmeasure, drain voltage is V _dmeasuretime monitor leakage current I _d, the corresponding I of above-mentioned circulation each time _dmonitoring, this is defined as to a test loop;

Second step, the stress voltage applying at grid end doubly increases with K, K>1, i.e. V _{gstress_2}=KV _{gstress_1}, drain terminal is still in zero offset, and stress time is still Δ t, applies in process at stress, and gate voltage is at V _{gstress_2}and V _gmeasurebetween cycling jump, simultaneously drain voltage is 0 and V _dmeasurebetween cycling jump, in each circulation, gate voltage is in V _{gstress_2}and V _gmeasuretime identical with first step correspondence; When gate voltage is V _gmeasure, drain voltage is V _dmeasureshi Jixu monitoring leakage current I _d; And then the stress voltage of grid end is doubly increased with K, repeated test, obtains the test result of N time, wherein V _{gstress_N}=K ^(N-1)v _{gstress_1}, the applying method of drain voltage applying method and the first step is identical; Carry out continuously from the process of the 1st time to the N time, do not have interval; The amount of degradation Δ V of threshold voltage _thobtained by formula below:

${\mathrm{\&Delta;V}}_{\mathrm{th}}=\frac{I_{D0}-I_D}{I_{D0}}(V_{\mathrm{Gmeasure}}-V_{\mathrm{th}0})---\left(1\right)$

Wherein, I _dthe leakage current at every turn measuring after stress application, V _th0it is the threshold voltage of semiconductor devices before stress;

The 3rd step, due to the degeneration Δ V of NBTI stress threshold voltages _thmeet,

${\mathrm{\&Delta;V}}_{\mathrm{th}}={\mathrm{AV}}_{\mathrm{Gstress}}^m{t}^n---\left(2\right)$

Wherein, A is preposition coefficient, and m is the exponential factor of grid end stress voltage, V _gstressbe the stress voltage applying at grid end, n is the exponential factor of stress time, and t is the added total stress time of grid end; By V in the first step _{gstress_1}under, Δ V _thwith the data of stress time t, carry out power function fitting according to formula (2), obtain corresponding n value and ;

The 4th step, by the 2nd time to the Δ V obtaining under N secondary stress _thequivalence is transformed into V (identical threshold voltage amount of degradation) _{gstress_1}under threshold voltage degenerate, as shown in formula (3):

Wherein t _{0_i}under every secondary stress, i the time that gate voltage corresponding to test loop is stress voltage;

The 2nd time to stress time t corresponding to each test loop under N secondary stress ₀be transformed into V _{gstress_1}under the equivalent stress time, as shown in formula (4):

$\begin{array}{c}{t}_{\mathrm{eff}\_1}(2\&RightArrow;1)=K^{(2-1)\&CenterDot;\frac{m}{n}}\&CenterDot;t_{0\_1}\\ .\\ .\\ .\\ t_{\mathrm{eff}\_i}(2\&RightArrow;1)=K^{(2-1)\&CenterDot;\frac{m}{n}}\&CenterDot;t_{0\_i}\\ .\\ .\\ .\\ t_{\mathrm{eff}\_1}(N\&RightArrow;1)=K^{(N-1)\&CenterDot;\frac{m}{n}}\&CenterDot;t_{0\_1}\\ .\\ .\\ .\\ t_{\mathrm{eff}\_i}(N\&RightArrow;1)=K^{(N-1)\&CenterDot;\frac{m}{n}}\&CenterDot;t_{0\_i}\end{array}---\left(4\right)$

After conversion, total stress time t that i test loop of j secondary stress is corresponding _jifor:

$t_{\mathrm{ji}}=\mathrm{\&Delta;t}+\underset{p=2}{\overset{j-1}{\mathrm{\&Sigma;}}}\underset{q=1}{\overset{C}{\mathrm{\&Sigma;}}}{t}_{\mathrm{eff}\_q}(p\&RightArrow;1)+\underset{q=1}{\overset{i}{\mathrm{\&Sigma;}}}{t}_{\mathrm{eff}\_q}(j\&RightArrow;1)---\left(5\right)$

Wherein, C is the number of times of test loop under stress each time; Make so threshold voltage that originally stress increases gradually degenerate to change into constant stress that (stress intensity is V _{gstress_1}) lower total stress time is t _jithreshold voltage degenerate;

The 5th step, by the total stress time t after conversion _ji, calculate rear Δ V corresponding to i test loop of j secondary stress of conversion according to formula (2) _{after th conversion-ji}:

The Δ V that conversion front and back are total _thbetween error be:

Wherein, C is the number of times of test loop under stress each time, Δ V _{before th conversion-ji}the I measuring for changing i test loop of front j secondary stress _daccording to the threshold voltage amount of degradation of formula (1) conversion; The error E rror obtaining is the function of m; Span to m travels through, and obtains optimum m value by minimum error E rror; Obtained by the 3rd step calculate A value;

The 6th step, the n value that the m value drawing according to the 5th step and A value and the 3rd step draw, is transformed into V _{gstress_1}lower total equivalent stress time is

$t_{V_{\mathrm{Gstress}1}}=\mathrm{\&Delta;t}+\underset{p=2}{\overset{N}{\mathrm{\&Sigma;}}}\underset{q=1}{\overset{C}{\mathrm{\&Sigma;}}}{t}_{\mathrm{eff}\_q}(p\&RightArrow;1)---\left(8\right)$

Equally, this equivalent stress time, according to formula (9), can be transformed into any operating voltage V _gunder the equivalent stress time:

$t_{V_G}=t_{V_{\mathrm{Gstress}\_1}}\&CenterDot;V_{\mathrm{Gstress}\_1}^{m/n}/V_G^{m/n}---\left(9\right)$

The 7th step, as threshold voltage amount of degradation Δ V _thbe transformed into a certain operating voltage V _gafter, get 10 years corresponding Δ V _th(in order to reflect the impact of CCV, need about 10 years, respectively get successively M Δ V _th(determining of M value needs to meet and can just reflect Δ V _ththe amplitude of fluctuation, the i.e. level of CCV, and it is very large to be unlikely to M value)) distribution, and then can obtain this semiconductor devices Δ V that degenerates in the time of end of life _thaverage and variance, and the inefficacy probability of semiconductor devices in the time of end of life, i.e. Δ V _thmeet the probability of inefficacy criterion;

The 8th step repeats said process on the semiconductor devices of multiple same size same process, with the identical operating voltage V of the 7th step _gunder, obtain respectively one group of Δ V _thaverage and variance, and inefficacy probability; At this V _gunder, and then can obtain Δ V _ththe variance of average between different components, and Δ V _ththe variance of variance between different components, and the average of inefficacy probability between different components, is designated as this V _gcharacteristic of correspondence inefficacy probability;

The 9th step, repeats the 7th step and the 8th step, Δ V _thbe transformed into other V _gunder, obtain different V _glower Δ V _ththe variance of average between different components, and Δ V _ththe variance of variance between different components, and different V _gcharacteristic of correspondence inefficacy probability; Correspondence is more than or equal to 0 and be less than the operating voltage V of 1 feature inefficacy probability _gmeet the semiconductor devices operating voltage VDD in 10 year life-span; Like this, the dynamic fluctuation of NBTI in the time of semiconductor devices end of life just can characterize out; In practical operation, concrete VDD value can be determined by the feature inefficacy probability of target call.

Preferred:

When described prediction semiconductor devices end of life, the method for the dynamic fluctuation of NBTI, is characterized in that, in the first step, and the voltage V applying at semiconductor device gate end _gmeasurevalue is V _th0± 10mV.

When described prediction semiconductor devices end of life, the method for the dynamic fluctuation of NBTI, is characterized in that, in the first step, and the voltage V applying at drain terminal _dmeasurevalue need meet semiconductor devices in linear zone.

When described prediction semiconductor devices end of life, the method for the dynamic fluctuation of NBTI, is characterized in that, in the first step, and the t of each circulation ₀can be identical, also can be different; Gate voltage is in V _gmeasurewith in V _{gstress_1}the ratio of time be less than 10%.

When described prediction semiconductor devices end of life, the method for the dynamic fluctuation of NBTI, is characterized in that, in the 5th step, the span of described m is 0～10.

When described prediction semiconductor devices end of life, the method for the dynamic fluctuation of NBTI, is characterized in that, the inefficacy criterion described in the 7th step is: Δ V _th=50mV.

When described prediction semiconductor devices end of life, the method for the dynamic fluctuation of NBTI, is characterized in that, the semiconductor devices of same size same process described in the 8th step needs at least 30.

When described prediction semiconductor devices end of life, the method for the dynamic fluctuation of NBTI, is characterized in that, in test process, temperature remains on 125 degrees Celsius.

Forecasting Methodology provided by the present invention, has considered the impact of CCV and DDV, and the dynamic fluctuation of NBTI during end of life is created as a three-dimensional problem.By introducing new method of testing, under the different operating voltage of semiconductor devices, the dynamic fluctuation of three-dimensional NBTI when end of life all can be obtained.Therefore the effective Forecasting Methodology of the dynamic fluctuation of NBTI while the invention provides nanoscale semiconductor devices end of life.

Brief description of the drawings

Fig. 1 is four end semiconductor devices schematic diagram.

Fig. 2 is the schematic diagram of nanoscale semiconductor devices dynamic fluctuation of three-dimensional NBTI in the time of end of life.For each semiconductor devices, Δ V _ththe depth representing Δ V of corresponding color _thdistribution, color is darker, represents Δ V _thlarger at this place's probability.

Fig. 3 is the schematic diagram of the Test extraction semiconductor devices clock signal that in the dynamic fluctuation process of three-dimensional NBTI, semiconductor device gate end and drain terminal apply when the end of life, the clock signal that wherein (a) semiconductor devices drain terminal applies; (b) clock signal that semiconductor device gate end applies; (c) heavily stressed (V _{gstress_2}..., V _{gstress_N}) under stress time forward (V under low stress to _{gstress_1}) equivalent stress time diagram.

Fig. 4 is by Δ V _thbe transformed into any V _gafter, extract this V _gunder, at the two-dimentional fluctuation of end of life and the schematic diagram of inefficacy probability.

Fig. 5 is the two-dimentional fluctuation of single semiconductor devices in the time of end of life of the extracting variation relation with VDD.

Embodiment

Below by embodiment also by reference to the accompanying drawings, describe Forecasting Methodology of the present invention in detail.

Framework structure, testing procedure and data processing method are as follows:

Framework builds part:

The object of this part is the dynamic fluctuation problem of three-dimensional NBTI while building semiconductor devices end of life.As shown in Figure 2, under nanoscale, the dynamic fluctuation of the NBTI of semiconductor devices in the time of end of life must be treated by three-dimensional viewpoint.Due to the impact of CCV and DDV, the normal working voltage VDD that nanoscale semiconductor devices can meet 10 year life-span is no longer definite value.The dynamic fluctuation of three-dimensional NBTI during for end of life, a dimension is VDD, can ensure under the VDD in 10 year life-span at each, the dynamic fluctuation of NBTI when end of life is two-dimensional problems: the fluctuation of the average that dimension is each device degradation between device, another dimension is the fluctuation between device of the variance of each device degradation.

Part of detecting (process of the dynamic fluctuation of NBTI when testing procedure described below is P-type semiconductor device detection and extraction end of life, the semiconductor devices of test is as shown in Figure 1; Source and body end in test process all in zero offset; Probe temperature remains on general 125 degrees Celsius of industry):

1) object of this step is to obtain the leakage current of the front semiconductor devices of stress under test voltage.Apply test voltage V at grid end _gmeasure(conventionally at threshold voltage V _th0near), apply test voltage V at drain terminal _dmeasure(value need meet semiconductor devices in linear zone), the leakage current I of semiconductor devices before measurement stress _d0.

2) object of this step is to obtain the drain current degradation under stress for the first time.Apply primary stress voltage V at grid end _{gstress_1}, drain terminal is in zero offset, and stress time is Δ t.Apply in process at stress, gate voltage is at V _{gstress_1}and V _gmeasurebetween cycling jump, simultaneously drain voltage is 0 and V _dmeasurebetween cycling jump.In each circulation, gate voltage is V _{gstress_1}time maximum be less than 10ms.The t of each circulation ₀can be identical, also can be different.Gate voltage is in V _gmeasurewith in V _{gstress_1}the ratio of time be less than 10%.When gate voltage is V _gmeasure, drain voltage is V _dmeasuretime monitor leakage current I _d, as shown in Figure 3, the therefore corresponding I of above-mentioned circulation each time _dmonitoring, this is defined as a test loop.

3) object of this step is to obtain the 2nd secondary stress to the drain current degradation under the N time (N is predefined value).The stress voltage applying at grid end doubly increases with K, i.e. V _{gstress_2}=KV _{gstress_1}, drain terminal is still in zero offset, and stress time is still Δ t.Apply in process at stress, gate voltage is at V _{gstress_2}and V _gmeasurebetween cycling jump, simultaneously drain voltage is 0 and V _dmeasurebetween cycling jump, in each circulation, gate voltage is in V _{gstress_2}and V _gmeasuretime identical with first step correspondence.When gate voltage is V _gmeasure, drain voltage is V _dmeasureshi Jixu monitoring leakage current I _d.And then the stress voltage of grid end is doubly increased with K, repeated test, obtains the test result of N time, wherein V _{gstress_N}=K ^(N-1)v _{gstress_1}, the applying method of drain voltage applying method and the first step is identical.There is not interval in the process from 1 to N, need carry out continuously, as shown in Figure 3.Leakage current I _ddegeneration change into the degeneration Δ V of threshold voltage by formula (1) _th.

Data processing method part:

1) after test finishes, by V _{gstress_1}under, Δ V _thwith the data of stress time t, carry out power function fitting according to formula (2), obtain corresponding n value and ;

2), according to formula (4), convert V by the 2nd time to the stress time under N secondary stress _{gstress_1}under the equivalent stress time (being the function of m).After conversion, total stress time t that i test loop of j secondary stress is corresponding _jican be drawn by formula (5).Then according to formula (6) and formula (7), calculate the total Δ V in conversion front and back _thbetween error.The error E rror obtaining is the function of m.Span (0～10) to m travels through, and obtains optimum m value by minimum error E rror.By step 1) obtain calculate A value.So, three unknown quantitys in formula (2), are all obtained, and then can be by formula (8) and formula (9), by V _{gstress_1}under the equivalent stress time be transformed into any operating voltage V _gunder the equivalent stress time.

3) as threshold voltage amount of degradation Δ V _thbe transformed into a certain operating voltage V _gafter, as shown in Figure 4, get 10 years corresponding Δ V _th(in order to reflect the impact of CCV, need about 10 years, respectively get successively M Δ V _th(M meets the Δ V taking out _threlative standard's variance equal Δ V under all stress times _ththe minimum number of relative standard's variance)) distribution, and then can obtain this semiconductor devices (Δ V that degenerates in the time of end of life _th) average and variance, and the inefficacy probability of semiconductor devices in the time of end of life, i.e. Δ V _thbe greater than inefficacy criterion and (be generally Δ V _th=50mV) probability.Upper at multiple similar devices (at least 30), repeat said process.And then can obtain Δ V _ththe variance of average between different components, and Δ V _ththe variance of variance between different components, and the average of inefficacy probability between different components, is designated as this V _gcharacteristic of correspondence inefficacy probability.Change the V being transformed into _g, repeat said process, and then can obtain different V _gunder, Δ V _thvariance and the Δ V of average between different components _ththe variance (as shown in Figure 5) of variance between different components, and feature inefficacy probability.The operating voltage V of character pair inefficacy probability (0≤feature inefficacy probability <1) _gmeet the semiconductor devices operating voltage VDD in 10 year life-span.Like this, the dynamic fluctuation of three-dimensional NBTI in the time of semiconductor devices end of life, can well characterize out.In practical operation, concrete VDD value can be determined by the feature inefficacy probability of target call.

Above-described embodiment is not intended to limit the present invention, and any those skilled in the art without departing from the spirit and scope of the present invention, can do various changes and retouching, and protection scope of the present invention defines depending on claim scope.

Claims (8)

1. a method for the dynamic fluctuation of NBTI while predicting semiconductor devices end of life, is applied to the semiconductor devices of nanoscale, it is characterized in that, first, by the source voltage V of semiconductor devices _swith bulk voltage V _ball the time be set to 0, then, carry out following testing procedure:

The first step, applies voltage V at semiconductor device gate end _gmeasure, drain terminal applies voltage V _dmeasure, the drain terminal electric current I of semiconductor devices before measurement stress _d0; Then apply primary stress voltage V at grid end _{gstress_1}, drain terminal is in zero offset, and stress time is Δ t, applies in process at stress, and gate voltage is at V _{gstress_1}and V _gmeasurebetween cycling jump, simultaneously drain voltage is 0 and V _dmeasurebetween cycling jump; In each circulation, gate voltage is V _{gstress_1}time t ₀maximal value be less than 10ms; When gate voltage is V _gmeasure, drain voltage is V _dmeasuretime monitor leakage current I _d, the corresponding I of above-mentioned circulation each time _dmonitoring, this is defined as to a test loop;

Second step, the stress voltage applying at grid end doubly increases with K, K>1, i.e. V _{gstress_2}=KV _{gstress_1}, drain terminal is still in zero offset, and stress time is still Δ t, applies in process at stress, and gate voltage is at V _{gstress_2}and V _gmeasurebetween cycling jump, simultaneously drain voltage is 0 and V _dmeasurebetween cycling jump, in each circulation, gate voltage is in V _{gstress_2}and V _gmeasuretime identical with first step correspondence; When gate voltage is V _gmeasure, drain voltage is V _dmeasureshi Jixu monitoring leakage current I _d; And then the stress voltage of grid end is doubly increased with K, repeated test, obtains the test result of N time, wherein V _{gstress_N}=K ^(N-1)v _{gstress_1}, the applying method of drain voltage applying method and the first step is identical; Carry out continuously from the process of the 1st time to the N time, do not have interval; The amount of degradation Δ V of threshold voltage _thobtained by formula below:

${\mathrm{\&Delta;V}}_{\mathrm{th}}=\frac{I_{D0}-I_D}{I_{D0}}(V_{\mathrm{Gmeasure}}-V_{\mathrm{th}0})---\left(1\right)$

Wherein, I _dthe leakage current at every turn measuring after stress application, V _th0it is the threshold voltage of semiconductor devices before stress;

The 3rd step, due to the degeneration Δ V of NBTI stress threshold voltages _thmeet,

${\mathrm{\&Delta;V}}_{\mathrm{th}}={\mathrm{AV}}_{\mathrm{Gstress}}^m{t}^n---\left(2\right)$

Wherein, A is preposition coefficient, and m is the exponential factor of grid end stress voltage, V _gstressbe the stress voltage applying at grid end, n is the exponential factor of stress time, and t is the added total stress time of grid end; By V in the first step _{gstress_1}under, Δ V _thwith the data of stress time t, carry out power function fitting according to formula (2), obtain corresponding n value and ;

The 4th step, by the 2nd time to the Δ V obtaining under N secondary stress _thbe transformed into equivalently V _{gstress_1}under threshold voltage degenerate, as shown in formula (3):

Wherein t _{0_i}under every secondary stress, i the time that gate voltage corresponding to test loop is stress voltage;

The 2nd time to stress time t corresponding to each test loop under N secondary stress ₀be transformed into V _{gstress_1}under the equivalent stress time, as shown in formula (4):

$\begin{array}{c}{t}_{\mathrm{eff}\_1}(2\&RightArrow;1)=K^{(2-1)\&CenterDot;\frac{m}{n}}\&CenterDot;t_{0\_1}\\ .\\ .\\ .\\ t_{\mathrm{eff}\_i}(2\&RightArrow;1)=K^{(2-1)\&CenterDot;\frac{m}{n}}\&CenterDot;t_{0\_i}\\ .\\ .\\ .\\ t_{\mathrm{eff}\_1}(N\&RightArrow;1)=K^{(N-1)\&CenterDot;\frac{m}{n}}\&CenterDot;t_{0\_1}\\ .\\ .\\ .\\ t_{\mathrm{eff}\_i}(N\&RightArrow;1)=K^{(N-1)\&CenterDot;\frac{m}{n}}\&CenterDot;t_{0\_i}\end{array}---\left(4\right)$

After conversion, total stress time t that i test loop of j secondary stress is corresponding _jifor:

$t_{\mathrm{ji}}=\mathrm{\&Delta;t}+\underset{p=2}{\overset{j-1}{\mathrm{\&Sigma;}}}\underset{q=1}{\overset{C}{\mathrm{\&Sigma;}}}{t}_{\mathrm{eff}\_q}(p\&RightArrow;1)+\underset{q=1}{\overset{i}{\mathrm{\&Sigma;}}}{t}_{\mathrm{eff}\_q}(j\&RightArrow;1)---\left(5\right)$

Wherein, C is the number of times of test loop under stress each time; Making so threshold voltage that originally stress increases gradually degenerate and changing into stress time total under constant stress is t _jithreshold voltage degenerate;

The 5th step, by the total stress time t after conversion _ji, calculate rear Δ V corresponding to i test loop of j secondary stress of conversion according to formula (2) _{after th conversion-ji}:

The Δ V that conversion front and back are total _thbetween error be:

Wherein, C is the number of times of test loop under stress each time, Δ V _{before th conversion-ji}the I measuring for changing i test loop of front j secondary stress _daccording to the threshold voltage amount of degradation of formula (1) conversion; The error E rror obtaining is the function of m; Span to m travels through, and obtains optimum m value by minimum error E rror; Obtained by the 3rd step calculate A value;

The 6th step, the n value that the m value drawing according to the 5th step and A value and the 3rd step draw, is transformed into V _{gstress_1}lower total equivalent stress time is

$t_{V_{\mathrm{Gstress}1}}=\mathrm{\&Delta;t}+\underset{p=2}{\overset{N}{\mathrm{\&Sigma;}}}\underset{q=1}{\overset{C}{\mathrm{\&Sigma;}}}{t}_{\mathrm{eff}\_q}(p\&RightArrow;1)---\left(8\right)$

Equally, this equivalent stress time, according to formula (9), can be transformed into any operating voltage V _gunder the equivalent stress time:

$t_{V_G}=t_{V_{\mathrm{Gstress}\_1}}\&CenterDot;V_{\mathrm{Gstress}\_1}^{m/n}/V_G^{m/n}---\left(9\right)$

The 7th step, as threshold voltage amount of degradation Δ V _thbe transformed into a certain operating voltage V _gafter, get 10 years corresponding Δ V _thdistribution, and then can obtain this semiconductor devices Δ V that degenerates in the time of end of life _thaverage and variance, and the inefficacy probability of semiconductor devices in the time of end of life, i.e. Δ V _thmeet the probability of inefficacy criterion;

The 8th step repeats said process on the semiconductor devices of multiple same size same process, with the identical operating voltage V of the 7th step _gunder, obtain respectively one group of Δ V _thaverage and variance, and inefficacy probability; At this V _gunder, and then can obtain Δ V _ththe variance of average between different components, and Δ V _ththe variance of variance between different components, and the average of inefficacy probability between different components, is designated as this V _gcharacteristic of correspondence inefficacy probability;

The 9th step, repeats the 7th step and the 8th step, Δ V _thbe transformed into other V _gunder, obtain different V _glower Δ V _ththe variance of average between different components, and Δ V _ththe variance of variance between different components, and different V _gcharacteristic of correspondence inefficacy probability; Correspondence is more than or equal to 0 and be less than the operating voltage V of 1 feature inefficacy probability _gmeet the semiconductor devices operating voltage VDD in 10 year life-span; Like this, the dynamic fluctuation of NBTI in the time of semiconductor devices end of life just can characterize out.

2. the method for the dynamic fluctuation of NBTI when prediction semiconductor devices end of life as claimed in claim 1, is characterized in that, in the first step, and the voltage V applying at semiconductor device gate end _gmeasurevalue is V _th0± 10mV.

3. the method for the dynamic fluctuation of NBTI when prediction semiconductor devices end of life as claimed in claim 1, is characterized in that, in the first step, and the voltage V applying at drain terminal _dmeasurevalue need meet semiconductor devices in linear zone.

4. the method for the dynamic fluctuation of NBTI when prediction semiconductor devices end of life as claimed in claim 1, is characterized in that, in the first step, and the t of each circulation ₀can be identical, also can be different; Gate voltage is in V _gmeasurewith in V _{gstress_1}the ratio of time be less than 10%.

5. the method for the dynamic fluctuation of NBTI when prediction semiconductor devices end of life as claimed in claim 1, is characterized in that, in the 5th step, the span of described m is 0～10.

6. the method for the dynamic fluctuation of NBTI when prediction semiconductor devices end of life as claimed in claim 1, is characterized in that, the inefficacy criterion described in the 7th step is: Δ V _th=50mV.

7. the method for the dynamic fluctuation of NBTI when prediction semiconductor devices end of life as claimed in claim 1, is characterized in that, the semiconductor devices of same size same process described in the 8th step needs at least 30.

8. the method for the dynamic fluctuation of NBTI when prediction semiconductor devices end of life as claimed in claim 1, is characterized in that, in test process, temperature remains on 125 degrees Celsius.