CN104103537A - Method for effectively controlling over-etching amount - Google Patents
Method for effectively controlling over-etching amount Download PDFInfo
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- CN104103537A CN104103537A CN201310113918.2A CN201310113918A CN104103537A CN 104103537 A CN104103537 A CN 104103537A CN 201310113918 A CN201310113918 A CN 201310113918A CN 104103537 A CN104103537 A CN 104103537A
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- etching
- stop layer
- dielectric
- test structure
- etching stop
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
Abstract
The invention provides a method for effectively controlling over-etching amount. A test structure which comprises, from the bottom to the top in turn, a substrate, an etching stop layer, an interlayer dielectric layer and a hard mask is provided. Thickness of the etching stop layer is consistent with that of a device to be etched. Then the test structure is etched by adopting a preset etching condition so that multiple blind holes used for interconnection are formed. Then the longitudinal section profile of the test structure after being etched is tested. If the lower surface of the blind holes is lower than the lower surface of the etching stop layer, and distance between the lower surface of the blind holes and the lower surface of the etching stop layer is less than or equal to preset over-etching amount, the device to be etched is etched by adopting the preset etching condition. The etching stop layer does not need to be thickened via special sample preparation, and a pre-copper-plating layer is not needed so that a detection method for over-etching amount is simple, and technology adjustment cost is substantially reduced. Besides, an online etching technology can be monitored in real time so that over-etching amount of interconnection through holes can be effectively controlled, and product yield rate is guaranteed.
Description
Technical field
The invention belongs to field of semiconductor manufacture, relate to a kind of technique method of adjustment, particularly relate to a kind of method of effective control over etching amount.
Background technology
Along with integrated circuit CMOS technology according to Moore's Law high speed development, interconnect delay replaces gradually device and postpones to become the key factor that affects chip performance.Parasitic capacitance between interconnection and interconnection resistance have caused the transmission delay of signal.Because copper has lower resistivity, superior electromigration resistance properties and high reliability, can reduce the interconnection resistance of metal, and then reduce total interconnect delay effect, now changes into low-resistance copper-connection by conventional aluminium interconnection.The electric capacity simultaneously reducing between interconnection can reduce to postpone equally, and parasitic capacitance C is proportional to the relative dielectric constant k of circuit layer dielectric, therefore uses low-k materials to replace traditional SiO as the dielectric of different circuit layers
2medium has become the needs of the development that meets high-speed chip.Therefore copper/low-K dielectric system has replaced traditional Al/SiO gradually
2system becomes the main flow of industry.
Do not limit in stereochemical structure in multilayer, between two interlayer dielectric layers, generally include etching stop layer, the effect of etching stop layer is that the etching depth of groove or through hole is accurately controlled and unification.If there is no etching stop layer, due to inhomogeneities, micro loading effect and the depth-to-width ratio effect etc. of dry etching, can make etching depth be difficult to control and inconsistent.Etching stop layer also has the function of copper diffusion barrier.But etching stop layer can increase electric capacity and layer capacitance between wire, when process node enters into 28 nanometers, (the back-end of line of line after semiconductor, BEOL) in, postpone in order to reduce RC (resistance capacitance delay), extensively adopt low k dielectric or super low k dielectric as inter-level dielectric, the thickness of etching stop layer (Etch Stop Layer, ESL) also constantly reduces.
In the Wiring technique of metal interconnecting wires, now generally adopt double damask structure technique: first in dielectric layer, output interconnection channel and through hole, then by electroplating or electroless copper cement copper in interconnection channel and through hole, recycling chemico-mechanical polishing (CMP) grinds off crossing the copper of filling out.The through-hole interconnection of etching runs through etching stop layer and drops on lower layer of copper surface, necessary over etching can ensure that the copper interconnecting line of subsequent deposition and the copper of lower floor can contact, but due to the very thin thickness of etching stop layer, control over etching amount and seem particularly important, because too much over etching can form damage to the copper of lower floor, form therein the defects such as cavity, weaken copper interconnecting line and being connected between it, the reliability of device is reduced.
A kind of method of traditional detection through hole over etching amount is to thicken the etching stopping layer thickness between super low k dielectric and lower floor's copper by twice or three times, and the degree of depth of detection etch is determined over etching amount, but this method need to repeat the technique of deposition-etch stop-layer on production line twice or three times, test structure needs special making, can not use the product of normal process flow to go judgement, therefore very inconvenient, and can not carry out the Real-Time Monitoring on line.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide a kind of method of effective control over etching amount, be used for solving prior art because etching stop layer is very thin, too much over etching can damage the copper of lower floor and the very inconvenient problem of method of existing detection over etching amount.
For achieving the above object and other relevant objects, the invention provides a kind of method of effective control over etching amount, at least comprise the following steps:
S1 a: test structure is provided, and described test structure comprises substrate, etching stop layer, interlayer dielectric layer and hard mask from bottom to top successively; The thickness of described etching stop layer is identical with the thickness of etching stop layer corresponding in device to be etched;
S2: form default etching pattern on described hard mask, then adopt default etching condition to carry out etching to described test structure, form some blind holes for interconnecting in described test structure;
S3: the longitudinal section pattern of the test structure after test etching, if the lower surface of described blind hole is lower than the lower surface of described etching stop layer, and the distance between the lower surface of described blind hole and described etching stop layer lower surface is less than or equal to default over etching amount, adopt described default etching condition to treat etched features and carry out etching, if do not meet, enter step S4;
S4: regulate the parameter in described default etching condition, and repeating step S1 ~ S3.
Alternatively, the etching stop layer in described test structure is identical with the preparation technology of etching stop layer corresponding in described device to be etched.
Alternatively, in described step S3, adopt the longitudinal section pattern of the test structure after scanning electron microscopy or transmission electron microscope test etching.
Alternatively, in described step S4, the parameter in described default etching condition comprises etch period.
Alternatively, described etching is plasma etching.
Alternatively, the material of described inter-level dielectric is low k dielectric or super low k dielectric, and described low k dielectric meets k<3, and described super low k dielectric meets k<2.5.
Alternatively, the material of described substrate is low k dielectric or super low k dielectric, and described low k dielectric meets k<3, and described super low k dielectric meets k<2.5.
Alternatively, the thickness range of described etching stop layer is 200 ~ 400 dusts.
As mentioned above, the method of effective control over etching amount of the present invention, there is following beneficial effect: consistent with practical devices of the thickness of etching stop layer in test structure of the present invention, its preparation technology is identical with the preparation technology of etching stop layer corresponding in device to be etched on actual time line, and do not need pre-copper plate, detection method is simple, has reduced the cost that technique is adjusted.The present invention can effectively control the over etching amount of through-hole interconnection, reduces damage to lower floor's copper, ensures to be effectively connected between copper interconnecting line and lower floor's copper the reliability of raising device, and etching technics on can Real-Time Monitoring line, the yield of guarantee product.
Brief description of the drawings
Fig. 1 is shown as the flow chart of the method for effective control over etching amount of the present invention.
Fig. 2 is shown as the schematic diagram of test structure in the method for effective control over etching amount of the present invention.
Fig. 3 is shown as the schematic diagram that forms blind hole in the method for effective control over etching amount of the present invention in test structure.
Element numbers explanation
S1 ~ S4 step
1 substrate
2 etching stop layers
3 interlayer dielectric layers
4 hard masks
5 blind holes
Embodiment
Below, by specific instantiation explanation embodiments of the present invention, those skilled in the art can understand other advantages of the present invention and effect easily by the disclosed content of this specification.The present invention can also be implemented or be applied by other different embodiment, and the every details in this specification also can be based on different viewpoints and application, carries out various modifications or change not deviating under spirit of the present invention.
Refer to Fig. 1 to Fig. 3.It should be noted that, the diagram providing in the present embodiment only illustrates basic conception of the present invention in a schematic way, satisfy and only show with assembly relevant in the present invention in graphic but not component count, shape and size drafting while implementing according to reality, when its actual enforcement, kenel, quantity and the ratio of each assembly can be a kind of random change, and its assembly layout kenel also may be more complicated.
First refer to Fig. 1, as shown in the figure, be shown as the flow chart of the method for effective control over etching amount of the present invention, the method for effective control over etching amount of the present invention at least comprises the following steps:
Step S1: refer to Fig. 2, as shown in the figure, provide a test structure, described test structure comprises substrate 1, etching stop layer 2, interlayer dielectric layer 3 and hard mask 4 from bottom to top successively; The thickness of described etching stop layer 2 is identical with the thickness of etching stop layer corresponding in device to be etched;
Concrete, in the present embodiment, first provide and wafer identical on real-time production line, but need not pass through pre-copper facing.It is to be noted, so-called identical wafer refers to that described wafer has experienced and technological process identical before device copper facing to be etched herein, on described wafer, can comprise the parts of making, in the present embodiment, described substrate 1 under being from level to level between medium, under it, also can there is the structures such as lower one deck copper-connection.The material of described substrate 1 is low k dielectric or super low k dielectric, and described low k dielectric meets k<3, and described super low k dielectric meets k<2.5.Then adopt the preparation technology of etching stop layer on actual time line to prepare etching stop layer 2 on described substrate 1, the etching stop layer 2 in described test structure is identical with the thickness of etching stop layer corresponding in device to be etched on real-time production line.And then employing forms successively interlayer dielectric layer 3 and hard mask 4 with the preparation technology of last layer interlayer dielectric layer corresponding in device to be etched on actual time line, hard mask on described etching stop layer 2.Therefore, the thickness of etching stop layer 2, interlayer dielectric layer 3 and hard mask 4 on described substrate 1 is identical with etching stop layer, last layer interlayer dielectric layer and hard mask thickness in device to be etched respectively, be to there is the copper layer of preplating under the etching stop layer of described device to be etched, and under the etching stop layer of described test structure, be substrate.Described substrate 1, etching stop layer 2, interlayer dielectric layer 3 and hard mask 4 common formation test structure of the present invention.
Concrete, the material of described inter-level dielectric 3 is low k dielectric or super low k dielectric, and described low k dielectric meets k<3, and described super low k dielectric meets k<2.5.The thickness range of described etching stop layer is 200 ~ 400 dusts.
Test structure of the present invention is without the thickness that thickens etching stop layer 2 by special sample preparation, and need not pass through pre-copper facing, and in follow-up etching process, over etching degree can directly reflect in described substrate 1.
Step S2: refer to Fig. 3, as shown in the figure, form default etching pattern on described hard mask 4, then adopt default etching condition to carry out etching to described test structure, form some blind holes 5 for interconnecting in described test structure;
Concrete, described etching is plasma etching.In the present embodiment, adopt C
4f
8as inter-level dielectric 3 described in reacting gas etching and described etching stop layer 2.In other embodiments, described etching gas can also be CF
4, CHF
3deng.
In the etching of the through-hole interconnection of practical devices, appropriate over etching can ensure can be connected between the copper layer of copper interconnecting line and lower floor.Due to the very thin thickness of etching stop layer, in the device to be etched of reality, be easy to over etching too many, and copper is difficult to be etched, too much plasma bombardment can damage the copper layer of lower floor, form therein the defects such as cavity, thereby weaken being connected between copper interconnecting line and copper layer, reduce the reliability of device.And due to the unsteadiness of etching, the etching condition of previously having established may be not suitable for current situation.Therefore need to monitor at any time the over etching amount on actual time line, to adjust etch technological condition, ensure the yield of product.
In the present invention, described default etching condition comprises the etching parameters such as etching gas flow, etching power, etch period.In the situation that other etching parameters is constant, the blind hole depth etching and etch period positive correlation, etch period is longer, and the degree of depth of blind hole 5 is darker.Therefore the key of the control to over etching amount is to adjust etch period, and to avoid, etch period is oversize causes that too many over etching causes harmful effect to device.
In test structure of the present invention, described etching stop layer is substrate 1 below 2, and as mentioned above, its material is low k dielectric or super low k dielectric, be easy to be etched, thereby the thickness that can be etched according to it is determined over etching amount.
Step S3: the longitudinal section pattern of the test structure after test etching, if the lower surface of described blind hole 5 is lower than the lower surface of described etching stop layer 2, and the distance between the lower surface of described blind hole 5 and described etching stop layer 2 lower surfaces is less than or equal to default over etching amount, adopt described default etching condition to treat etched features and carry out etching, if do not meet, enter step S4;
Concrete, adopt scanning electron microscopy or transmission electron microscope to test the longitudinal section pattern of the test structure after etching.In the present embodiment, by test structure section after etching, then adopt its longitudinal section pattern of scanning electron microscope test, and obtain the over etching amount of described blind hole 5.While it is pointed out that section, coordinate focused ion beam to put sample ensure to cut in blind hole by scanning electron microscopy or transmission electron microscope, the common practise that this technology is this area repeats no more herein.
In order to ensure necessary over etching, the lower surface that must meet blind hole 5 arrives described etching stop layer below 2, but can not exceed default over etching amount.Exceed default over etching amount, in actual element manufacturing, can produce damage to the copper of lower floor, affect the reliability of device.Therefore, if the lower surface of described blind hole 5 higher than or flush in the lower surface of described etching stop layer 2, or the lower surface of described blind hole 5 and described etching stop layer 2 lower surfaces between distance be greater than default over etching amount, just need to adjust default etching condition, to ensure the yield of product on line.The method regulating refers to the explanation about step S4 below.
Step S4: regulate the parameter in described default etching condition, and repeating step S1 ~ S3.
As mentioned above, in the situation that other etching parameters is constant, the blind hole depth etching and etch period positive correlation, etch period is longer, and the degree of depth of blind hole 5 is darker.In the present embodiment, determine suitable etching technics by adjusting etch period.In other embodiments, also can be by regulating the parameters such as etching power or its combination to regulate.
Concrete, the lower surface that obtains described blind hole 5 if detect higher than or flush in the lower surface of described etching stop layer 2, the etching depth that blind hole 5 is described is inadequate, can extend the etch period in described default etching condition, and repeat above-mentioned steps S1 ~ S3, until etching depth is suitable, then adopt default etching condition now to carry out etching to the device to be etched on line.In like manner, if the distance between the lower surface of described blind hole 5 and described etching stop layer 2 lower surfaces is greater than default over etching amount, shorten the etch period in described default etching condition, and repeat above-mentioned steps S1 ~ S3, until etching depth is suitable, then adopt default etching condition now to carry out etching to the device to be etched on line.
Can implement to monitor the over etching amount on line by above step, and adjust at any time best etching condition, realize the effective control to blind hole 5 over etching amounts, ensure the yield of product.
Refer to table 1, be shown as three groups of blind hole over etching amounts that different etching conditions is corresponding in the present embodiment.
| Etching condition | Over etching amount |
| C 4F 8，45s | 500 dusts |
| C 4F 8，35s | 350 dusts |
| C 4F 8，25s | 100 dusts |
Table 1
It is to be noted, in table 1, only list the canonical parameter in etching condition: etching gas and etch period, in table 1, etching condition also comprises other parameter, as etching power etc., because in the present embodiment being determines suitable etching technics by adjusting etch period, in table 1, in three groups of different etching conditions, other parameter is all consistent, therefore do not list in detail.
In sum, in the method for effective control over etching amount of the present invention, the etching stop layer preparation technology of test structure is identical with the preparation technology of etching stop layer corresponding in device to be etched on real-time production line, consistent with practical devices of thickness, do not need to thicken etching stop layer by special sample preparation, and do not need pre-copper plate, the detection method of over etching amount is simple, significantly reduce the cost that technique is adjusted.The present invention can effectively control the over etching amount of through-hole interconnection, reduce the damage to lower floor's copper, ensure to be effectively connected between copper interconnecting line and lower floor's copper, improve the reliability of device, and the product that can use normal process flow goes judgement, etching technics on Real-Time Monitoring production line, the yield of guarantee product.So the present invention has effectively overcome various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all can, under spirit of the present invention and category, modify or change above-described embodiment.Therefore, such as in affiliated technical field, have and conventionally know that the knowledgeable, not departing from all equivalence modifications that complete under disclosed spirit and technological thought or changing, must be contained by claim of the present invention.
Claims (8)
1. a method of effectively controlling over etching amount, is characterized in that, the method for described effective control over etching amount at least comprises the following steps:
S1 a: test structure is provided, and described test structure comprises substrate, etching stop layer, interlayer dielectric layer and hard mask from bottom to top successively; The thickness of described etching stop layer is identical with the thickness of etching stop layer corresponding in device to be etched;
S2: form default etching pattern on described hard mask, then adopt default etching condition to carry out etching to described test structure, form some blind holes for interconnecting in described test structure;
S3: the longitudinal section pattern of the test structure after test etching, if the lower surface of described blind hole is lower than the lower surface of described etching stop layer, and the distance between the lower surface of described blind hole and described etching stop layer lower surface is less than or equal to default over etching amount, adopt described default etching condition to treat etched features and carry out etching, if do not meet, enter step S4;
S4: regulate the parameter in described default etching condition, and repeating step S1 ~ S3.
2. the method for effective control over etching amount according to claim 1, is characterized in that: the etching stop layer in described test structure is identical with the preparation technology of etching stop layer corresponding in described device to be etched.
3. the method for effective control over etching amount according to claim 1, is characterized in that: in described step S3, adopt the longitudinal section pattern of the test structure after scanning electron microscopy or transmission electron microscope test etching.
4. the method for effective control over etching amount according to claim 1, is characterized in that: in described step S4, the parameter in described default etching condition comprises etch period.
5. the method for effective control over etching amount according to claim 1, is characterized in that: described etching is plasma etching.
6. the method for effective control over etching amount according to claim 1, it is characterized in that: the material of described inter-level dielectric is low k dielectric or super low k dielectric, described low k dielectric meets k<3, and described super low k dielectric meets k<2.5.
7. the method for effective control over etching amount according to claim 1, it is characterized in that: the material of described substrate is low k dielectric or super low k dielectric, described low k dielectric meets k<3, and described super low k dielectric meets k<2.5.
8. the method for effective control over etching amount according to claim 1, is characterized in that: the thickness range of described etching stop layer is 200 ~ 400 dusts.
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|---|---|---|---|
| CN201310113918.2A CN104103537B (en) | 2013-04-02 | 2013-04-02 | The method effectively controlling over etching amount |
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| CN201310113918.2A CN104103537B (en) | 2013-04-02 | 2013-04-02 | The method effectively controlling over etching amount |
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| CN104103537B CN104103537B (en) | 2016-12-28 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114488703A (en) * | 2021-12-10 | 2022-05-13 | 武汉新芯集成电路制造有限公司 | Method for determining etching scheme, test mask plate and etching system |
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| CN101740475A (en) * | 2008-11-11 | 2010-06-16 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device with dual-mosaic structure and forming method thereof |
| CN102237298A (en) * | 2010-04-27 | 2011-11-09 | 中芯国际集成电路制造(上海)有限公司 | Method for improving stability of through hole etching |
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2013
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| US20040110369A1 (en) * | 2002-12-05 | 2004-06-10 | Ping Jiang | Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities |
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| CN101740475A (en) * | 2008-11-11 | 2010-06-16 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor device with dual-mosaic structure and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114488703A (en) * | 2021-12-10 | 2022-05-13 | 武汉新芯集成电路制造有限公司 | Method for determining etching scheme, test mask plate and etching system |
| CN114488703B (en) * | 2021-12-10 | 2024-04-12 | 武汉新芯集成电路制造有限公司 | Determination method of etching scheme, test mask plate and etching system |
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| CN104103537B (en) | 2016-12-28 |
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