CN104102035A - Array substrate and driving method thereof, as well as display device - Google Patents
Array substrate and driving method thereof, as well as display device Download PDFInfo
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- CN104102035A CN104102035A CN201410302428.1A CN201410302428A CN104102035A CN 104102035 A CN104102035 A CN 104102035A CN 201410302428 A CN201410302428 A CN 201410302428A CN 104102035 A CN104102035 A CN 104102035A
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000000758 substrate Substances 0.000 title abstract 4
- 239000010409 thin film Substances 0.000 claims description 9
- 229910044991 metal oxide Inorganic materials 0.000 claims description 4
- 150000004706 metal oxides Chemical class 0.000 claims description 4
- 230000005669 field effect Effects 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 15
- 230000010355 oscillation Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 10
- 238000004458 analytical method Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000033228 biological regulation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3614—Control of polarity reversal in general
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0297—Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
- G09G2330/023—Power management, e.g. power saving using energy recovery or conservation
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
- G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
- Liquid Crystal (AREA)
- Multimedia (AREA)
Abstract
The invention discloses an array substrate and a driving method thereof, as well as a display device. The array substrate comprises a common voltage generating unit, a sequential control unit, a data voltage generating unit, a switch control unit and pixel units, wherein the switch control unit is connected with the common voltage generating unit, the sequential control unit, the data voltage generating unit, a common voltage wire and a data wire; at a current frame, the switch control unit is used for loading a common voltage signal onto the common voltage wire and loading a data voltage signal onto the data wire; at a next frame, the switch control unit is used for loading a common voltage signal onto the data wire and loading a data voltage signal onto the common voltage wire. The switch control unit is arranged for switching voltage signals loaded in the data wire and the common voltage wire, so that the polarity-reversal requirement of liquid crystal molecules in the display device is met; meanwhile, the array substrate can be used for reducing the output voltage swing of the data voltage signals, so that the power consumption of the display device is reduced.
Description
Technical field
The present invention relates to display technique field, particularly a kind of array base palte and driving method thereof, display device.
Background technology
Liquid crystal display is current conventional flat-panel monitor, and wherein (Thin Film Transistor Liquid Crystal Display is called for short: TFT-LCD) be the main product in liquid crystal display Thin Film Transistor-LCD.
Thin Film Transistor-LCD comprises: viewing area and non-display area, be provided with several pixel cells in viewing area, in each pixel cell, include pixel electrode, memory capacitance and thin film transistor (TFT), the first end of memory capacitance is connected with the source electrode of data line and thin film transistor (TFT), and the second end of memory capacitance is connected with grid line or public pressure wire.
Situation about being connected with public pressure wire taking the second end of memory capacitance is as example.In the time that grid line corresponding to pixel cell scans, data voltage signal is loaded on the first end of memory capacitance by data line, public voltage signal is loaded on the second end of memory capacitance by public pressure wire, now memory capacitance two ends form voltage difference, be that memory capacitance charging is complete, memory capacitance for maintaining the voltage on pixel cell pixel electrode after the grid line end of scan of corresponding row.
At present, public voltage signal is generally direct current signal or is AC signal.In the time that public voltage signal is AC signal, the output voltage of data voltage signal only needs to be arranged between 0～5V, can meet the reversal of poles demand of the liquid crystal molecule in liquid crystal display; And in the time that public voltage signal is direct current signal, the output voltage of data voltage signal needs between be arranged on-5V～5V, can realize the reversal of poles demand of the liquid crystal molecule in liquid crystal display.
From foregoing, in the time that public voltage signal is direct current signal, the amplitude of oscillation of the output voltage of corresponding data voltage signal is large (regulation of line voltage is larger).And the increase of the amplitude of oscillation of the output voltage of data voltage signal can cause memory capacitance to rise in the power consumption of charge and discharge process, thereby cause the power consumption of whole display panels to rise.
Summary of the invention
The invention provides a kind of array base palte and driving method thereof, display device, in realizing reversal of poles, also can realize the decline of the amplitude of oscillation of the output voltage of data voltage signal, thereby reduced the power consumption of display device.
For achieving the above object, the invention provides a kind of array base palte, comprise: common electric voltage generation unit, data voltage generation unit, timing control unit, some grid lines, data line and public pressure wire, described grid line and data line limit several pixel cells, described pixel cell comprises: the first display switch pipe and memory capacitance, the control utmost point of described the first display switch pipe is connected with the described grid line of corresponding row, first utmost point of described the first display switch pipe is connected with the described data line of respective column, second utmost point of described display switch pipe is connected with the first end of described memory capacitance, the second end of described memory capacitance is connected with the described public pressure wire of respective column,
Described array base palte also comprises: several switch control units, and described switch control unit is connected with described data line, described public pressure wire, described common electric voltage generation unit, described data voltage generation unit and described timing control unit;
Described common electric voltage generation unit is used for generating public voltage signal;
Described data voltage generation unit is for generated data voltage signal;
Described timing control unit is used for generating timing control signal;
Described switch control unit, under the control of described timing control signal, is loaded on described public voltage signal in described public pressure wire, and described data voltage signal is loaded on described data line; Or, described public voltage signal is loaded on described data line, and described data voltage signal is loaded in described public pressure wire.
Alternatively, described switch control unit comprises: the first gauge tap pipe, the second gauge tap pipe, the 3rd gauge tap pipe and the 4th gauge tap pipe;
The control of described the first gauge tap pipe, described the second gauge tap pipe, described the 3rd gauge tap pipe and described the 4th gauge tap pipe is extremely all connected with described timing control unit;
First utmost point of described the first gauge tap pipe is connected with described data voltage generation unit, and second utmost point of described the first gauge tap pipe is connected with described data line;
First utmost point of described the second gauge tap pipe is connected with described data voltage generation unit, and second utmost point of described the second gauge tap pipe is connected with described public pressure wire;
First utmost point of described the 3rd gauge tap pipe is connected with described common electric voltage generation unit, and second utmost point of described the 3rd gauge tap pipe is connected with public pressure wire;
First utmost point of described the 4th gauge tap pipe is connected with described common electric voltage generation unit, and second utmost point of described gauge tap pipe is connected with described data line.
Alternatively, described the first gauge tap pipe, the second gauge tap pipe, the 3rd gauge tap pipe and the 4th gauge tap pipe are metal oxide semiconductor field effect tube.
Alternatively, described timing control unit comprises a sequential control line, and the control utmost point of described the first gauge tap pipe, described the second gauge tap pipe, described the 3rd gauge tap pipe and described the 4th gauge tap pipe is connected with described sequential control line;
Described the first gauge tap pipe and described the 3rd gauge tap pipe are N-type transistor, and described the second gauge tap pipe and described the 4th gauge tap pipe are P transistor npn npn;
Or described the first gauge tap pipe and described the 3rd gauge tap pipe are P transistor npn npn, described the second gauge tap pipe and described the 4th gauge tap pipe are N-type transistor.
Alternatively, described timing control unit comprises two sequential control lines, described the first gauge tap pipe is connected one bar of described sequential control line with the control utmost point of described the 3rd gauge tap pipe, described the second gauge tap pipe is connected another bar of sequential control line with the control utmost point of described the 4th gauge tap pipe, and the timing control signal loading in two described sequential control lines is contrary;
Described the first gauge tap pipe, described the second gauge tap pipe, described the 3rd gauge tap pipe and described the 4th gauge tap pipe are N-type transistor;
Or described the first gauge tap pipe, described the second gauge tap pipe, described the 3rd gauge tap pipe and described the 4th gauge tap pipe are P transistor npn npn.
Alternatively, also comprise: the second display switch pipe, the control utmost point of described the second display switch pipe is connected with described grid line, and first utmost point of described the second display switch pipe is connected with described public pressure wire, and second utmost point of described the second display switch pipe is connected with the second end of described memory capacitance.
Alternatively, described the second display switch pipe is thin film transistor (TFT).
For achieving the above object, the present invention also provides a kind of display device, comprising: array base palte, this array base palte adopts above-mentioned array base palte.
For achieving the above object, the present invention also provides a kind of driving method of array base palte, described array base palte comprises: common electric voltage generation unit, data voltage generation unit, timing control unit, some grid lines, data line and public pressure wire, described grid line and data line limit several pixel cells, described pixel cell comprises: the first display switch pipe and memory capacitance, the control utmost point of described the first display switch pipe is connected with the described grid line of corresponding row, first utmost point of described the first display switch pipe is connected with the described data line of respective column, second utmost point of described display switch pipe is connected with the first end of described memory capacitance, the second end of described memory capacitance is connected with the described public pressure wire of respective column,
Described array base palte also comprises: several switch control units, and described switch control unit is connected with described data line, described public pressure wire, described common electric voltage generation unit, described data voltage generation unit and described timing control unit;
Described common electric voltage generation unit is used for generating public voltage signal;
Described data voltage generation unit is for generated data voltage signal;
Described timing control unit is used for generating timing control signal;
Described driving method comprises:
In a frame, described switch control unit, under the control of described timing control signal, is loaded on described public voltage signal in described public pressure wire, and described data voltage signal is loaded on described data line;
In next frame, described switch control unit is under the control of described timing control signal, and just described public voltage signal is loaded on described data line, and described data voltage signal is loaded in described public pressure wire;
Or in a frame, described switch control unit, under the control of described timing control signal, is loaded on described public voltage signal on described data line, and described data voltage signal is loaded in described public pressure wire;
In next frame, described switch control unit, under the control of described timing control signal, is loaded on described public voltage signal in described public pressure wire, and described data voltage signal is loaded on described data line.
The present invention has following beneficial effect:
The invention provides a kind of array base palte and driving method thereof, display device, wherein this array base palte comprises: common electric voltage generation unit, timing control unit, several data voltage generation units, switch control unit and pixel cell, switch control unit and common electric voltage generation unit, timing control unit, data voltage generation unit, public pressure wire is connected with data line, switch control unit switches for the voltage signal that data line and public pressure wire are loaded, thereby realize the reversal of poles demand of liquid crystal molecule in display device, simultaneously, array base palte provided by the invention can also effectively reduce the amplitude of oscillation of the output voltage of data voltage signal, thereby reach the object that reduces display device power consumption.
Brief description of the drawings
The schematic diagram of the array base palte that Fig. 1 provides for the embodiment of the present invention one;
Fig. 2 is the sequential chart of the array base palte shown in Fig. 1;
Fig. 3 is the schematic diagram of switch control unit in Fig. 1;
Fig. 4 is the another sequential chart of the array base palte shown in Fig. 1;
The schematic diagram of the array base palte that Fig. 5 provides for the embodiment of the present invention two;
Fig. 6 is the sequential chart of the array base palte shown in Fig. 5;
Fig. 7 is the schematic diagram of switch control unit in Fig. 5;
The process flow diagram of the driving method of the array base palte that Fig. 8 provides for the embodiment of the present invention.
Embodiment
For making those skilled in the art understand better technical scheme of the present invention, below in conjunction with accompanying drawing, array base palte provided by the invention and driving method thereof, display device are described in detail.
Embodiment mono-
The schematic diagram of the array base palte that Fig. 1 provides for the embodiment of the present invention one, Fig. 2 is the sequential chart of the array base palte shown in Fig. 1, Fig. 3 is the schematic diagram of switch control unit in Fig. 1, as shown in Figure 1 to Figure 3, this array base palte comprises: common electric voltage generation unit, data voltage generation unit, timing control unit, some grid lines, data line and public pressure wire, grid line and data line limit several pixel cells, pixel cell comprises: the first display switch pipe and memory capacitance, the control utmost point of the first display switch pipe is connected with the grid line of corresponding row, first utmost point of the first display switch pipe is connected with the data line of respective column, second utmost point of display switch pipe is connected with the first end of memory capacitance, the second end of memory capacitance is connected with the public pressure wire of respective column, this array base palte also comprises: several switch control units, and switch control unit is connected with data line, public pressure wire, common electric voltage generation unit, data voltage generation unit and timing control unit, wherein, common electric voltage generation unit is used for generating public voltage signal, data voltage generation unit is for generated data voltage signal, timing control unit is used for generating timing control signal, switch control unit, under the control of timing control signal, is loaded on public voltage signal in public pressure wire, and data voltage signal is loaded on data line, or, public voltage signal is loaded on data line, and data voltage signal is loaded in public pressure wire.
It should be noted that, in the present embodiment, the quantity of grid line is that n is capable, the quantity of data line is m row, the quantity of public pressure wire is m row, the quantity of pixel cell is n × m, has only schematically specifically drawn two row grid lines (Gate_1 and Gate_2), two column data lines (Data_1 and Data_2), two row public pressure wire (Vcom_1 and Vcom_2) and four pixel cells (Pixel_1, Pixel_2, Pixel_3 and Pixel_4) in Fig. 1.In the present embodiment, the corresponding switch control unit of whole pixel cells in same row has only schematically specifically drawn two switch control units (A and B) in Fig. 1.
The present invention is by arranging switch control unit, thereby the voltage signal loading in data line and public pressure wire in two continuous frames is switched, and then realize the reversal of poles demand of liquid crystal molecule in display device, simultaneously, the present invention can also effectively reduce the amplitude of oscillation of the voltage of data voltage signal, thereby reaches the object that reduces display device power consumption.
In the present embodiment, taking switch control unit A as example, switch control unit specifically comprises: the first gauge tap pipe M1, the second gauge tap pipe M2, the 3rd gauge tap pipe M3 and the 4th gauge tap pipe M4, wherein, the first gauge tap pipe M1, the second gauge tap pipe M2, the 3rd gauge tap pipe M3 are extremely all connected with timing control unit with the control of the 4th gauge tap pipe M4; First utmost point of the first gauge tap pipe M1 is connected with data voltage generation unit, and second utmost point of the first gauge tap pipe M1 is connected with data line Data_1; First utmost point of the second gauge tap pipe M2 is connected with data voltage generation unit, and second utmost point of the second gauge tap pipe M2 is connected with public pressure wire Vcom_1; First utmost point of the 3rd gauge tap pipe is connected with common electric voltage generation unit, and second utmost point of the 3rd gauge tap pipe is connected with public pressure wire Vcom_1; First utmost point of the 4th gauge tap pipe is connected with common electric voltage generation unit, and second utmost point of gauge tap pipe is connected with data line Data_1.In the present embodiment, the first gauge tap pipe M1, the second gauge tap pipe M2, the 3rd gauge tap pipe M3 and the 4th gauge tap pipe M4 can be thin film transistor (TFT) (Thin Film Transistor, be called for short TFT pipe), also it can be metal oxide semiconductor field effect tube (Metal Oxide Scmiconductor is called for short MOS).But because MOS electron mobility is higher, discharge and recharge speed fast, in the time using as switch, the ON/OFF control rate of MOS is fast, therefore in the present embodiment preferably, the first gauge tap pipe M1, the second gauge tap pipe M2, the 3rd gauge tap pipe M3 and the 4th gauge tap pipe M4 are MOS, from realizing, the voltage signal loading data line Data_1 and public pressure wire Vcom_1 have been carried out precisely switching fast.The concrete structure of the concrete structure of switch control unit B and switch control unit A is similar, repeats no more herein.
It should be noted that, the switch control unit A (B) in the present embodiment is arranged on the cabling region of array base palte.
In addition, in each pixel cell of array base palte, be also provided with the second display switch pipe, taking pixel cell Pixel_1 as example, the control utmost point of the second display switch pipe T2 is connected with grid line Gate_1, first utmost point of the second display switch pipe T2 is connected with public pressure wire, and second second utmost point of display switch pipe T2 and the second end of memory capacitance C1 are connected.In the present embodiment, the second display switch pipe can be also TFT or MOS.Preferably, the second display switch pipe is TFT.Because the first display switch pipe T1 and the second display switch pipe T2 are all positioned at pixel cell, and both are TFT, therefore the second display switch pipe T2 can adopt the production technology identical with the first display switch pipe T1 and synchronously form with the first display switch pipe T1, thereby effectively shorten the production cycle of this array base palte, improve the formation efficiency that produces line.
Adopt the sequential shown in Fig. 2, can realize the display device that includes the array base palte shown in Fig. 1 and carry out a reversion, be described in detail with the situation that realizes display device point and reverse below in conjunction with accompanying drawing.In the present embodiment, timing control unit comprises a sequential control line Clock, and the control utmost point of the first gauge tap pipe M1 (M5), the second gauge tap pipe M2 (M6), the 3rd gauge tap pipe M3 (M7) and the 4th gauge tap pipe M4 (M8) is connected with sequential control line Clock.The quantity of switch control unit is two, and the first gauge tap pipe M1 in switch control unit A and the 3rd gauge tap pipe M3 are N-type MOS, the second gauge tap pipe M2 and the 4th gauge tap pipe M4 are P type MOS, the first gauge tap pipe M5 in switch control unit B and the 3rd gauge tap pipe M7 are P type MOS, and the second gauge tap pipe M6 and the 4th gauge tap pipe M8 are N-type MOS.The first display switch pipe T1 (T3, T5, T7) and the second display switch pipe T2 (T4, T6, T8) are N-type TFT.
In the first frame;
The first row grid line Gate_1 starts to scan, the first display switch pipe T1 in pixel cell Pixel_1 and the second display switch pipe T2 are in conducting state, and the first display switch pipe 3 in pixel cell Pixel_2 and the second display switch pipe T4 are in conducting state.The first display switch pipe T5 in pixel cell Pixel_3 and the second display switch pipe T6 are in cut-off state, and the first display switch pipe T7 in pixel cell Pixel_4 and the second display switch pipe T8 are in cut-off state.
Meanwhile, the timing control signal in sequential control line Clock is in high level, and the first gauge tap pipe M1 in switch control unit A and the 3rd gauge tap pipe M3 are in conducting state, and the second gauge tap pipe M2 and the 4th gauge tap pipe M4 are in cut-off state.The first gauge tap pipe M5 in switch control unit B and the 3rd gauge tap pipe M7 are in cut-off state, and the second gauge tap pipe M6 and the 4th gauge tap pipe M8 are in conducting state.Correspondingly, in data line Data_1, load data voltage signal, in public pressure wire Vcom_1, loaded public voltage signal, in data line Data_2, loaded public voltage signal, in public pressure wire Vcom_2, loaded data voltage signal.
Correspondingly, the first end of the memory capacitance C1 in pixel cell Pixel_1 has loaded data voltage signal, and the second end of memory capacitance C1 has loaded public voltage signal, and the voltage difference at memory capacitance C1 two ends is Vdata-Vvcom; The first end of memory capacitance C2 in pixel cell Pixel_2 has loaded public voltage signal, the second end of memory capacitance C1 has loaded data voltage signal, the voltage difference at memory capacitance C1 two ends is Vvcom-Vdata, the output voltage that wherein Vdata is data voltage signal, the output voltage that Vvcom is public voltage signal.
It should be noted that, the output voltage of data voltage signal is corresponding with the demonstration GTG of pixel cell, the output voltage span of the data voltage signal in the present embodiment is between 0V～5V, for ease of describing, in the present embodiment, supposition output voltage of data voltage signal in the first frame and the second frame is all 3V, and the output voltage of public voltage signal is OV (not considering feed voltage in the present embodiment).
Therefore, after grid line Gate_1 has scanned, the voltage difference at the memory capacitance C1 two ends in pixel cell Pixel_1 is Vdata-Vvcom=3V-0V=3V, and the voltage difference at the memory capacitance C2 two ends in pixel cell Pixel_2 is Vvcom-Vdata=0V-3V=-3V.
The first row grid line Gate_1 end of scan, the second row grid line Gate_2 starts scanning.Now the first display switch pipe T1 in pixel cell Pixel_1 and the second display switch pipe T2 are in cut-off state, the first display switch pipe 3 in pixel cell Pixel_2 and the second display switch pipe T4 are in cut-off state, the first display switch pipe T5 in pixel cell Pixel_3 and the second display switch pipe T6 are in conducting state, and the first display switch pipe T7 in pixel cell Pixel_4 and the second display switch pipe T8 are in conducting state.
Meanwhile, the timing control signal in sequential control line Clock is in low level, and the first gauge tap pipe M1 in switch control unit A and the 3rd gauge tap pipe M3 are in cut-off state, and the second gauge tap pipe M2 and the 4th gauge tap pipe M4 are in conducting state.The first gauge tap pipe M5 in switch control unit B and the 3rd gauge tap pipe M7 are in conducting state, and the second gauge tap pipe M6 and the 4th gauge tap pipe M8 are in cut-off state.Correspondingly, in data line Data_1, load public voltage signal, in public pressure wire Vcom_1, loaded data voltage signal, in data line Data_2, loaded data voltage signal, in public pressure wire Vcom_2, loaded public voltage signal.
Because the second display switch pipe T2 in pixel cell Pixel_1 now and the second display switch pipe T4 in pixel cell Pixel_2 are all in cut-off state, therefore, data voltage signal in the first public pressure wire Vcom_1 cannot be transferred to the second end of memory capacitance in pixel cell Pixel_1, public voltage signal in the second public pressure wire Vcom_2 cannot be transferred to the second end of memory capacitance in pixel cell Pixel_2, thereby has effectively avoided data line and public pressure wire to carry out the impact of voltage signal switching on memory capacitance in pixel cell.
Correspondingly, the first end of the memory capacitance C3 in pixel cell Pixel_3 has loaded public voltage signal, and the second end of memory capacitance C3 has loaded data voltage signal, and the voltage difference at memory capacitance C3 two ends is Vvcom-Vdata=0V-3V=-3V; The first end of memory capacitance C4 in pixel cell Pixel_4 has loaded data voltage signal, and the second end of memory capacitance C4 has loaded public voltage signal, and the voltage difference at memory capacitance C4 two ends is Vdata-Vvcom=3V-0V=3V.
The second row grid line Gate_2 end of scan, the third line grid line Gate_3 (not shown in figure 1) starts scanning.The like, until last column grid line Gate_n (not shown in figure 1) completes scanning, the first frame picture finishes.
In the first frame, the voltage difference at memory capacitance C1 two ends be on the occasion of, the voltage difference at memory capacitance C2 two ends is negative value, the voltage difference at memory capacitance C3 two ends is negative value, the voltage difference at memory capacitance C4 two ends be on the occasion of.
In the second frame;
The first row grid line Gate_1 starts to scan, the first display switch pipe T1 in pixel cell Pixel_1 and the second display switch pipe T2 are in conducting state, and the first display switch pipe 3 in pixel cell Pixel_2 and the second display switch pipe T4 are in conducting state.The first display switch pipe T5 in pixel cell Pixel_3 and the second display switch pipe T6 are in cut-off state, and the first display switch pipe T7 in pixel cell Pixel_4 and the second display switch pipe T8 are in cut-off state.
Simultaneously, timing control signal in sequential control line Clock is in low level, according to above-mentioned known to the analysis in the first frame, now in data line Data_1, load public voltage signal, in public pressure wire Vcom_1, load data voltage signal, in data line Data_2, load data voltage signal, in public pressure wire Vcom_2, loaded public voltage signal.
Correspondingly, the first end of the memory capacitance C1 in pixel cell Pixel_1 has loaded public voltage signal, and the second end of memory capacitance C1 has loaded data voltage signal, and the voltage difference at memory capacitance C1 two ends is Vvcom-Vdata=0V-3V=-3V; The first end of memory capacitance C2 in pixel cell Pixel_2 has loaded data voltage signal, and the second end of memory capacitance C1 has loaded public voltage signal, and the voltage difference at memory capacitance C1 two ends is Vdata-Vvcom=3V-0V=3V.
The first row grid line Gate_1 end of scan, the second row grid line Gate_2 starts scanning.Now the first display switch pipe T1 in pixel cell Pixel_1 and the second display switch pipe T2 are in cut-off state, the first display switch pipe 3 in pixel cell Pixel_2 and the second display switch pipe T4 are in cut-off state, the first display switch pipe T5 in pixel cell Pixel_3 and the second display switch pipe T6 are in conducting state, and the first display switch pipe T7 in pixel cell Pixel_4 and the second display switch pipe T8 are in conducting state.
Simultaneously, timing control signal in sequential control line Clock is in low level, according to above-mentioned known to the analysis in the first frame, now in data line Data_1, load data voltage signal, in public pressure wire Vcom_1, load public voltage signal, in data line Data_2, load public voltage signal, in public pressure wire Vcom_2, loaded data voltage signal.
Because the second display switch pipe T2 in pixel cell Pixel_1 now and the second display switch pipe T4 in pixel cell Pixel_2 are all in cut-off state, therefore, public voltage signal in the first public pressure wire Vcom_1 cannot be transferred to the second end of memory capacitance in pixel cell Pixel_1, data voltage signal in the second public pressure wire Vcom_2 cannot be transferred to the second end of memory capacitance in pixel cell Pixel_2, thereby has effectively avoided data line and public pressure wire to carry out the impact of voltage signal switching on memory capacitance in pixel cell.
Correspondingly, the first end of the memory capacitance C3 in pixel cell Pixel_3 has loaded data voltage signal, and the second end of memory capacitance C3 has loaded public voltage signal, and the voltage difference at memory capacitance C3 two ends is Vdata-Vvcom=3V-0V=3V; The first end of memory capacitance C4 in pixel cell Pixel_4 has loaded public voltage signal, and the second end of memory capacitance C4 has loaded data voltage signal, and the voltage difference at memory capacitance C4 two ends is Vvcom-Vdata=0V-3V=-3V.
The second row grid line Gate_2 end of scan, the third line grid line Gate_3 (not shown in figure 1) starts scanning.The like, until last column grid line Gate_n completes scanning, the second frame picture finishes.
In the second frame, the voltage difference at memory capacitance C1 two ends is negative value, the voltage difference at memory capacitance C2 two ends be on the occasion of, the voltage difference at memory capacitance C3 two ends be on the occasion of, the voltage difference at memory capacitance C4 two ends is negative value.
Known by said process, the display device that includes the array base palte shown in Fig. 1 has realized some reversion.In addition, in the process of realization point reversion, in the situation that public voltage signal is direct current signal, the output voltage of data voltage signal is maintained between 0～5V, thereby reduced the amplitude of oscillation of the output voltage of data voltage signal, and then reduced the power consumption of display device.Meanwhile, due to an only corresponding sequential control line of the whole switch control units on array base palte, therefore can effectively reduce the setting of array base palte upward wiring, thus the effectively area of viewing area of energy.
It should be noted that, the display device that includes the array base palte shown in Fig. 1 not only can realize a reversion, can also realize row reversion.Fig. 4 is the another sequential chart of the array base palte shown in Fig. 1, as shown in Figure 4, adopt the sequential shown in Fig. 4 can realize row reversion and the row reversion of the display device that includes the array base palte shown in Fig. 1, difference shown in sequential shown in Fig. 4 and Fig. 2 is, in Fig. 4, timing control signal keeps high level in the first frame always, in the second frame, keep low level always, just once change every the level of the time of frame sequence control signal.
In the time that the array base palte shown in Fig. 1 adopts the sequential shown in Fig. 4, in the first frame, the voltage difference at memory capacitance C1 two ends be on the occasion of, the voltage difference at memory capacitance C2 two ends is negative value, the voltage difference at memory capacitance C3 two ends be on the occasion of, the voltage difference at memory capacitance C4 two ends is negative value; In the second frame, the voltage difference at memory capacitance C1 two ends is negative value, the voltage difference at memory capacitance C2 two ends be on the occasion of, the voltage difference at memory capacitance C3 two ends is negative value, the voltage difference at memory capacitance C4 two ends be on the occasion of, realized row reversions, detailed process is not described in detail herein.
In addition, array base palte provided by the invention can also be realized row reversion, suppose in Fig. 1, if the first gauge tap pipe M1 in switch control unit A and the 3rd gauge tap pipe M3 are N-type MOS, the second gauge tap pipe M2 and the 4th gauge tap pipe M4 are P type MOS, and the first gauge tap pipe M5 in switch control unit B and the 3rd gauge tap pipe M7 are N-type MOS, the second gauge tap pipe M6 and the 4th gauge tap pipe M8 are P type MOS, and switch control unit A is identical with switch control unit B.When adopt shown in Fig. 2 sequential time, in the first frame, the voltage difference at memory capacitance C1 two ends be on the occasion of, the voltage difference at memory capacitance C2 two ends be on the occasion of, the voltage difference at memory capacitance C3 two ends is negative value, the voltage difference at memory capacitance C4 two ends is negative value; In the second frame, the voltage difference at memory capacitance C1 two ends is negative value, and the voltage difference at memory capacitance C2 two ends is negative value, the voltage difference at memory capacitance C3 two ends be on the occasion of, the voltage difference at memory capacitance C4 two ends be on the occasion of, realized capable reversion, detailed process is not described in detail herein.
The embodiment of the present invention one provides a kind of array base palte, this array base palte comprises: common electric voltage generation unit, timing control unit, several data voltage generation units, switch control unit and pixel cell, wherein switch control unit and common electric voltage generation unit, timing control unit, data voltage generation unit, public pressure wire is connected with data line, switch control unit switches for the voltage signal that data line and public pressure wire are loaded, thereby realize the reversal of poles demand of liquid crystal molecule in display device, simultaneously, array base palte provided by the invention can also effectively reduce the amplitude of oscillation of the output voltage of data voltage signal, thereby reach the object that reduces display device power consumption.
Embodiment bis-
The schematic diagram of the array base palte that Fig. 5 provides for the embodiment of the present invention two, Fig. 6 is the sequential chart of the array base palte shown in Fig. 5, Fig. 7 is the schematic diagram of switch control unit in Fig. 5, as shown in Figures 5 to 7, the difference of the array base palte shown in the array base palte shown in Fig. 5 and Fig. 1 is, timing control unit in array base palte shown in Fig. 7 comprises two sequential control line Clock_1 (Clock_2), the first gauge tap pipe M1 in switch control unit A is connected sequential control line Clock_1 with the 3rd gauge tap pipe M3, the second gauge tap pipe M2 in switch control unit A is connected sequential control line Clock_2 with the 4th gauge tap pipe M4, the first gauge tap pipe M5 in switch control unit B is connected sequential control line Clock_1 with the 3rd gauge tap pipe M7, the second gauge tap pipe M6 in switch control unit B is connected sequential control line Clock_2 with the 4th gauge tap pipe M8, and the timing control signal loading in sequential control line Clock_1 and sequential control line Clock_2 is contrary.
In the present embodiment, suppose that the first gauge tap pipe M1, the second gauge tap pipe M2, the 3rd gauge tap pipe M3 and the 4th gauge tap pipe M4 in switch control unit A are N-type MOS, the first gauge tap pipe M5, the second gauge tap pipe M6, the 3rd gauge tap pipe M7 and the 4th gauge tap pipe M8 in switch control unit B are P type MOS.
In the first frame;
The first row grid line Gate_1 starts to scan, the first display switch pipe T1 in pixel cell Pixel_1 and the second display switch pipe T2 are in conducting state, and the first display switch pipe 3 in pixel cell Pixel_2 and the second display switch pipe T4 are in conducting state.The first display switch pipe T5 in pixel cell Pixel_3 and the second display switch pipe T6 are in cut-off state, and the first display switch pipe T7 in pixel cell Pixel_4 and the second display switch pipe T8 are in cut-off state.
Meanwhile, the timing control signal in sequential control line Clock_1 is in high level, and the timing control signal in sequential control line Clock_2 is in low level.Therefore, the first gauge tap pipe M1 in switch control unit A and the 3rd gauge tap pipe M3 are in conducting state, and the second gauge tap pipe M2 and the 4th gauge tap pipe M4 are in cut-off state.The first gauge tap pipe M5 in switch control unit B and the 3rd gauge tap pipe M7 are in cut-off state, and the second gauge tap pipe M6 and the 4th gauge tap pipe M8 are in conducting state.Correspondingly, in data line Data_1, load data voltage signal, in public pressure wire Vcom_1, loaded public voltage signal, in data line Data_2, loaded public voltage signal, in public pressure wire Vcom_2, loaded data voltage signal.
Therefore, after grid line Gate_1 has scanned, the voltage difference at the memory capacitance C1 two ends in pixel cell Pixel_1 is Vdata-Vvcom=3V-0V=3V, and the voltage difference at the memory capacitance C2 two ends in pixel cell Pixel_2 is Vvcom-Vdata=0V-3V=-3V.
The first row grid line Gate_1 end of scan, the second row grid line Gate_2 starts scanning.Now the first display switch pipe T1 in pixel cell Pixel_1 and the second display switch pipe T2 are in cut-off state, the first display switch pipe 3 in pixel cell Pixel_2 and the second display switch pipe T4 are in cut-off state, the first display switch pipe T5 in pixel cell Pixel_3 and the second display switch pipe T6 are in conducting state, and the first display switch pipe T7 in pixel cell Pixel_4 and the second display switch pipe T8 are in conducting state.
Meanwhile, the timing control signal in sequential control line Clock_1 is in low level, and the timing control signal in sequential control line Clock_2 is in high level.Therefore, the first gauge tap pipe M1 in switch control unit A and the 3rd gauge tap pipe M3 are in cut-off state, and the second gauge tap pipe M2 and the 4th gauge tap pipe M4 are in conducting state.The first gauge tap pipe M5 in switch control unit B and the 3rd gauge tap pipe M7 are in conducting state, and the second gauge tap pipe M6 and the 4th gauge tap pipe M8 are in cut-off state.Correspondingly, in data line Data_1, load public voltage signal, in public pressure wire Vcom_1, loaded data voltage signal, in data line Data_2, loaded data voltage signal, in public pressure wire Vcom_2, loaded public voltage signal.
Therefore, after grid line Gate_2 has scanned, the voltage difference at the memory capacitance C1 two ends in pixel cell Pixel_1 is Vvcom-Vdata=0V-3V=-3V, and the voltage difference at the memory capacitance C2 two ends in pixel cell Pixel_2 is Vdata-Vvcom=3V-0V=3V.
The second row grid line Gate_2 end of scan, the third line grid line Gate_3 (not shown in Fig. 5) starts scanning.The like, until last column grid line Gate_n (not shown in Fig. 5) completes scanning, the first frame picture finishes.
In the first frame, the voltage difference at memory capacitance C1 two ends be on the occasion of, the voltage difference at memory capacitance C2 two ends is negative value, the voltage difference at memory capacitance C3 two ends is negative value, the voltage difference at memory capacitance C4 two ends be on the occasion of.
In the second frame;
The first row grid line Gate_1 starts to scan, the first display switch pipe T1 in pixel cell Pixel_1 and the second display switch pipe T2 are in conducting state, and the first display switch pipe 3 in pixel cell Pixel_2 and the second display switch pipe T4 are in conducting state.The first display switch pipe T5 in pixel cell Pixel_3 and the second display switch pipe T6 are in cut-off state, and the first display switch pipe T7 in pixel cell Pixel_4 and the second display switch pipe T8 are in cut-off state.
Simultaneously, timing control signal in sequential control line Clock_1 is in low level, timing control signal in sequential control line Clock_2 is in high level, according to above-mentioned known to the analysis in the first frame, now in data line Data_1, load public voltage signal, in public pressure wire Vcom_1, load data voltage signal, in data line Data_2, loaded data voltage signal, in public pressure wire Vcom_2, loaded public voltage signal.
Therefore, after grid line Gate_2 has scanned, the voltage difference at the memory capacitance C1 two ends in pixel cell Pixel_1 is Vvcom-Vdata=0V-3V=-3V, and the voltage difference at the memory capacitance C2 two ends in pixel cell Pixel_2 is Vdata-Vvcom=3V-0V=3V.
The first row grid line Gate_1 end of scan, the second row grid line Gate_2 starts scanning.Now the first display switch pipe T1 in pixel cell Pixel_1 and the second display switch pipe T2 are in cut-off state, the first display switch pipe 3 in pixel cell Pixel_2 and the second display switch pipe T4 are in cut-off state, the first display switch pipe T5 in pixel cell Pixel_3 and the second display switch pipe T6 are in conducting state, and the first display switch pipe T7 in pixel cell Pixel_4 and the second display switch pipe T8 are in conducting state.
Simultaneously, timing control signal in sequential control line Clock_1 is in high level, timing control signal in sequential control line Clock_1 is in low level, according to above-mentioned known to the analysis in the first frame, now in data line Data_1, load data voltage signal, in public pressure wire Vcom_1, load public voltage signal, in data line Data_2, loaded public voltage signal, in public pressure wire Vcom_2, loaded data voltage signal.
Correspondingly, the first end of the memory capacitance C3 in pixel cell Pixel_3 has loaded data voltage signal, and the second end of memory capacitance C3 has loaded public voltage signal, and the voltage difference at memory capacitance C3 two ends is Vdata-Vvcom=3V-0V=3V; The first end of memory capacitance C4 in pixel cell Pixel_4 has loaded public voltage signal, and the second end of memory capacitance C4 has loaded data voltage signal, and the voltage difference at memory capacitance C4 two ends is Vvcom-Vdata=0V-3V=-3V.
The second row grid line Gate_2 end of scan, the third line grid line Gate_3 (not shown) starts scanning.The like, until last column grid line Gate_n completes scanning, the second frame picture finishes.
In the second frame, the voltage difference at memory capacitance C1 two ends is negative value, the voltage difference at memory capacitance C2 two ends be on the occasion of, the voltage difference at memory capacitance C3 two ends be on the occasion of, the voltage difference at memory capacitance C4 two ends is negative value.
Known by said process, the display device that includes the array base palte shown in Fig. 5 has realized some reversion.In addition, in the process of realization point reversion, in the situation that public voltage signal is direct current signal, the output voltage of data voltage signal is maintained between 0～5V, thereby reduced the amplitude of oscillation of the output voltage of data voltage signal, and then reduced the power consumption of display device.
It will be appreciated by persons skilled in the art that in actual applications, the timing control unit in the present invention can also comprise many sequential control lines, and multiple sequential control lines complete the control to controlling switching tube in switch control unit jointly.In addition, the type of each gauge tap pipe in switch control unit (N-type/P type) and timing control signal also can convert accordingly, and the present invention no longer describes one by one for example.
The embodiment of the present invention two provides a kind of array base palte, this array base palte comprises: common electric voltage generation unit, timing control unit, several data voltage generation units, switch control unit and pixel cell, wherein switch control unit and common electric voltage generation unit, timing control unit, data voltage generation unit, public pressure wire is connected with data line, switch control unit switches for the voltage signal that data line and public pressure wire are loaded, thereby realize the reversal of poles demand of liquid crystal molecule in display device, simultaneously, array base palte provided by the invention can also effectively reduce the amplitude of oscillation of the voltage of data voltage signal, thereby reach the object that reduces display device power consumption.
Embodiment tri-
The embodiment of the present invention three provides a kind of display device, this display device comprises array base palte, wherein the array base palte providing in above-described embodiment one or embodiment bis-can be provided this array base palte, and particular content can, with reference to the description in above-described embodiment one or embodiment bis-, repeat no more herein.
The embodiment of the present invention three provides a kind of display device, this display device comprises: array base palte, this array base palte comprises: common electric voltage generation unit, timing control unit, several data voltage generation units, switch control unit and pixel cell, wherein switch control unit and common electric voltage generation unit, timing control unit, data voltage generation unit, public pressure wire is connected with data line, switch control unit switches for the voltage signal that data line and public pressure wire are loaded, thereby realize the reversal of poles demand of liquid crystal molecule in display device, simultaneously, array base palte provided by the invention can also effectively reduce the amplitude of oscillation of the voltage of data voltage signal, thereby reach the object that reduces display device power consumption.
Embodiment tetra-
The process flow diagram of the driving method of the array base palte that Fig. 8 provides for the embodiment of the present invention four, as shown in Figure 8, wherein this array base palte adopts the array base palte in above-described embodiment one or embodiment bis-, concrete structure can be referring to the description in above-described embodiment one or embodiment bis-, repeat no more, this driving method comprises herein:
Step 101: in a frame, switch control unit, under the control of timing control signal, is loaded on public voltage signal in public pressure wire, and data voltage signal is loaded on data line.
Step 102: in next frame, switch control unit is under the control of timing control signal, and just public voltage signal is loaded on data line, and data voltage signal is loaded in public pressure wire.
It should be noted that, the order of above-mentioned steps 101 and step 102 can exchange.
By perform step 101 and step 102 can make the positive negativity of the voltage difference of memory capacitance in pixel cell produce alternately to change, thereby realize the reversal of poles of the corresponding liquid crystal molecule of this pixel cell.Based on above-mentioned principle, this array base palte can be realized some reversion, row reversion and row reversion, and its detailed process can, referring to the description in above-described embodiment one or embodiment bis-, repeat no more herein.
The embodiment of the present invention four provides a kind of driving method of array base palte, in two adjacent frames, switch control unit switches the voltage signal loading in data line and public pressure wire, thereby realize the reversal of poles demand of liquid crystal molecule in display device, simultaneously, driving method provided by the invention can also effectively reduce the amplitude of oscillation of the voltage of data voltage signal, thereby reaches the object that reduces display device power consumption.
Be understandable that, above embodiment is only used to principle of the present invention is described and the illustrative embodiments that adopts, but the present invention is not limited thereto.For those skilled in the art, without departing from the spirit and substance in the present invention, can make various modification and improvement, these modification and improvement are also considered as protection scope of the present invention.
Claims (9)
1. an array base palte, it is characterized in that, comprise: common electric voltage generation unit, data voltage generation unit, timing control unit, some grid lines, data line and public pressure wire, described grid line and data line limit several pixel cells, described pixel cell comprises: the first display switch pipe and memory capacitance, the control utmost point of described the first display switch pipe is connected with the described grid line of corresponding row, first utmost point of described the first display switch pipe is connected with the described data line of respective column, second utmost point of described display switch pipe is connected with the first end of described memory capacitance, the second end of described memory capacitance is connected with the described public pressure wire of respective column,
Described array base palte also comprises: several switch control units, and described switch control unit is connected with described data line, described public pressure wire, described common electric voltage generation unit, described data voltage generation unit and described timing control unit;
Described common electric voltage generation unit is used for generating public voltage signal;
Described data voltage generation unit is for generated data voltage signal;
Described timing control unit is used for generating timing control signal;
Described switch control unit, under the control of described timing control signal, is loaded on described public voltage signal in described public pressure wire, and described data voltage signal is loaded on described data line; Or, described public voltage signal is loaded on described data line, and described data voltage signal is loaded in described public pressure wire.
2. array base palte according to claim 1, is characterized in that, described switch control unit comprises: the first gauge tap pipe, the second gauge tap pipe, the 3rd gauge tap pipe and the 4th gauge tap pipe;
The control of described the first gauge tap pipe, described the second gauge tap pipe, described the 3rd gauge tap pipe and described the 4th gauge tap pipe is extremely all connected with described timing control unit;
First utmost point of described the first gauge tap pipe is connected with described data voltage generation unit, and second utmost point of described the first gauge tap pipe is connected with described data line;
First utmost point of described the second gauge tap pipe is connected with described data voltage generation unit, and second utmost point of described the second gauge tap pipe is connected with described public pressure wire;
First utmost point of described the 3rd gauge tap pipe is connected with described common electric voltage generation unit, and second utmost point of described the 3rd gauge tap pipe is connected with public pressure wire;
First utmost point of described the 4th gauge tap pipe is connected with described common electric voltage generation unit, and second utmost point of described gauge tap pipe is connected with described data line.
3. array base palte according to claim 2, is characterized in that, described the first gauge tap pipe, the second gauge tap pipe, the 3rd gauge tap pipe and the 4th gauge tap pipe are metal oxide semiconductor field effect tube.
4. array base palte according to claim 2 described in, it is characterized in that, described timing control unit comprises a sequential control line, and the control utmost point of described the first gauge tap pipe, described the second gauge tap pipe, described the 3rd gauge tap pipe and described the 4th gauge tap pipe is connected with described sequential control line;
Described the first gauge tap pipe and described the 3rd gauge tap pipe are N-type transistor, and described the second gauge tap pipe and described the 4th gauge tap pipe are P transistor npn npn;
Or described the first gauge tap pipe and described the 3rd gauge tap pipe are P transistor npn npn, described the second gauge tap pipe and described the 4th gauge tap pipe are N-type transistor.
5. array base palte according to claim 2, it is characterized in that, described timing control unit comprises two sequential control lines, described the first gauge tap pipe is connected one bar of described sequential control line with the control utmost point of described the 3rd gauge tap pipe, described the second gauge tap pipe is connected another bar of sequential control line with the control utmost point of described the 4th gauge tap pipe, and the timing control signal loading in two described sequential control lines is contrary;
Described the first gauge tap pipe, described the second gauge tap pipe, described the 3rd gauge tap pipe and described the 4th gauge tap pipe are N-type transistor;
Or described the first gauge tap pipe, described the second gauge tap pipe, described the 3rd gauge tap pipe and described the 4th gauge tap pipe are P transistor npn npn.
6. array base palte according to claim 1, it is characterized in that, also comprise: the second display switch pipe, the control utmost point of described the second display switch pipe is connected with described grid line, first utmost point of described the second display switch pipe is connected with described public pressure wire, and second utmost point of described the second display switch pipe is connected with the second end of described memory capacitance.
7. array base palte according to claim 6, is characterized in that, described the second display switch pipe is thin film transistor (TFT).
8. a display device, is characterized in that, comprising: as the array base palte as described in arbitrary in the claims 1-7.
9. the driving method of an array base palte, it is characterized in that, described array base palte comprises: common electric voltage generation unit, data voltage generation unit, timing control unit, some grid lines, data line and public pressure wire, described grid line and data line limit several pixel cells, described pixel cell comprises: the first display switch pipe and memory capacitance, the control utmost point of described the first display switch pipe is connected with the described grid line of corresponding row, first utmost point of described the first display switch pipe is connected with the described data line of respective column, second utmost point of described display switch pipe is connected with the first end of described memory capacitance, the second end of described memory capacitance is connected with the described public pressure wire of respective column,
Described array base palte also comprises: several switch control units, and described switch control unit is connected with described data line, described public pressure wire, described common electric voltage generation unit, described data voltage generation unit and described timing control unit;
Described common electric voltage generation unit is used for generating public voltage signal;
Described data voltage generation unit is for generated data voltage signal;
Described timing control unit is used for generating timing control signal;
Described driving method comprises:
In a frame, described switch control unit, under the control of described timing control signal, is loaded on described public voltage signal in described public pressure wire, and described data voltage signal is loaded on described data line;
In next frame, described switch control unit is under the control of described timing control signal, and just described public voltage signal is loaded on described data line, and described data voltage signal is loaded in described public pressure wire;
Or in a frame, described switch control unit, under the control of described timing control signal, is loaded on described public voltage signal on described data line, and described data voltage signal is loaded in described public pressure wire;
In next frame, described switch control unit, under the control of described timing control signal, is loaded on described public voltage signal in described public pressure wire, and described data voltage signal is loaded on described data line.
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| CN201410302428.1A CN104102035B (en) | 2014-06-27 | 2014-06-27 | Array substrate and driving method thereof, as well as display device |
| US14/540,425 US9972272B2 (en) | 2014-06-27 | 2014-11-13 | Array substrate and driving method thereof, and display device |
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| CN201410302428.1A CN104102035B (en) | 2014-06-27 | 2014-06-27 | Array substrate and driving method thereof, as well as display device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105869599A (en) * | 2016-06-08 | 2016-08-17 | 武汉天马微电子有限公司 | Array substrate, driving method thereof and display panel |
| CN108922493A (en) * | 2018-09-21 | 2018-11-30 | 京东方科技集团股份有限公司 | A kind of driving circuit and its driving method, display device |
| CN113299244A (en) * | 2021-05-24 | 2021-08-24 | 京东方科技集团股份有限公司 | Voltage control module, driving method and display device |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104934007A (en) * | 2015-07-06 | 2015-09-23 | 合肥京东方光电科技有限公司 | Data line driving method and unit, source electrode driver, panel driving apparatus and display apparatus |
| CN110349549B (en) * | 2019-07-17 | 2022-07-05 | 京东方科技集团股份有限公司 | Driving method and driving circuit of liquid crystal display panel and display device |
| CN113823238A (en) * | 2021-09-26 | 2021-12-21 | 惠科股份有限公司 | Driving circuit of display panel and display device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050116654A1 (en) * | 2003-11-27 | 2005-06-02 | Hideo Sato | Display device |
| JP2007140191A (en) * | 2005-11-18 | 2007-06-07 | Epson Imaging Devices Corp | Active matrix type liquid crystal display device |
| CN101071240A (en) * | 2006-05-10 | 2007-11-14 | Lg.菲利浦Lcd株式会社 | Liquid crystal display panel, liquid crystal display device having the same, and driving method thereof |
| CN101334975A (en) * | 2007-06-28 | 2008-12-31 | 乐金显示有限公司 | Liquid crystal display and driving method thereof |
| CN102810304A (en) * | 2012-08-09 | 2012-12-05 | 京东方科技集团股份有限公司 | Pixel unit, pixel structure, display device and pixel driving method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100864918B1 (en) * | 2001-12-26 | 2008-10-22 | 엘지디스플레이 주식회사 | Apparatus for driving data of liquid crystal display |
| KR101843360B1 (en) * | 2010-12-24 | 2018-03-30 | 삼성디스플레이 주식회사 | Array substrate, display apparatus and method of operating the display apparatus |
| TWI549113B (en) * | 2015-05-29 | 2016-09-11 | 鴻海精密工業股份有限公司 | Display device |
-
2014
- 2014-06-27 CN CN201410302428.1A patent/CN104102035B/en not_active Expired - Fee Related
- 2014-11-13 US US14/540,425 patent/US9972272B2/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050116654A1 (en) * | 2003-11-27 | 2005-06-02 | Hideo Sato | Display device |
| JP2007140191A (en) * | 2005-11-18 | 2007-06-07 | Epson Imaging Devices Corp | Active matrix type liquid crystal display device |
| CN101071240A (en) * | 2006-05-10 | 2007-11-14 | Lg.菲利浦Lcd株式会社 | Liquid crystal display panel, liquid crystal display device having the same, and driving method thereof |
| CN101334975A (en) * | 2007-06-28 | 2008-12-31 | 乐金显示有限公司 | Liquid crystal display and driving method thereof |
| CN102810304A (en) * | 2012-08-09 | 2012-12-05 | 京东方科技集团股份有限公司 | Pixel unit, pixel structure, display device and pixel driving method |
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| CN105869599A (en) * | 2016-06-08 | 2016-08-17 | 武汉天马微电子有限公司 | Array substrate, driving method thereof and display panel |
| CN105869599B (en) * | 2016-06-08 | 2018-07-31 | 武汉天马微电子有限公司 | Array substrate, driving method thereof and display panel |
| CN108922493A (en) * | 2018-09-21 | 2018-11-30 | 京东方科技集团股份有限公司 | A kind of driving circuit and its driving method, display device |
| CN113299244A (en) * | 2021-05-24 | 2021-08-24 | 京东方科技集团股份有限公司 | Voltage control module, driving method and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104102035B (en) | 2017-01-18 |
| US20150379966A1 (en) | 2015-12-31 |
| US9972272B2 (en) | 2018-05-15 |
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