CN104094401A - Wire tail connector for a semiconductor device - Google Patents

Wire tail connector for a semiconductor device Download PDF

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Publication number
CN104094401A
CN104094401A CN201280068657.0A CN201280068657A CN104094401A CN 104094401 A CN104094401 A CN 104094401A CN 201280068657 A CN201280068657 A CN 201280068657A CN 104094401 A CN104094401 A CN 104094401A
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CN
China
Prior art keywords
naked core
bonding
moulding compound
naked
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201280068657.0A
Other languages
Chinese (zh)
Other versions
CN104094401B (en
Inventor
邱进添
俞志明
H.塔基亚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk Information Technology Shanghai Co Ltd
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SanDisk Information Technology Shanghai Co Ltd
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Publication date
Application filed by SanDisk Information Technology Shanghai Co Ltd filed Critical SanDisk Information Technology Shanghai Co Ltd
Publication of CN104094401A publication Critical patent/CN104094401A/en
Application granted granted Critical
Publication of CN104094401B publication Critical patent/CN104094401B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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  • Engineering & Computer Science (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A memory device, and a method of making the memory device, are disclosed. The memory device is fabricated by mounting one or more semiconductor die on a substrate, and wire bonding the die to the substrate. The die and wire bonds are encapsulated, and the encapsulated device is singulated. The wire bonds are severed during the singulation step, and thereafter the severed wire bonds are connected to the substrate by external connectors on one or more surfaces of the molding compound.

Description

For the buttock line connector of semiconductor device
Background technology
Strong growth in portable consumer electronic product demand has advanced the demand of high capacity storage device.Nonvolatile semiconductor memory device, for example flash card, is just being widely used for meeting the upper ever-increasing needs of digital information storage and exchange.Their portability, multifunctionality and robust design and their high reliability and large capacity, make such storage device ideally for the electronic installation of broad variety, for example, comprise digital camera, digital music player, video game console, PDA and mobile phone.
Although known the encapsulating structure of broad variety, flash card can be made as system in package (SiP) or many bare die module (MCM) conventionally, and wherein multiple naked cores are arranged on substrate with stacked structure.The edge view of conventional semiconductor package body 20 (there is no moulding compound) is illustrated in Fig. 1 and 2 of prior art.Typical packaging body comprises the multiple semiconductor naked cores 22,24 that are arranged on substrate 26.Be known that with certain side-play amount stacked semiconductor naked core (prior art Fig. 1) or with stacked structure stacked semiconductor naked core on top each other.In stacked structure, naked core 22,24 can be by separately (prior art Fig. 2) of wall 34, or by wherein burying underground from the rete of the Bonding of lower naked core separately.Although Fig. 1 and 2 do not illustrate, semiconductor naked core is formed with the naked core bonding welding pad on naked core upper surface.Substrate 26 can be formed by the electric insulation core being folded between upper and lower conductive layers.
Above and/or under conductive layer can be etched to form conductive pattern, comprise electrical lead and finger-type solder joint.Bonding can be connected between the naked core bonding welding pad of semiconductor naked core 22,24 and the finger-type solder joint of substrate 26, to be electrically connected semiconductor naked core to substrate.So the electrical lead on substrate provides circuit between naked core and host apparatus.Once set up the electrical connection between naked core and substrate, assembly is typically encapsulated in moulding compound (not shown) so that protectiveness encapsulation to be provided.
The length of substrate 26 and the whole length of sealing packaging body 20 therefore forming are greater than naked core 22,24.This one of them reason is on naked core and substrate, between Bonding position, to need space (Fig. 2) for Bonding capillary 32 to form Bonding between substrate 26 and naked core 22,24.If be formed as too close naked core to the Bonding of substrate 26, capillary 32 will contact the naked core of naked core in stacking before the connection forming on substrate.Naked core is stacking higher, and the space needing between Bonding position on naked core and substrate is larger.
Brief description of the drawings
Fig. 1 and 2 is the edge view that omits the prior art of two conventional semiconductor bulk encapsulation of moulding compound.
Fig. 3 is the flow chart of an embodiment of the disclosure.
Fig. 4 is in the first stage of manufacturing, install and Bonding to the stacking end view of naked core of the anchored bond pad on substrate.
Fig. 5 A is the vertical view of the naked core heap superimposition substrate shown in Fig. 4.
Fig. 5 B is the vertical view of the alternative embodiment shown in Fig. 5 A.
Fig. 6 A, 6B and 6C are the vertical views of the replacement panel construction before sealing according to the storage device of disclosure embodiment.
Fig. 7 is the end view the same with Fig. 4, also comprises moulding compound.
Fig. 8 is the vertical view of the heap of naked core shown in Fig. 7 superimposition substrate.
Fig. 9 is the end view the same with Fig. 7, and wherein a part for moulding compound, Bonding and substrate slices off from device point.
Figure 10 is the vertical view of semiconductor device shown in Fig. 9.
Figure 11 is the end-view of semiconductor device shown in Fig. 9.
Figure 12 is the end view the same with Fig. 9, also shows the aerial lug forming according to the outside of the moulding compound of disclosure embodiment.
Figure 13 is the vertical view of semiconductor device shown in Figure 12.
Figure 14 is the end-view of the semiconductor device shown in Figure 12.
Figure 15 is the perspective view of the semiconductor device shown in Figure 12.
Figure 16 is the perspective view that is stacked into multiple semiconductor devices of array in order to form aerial lug.
Figure 17 is the perspective view of the alternative embodiment of semiconductor device, at least both sides of semiconductor device, comprises aerial lug.
Figure 18,19 and 20 is respectively according to the end view of the semiconductor device of alternative embodiment of the present disclosure, vertical view and end-view.
Figure 21,22 and 23 is respectively that the semiconductor device of Figure 18-20 is cut apart and removes end view, vertical view and the end-view after moulding compound, bonding wire and a substrate part.
Figure 24 is the end-view the same with Figure 23, and it further shows aerial lug.
Figure 25 and 26 is vertical view and end-views of the semiconductor device cut apart, and this semiconductor device of cutting apart comprises the bonding wire on the outer surface that is exposed to moulding compound.
Figure 27 is the end-view the same with Figure 26, also shows exposure bonding wire on the outer surface of the connection mode plastics aerial lug to substrate.
Figure 28 is the end-view that the aerial lug structure of replacing shown in Figure 27 is shown.
Figure 29 is according to the perspective view of the semiconductor device of further embodiment, shows the aerial lug extending to another surface from a surface of moulding compound.
Embodiment
Now, describe embodiment with reference to Fig. 3 to Figure 29, it relates to the semiconductor device that comprises little length and/or width.In example, little length and/or width can be realized by forming bonding wire between the anchored bond pad on semiconductor naked core and substrate in naked core is stacking.After sealing, semiconductor device can be cut apart by this way, removes anchored bond pad and cuts off bonding wire to realize little length and/or width generally along their length.The bonding wire cutting off is exposed to the surface of moulding compound, and then can be electrically connected to the contact pad on substrate by the aerial lug forming on the surface of moulding compound.
Should be understood that the present invention can implement with different forms, is limited to and should not be construed as the embodiment setting forth here.On the contrary, it is for of the present disclosure thorough and complete that these embodiment are provided, and fully passes on the present invention to those skilled in the art.In fact, the present invention is intended to cover alternative, amendment and the equivalent of these embodiment, and it is included in the scope and spirit of the present invention that limit as claims.In addition,, in following detailed description of the present invention, in order to provide, thorough understanding of the present invention has been provided to numerous details.But those of ordinary skill in the art is noted that the present invention can implement in the situation that there is no these details.
The term that may adopt here " top (top) ", " end (bottom) ", " upper (top) ", " under (bottom) ", " vertically " and/or " level " be only in order to facilitate and the object of example, and have no intention the present invention to be limited to the exchange that referenced items can be in position.
Fig. 3 is the flow chart that is used to form the embodiment of micropodia mark storage device.First referring to Figure 4 and 5 A, semiconductor device 150 comprises substrate 152, and the naked core stacking 153 with semiconductor naked core 154,156,158 and 160 has been installed on it.Although the naked core shown in figure stacking 153 comprises four memory naked cores and a controller naked core, naked core is stacked in further embodiment can comprise more or less naked core.And, although Figure 4 and 5 A (with other figure) demonstrates single semiconductor device 150, but can understand device 150 can with on liner panel l76 multiple other device 150 together with in batch processing (Fig. 6 A), as illustrated below, to realize large-scale production.Line number and the columns of the device 150 on liner panel 176 can change.
Liner panel 176 starts from multiple substrates 152 (again, such substrate is illustrated in Figure 4 and 5 A).Substrate 152 can be different types of naked core mounting medium, comprises printed circuit board (PCB) (PCB), lead frame or the automatic splicing tpae of coil type (TAB).If substrate 152 is PCB, substrate can be become by the karyomorphism with top conductive layer and bottom conductive layer.Endorse by various dielectric substances and form, for example, polyimide laminates, the epoxy resin that comprises FR4 and FR5 and Bismaleimide Triazine (BT) etc.Although not bery strict for the present invention, the thickness that core has can at 40 microns, (μ be m) between 200 μ m, although the thickness of core can change in alternative embodiment outside this scope.Can be pottery or organic at alternative embodiment center.
Conductive layer around core can be by the copper of copper, copper alloy, plating or the copper alloy plating, copper steel plating or other metal and the known material for liner panel.Conductive layer can have the thickness of approximately 10 μ m to 25 μ m, although the thickness of these layers can change in alternative embodiment outside this scope.
In step 220, substrate 152 is holed with limited hole via hole (not shown) in substrate 152.Substrate 152 can be formed by multiple conductive layers, and this via hole can be from one deck to another layer of ac signal.Next,, in step 222, conductive pattern is formed on one or more conductive layers.Conductive pattern (one or more) can comprise electric trace line (not shown), contact pad 162 and one or more anchored bond pad 164 (in figure, only having numbered some pad 162,164).Shown in the quantity of contact pad 162 and anchored bond pad 164 be only example, and substrate 152 can comprise that they can be in different position to that indicated in the drawings than more contact pad and/or anchored bond pad shown in figure.Conductive pattern on top surface and/or the basal surface of substrate 152 can form by various known technique, for example, comprises various photoetching processes.
In the embodiment shown in Fig. 5 A, can there is contact pad 162 and the anchored bond pad 164 of equal number.Contact pad 162 can be in alignment with each other in the first row, and anchored bond pad 164 can be in alignment with each other on the second row.Each contact pad 162 can have corresponding anchored bond pad 164.In further embodiment, the quantity of contact pad 162 can be different from the quantity of anchored bond pad 164.As an example shown in Fig. 5 B, can have various contact pad 162, but single anchored bond pad 164 has the length together of the several anchored bond pad 164 shown in Fig. 5 A.
Referring to the flow chart of Fig. 2, next substrate 152 can check in the automatic optical detecting system (AOI) of step 224 again.Once after checking, can welding resistance mould (S/M) be applied to substrate in step 226, leave contact pad 162 and the anchored bond pad 164 of exposure.Applying after welding resistance mould, any other welding region on contact pad 162, anchored bond pad 164 and conductive pattern can be electroplate with Ni/Au etc. with known electro-plating method or thin film deposition processes in step 230.
Electroplated contact pads in known substrate contact pad and and the bonding wire of its welding between provide better and be electrically connected.But, as described below, needn't between bonding wire and anchored bond pad 164, provide best electrical connection, and bonding wire is not welded to contact pad 162.Therefore, in further embodiment, can omit electroplated contact pads 162 and/or anchored bond pad 164.As selection, electrodepositable contact pad 162 and/or anchored bond pad 164, but use the material outside Ni/Au.
Next can passive component (not shown) be fixed in step 240 to the top surface of substrate 152.Install and reflux technique by known surface, one or more passive components can be installed on substrate 152 and by being connected to contact pad electrical connection or being electrically coupled to conductive pattern.Passive component for example can comprise one or more capacitors, resistor and/or inductor, but also can imagine other element.
For example as shown in Figure 4 and as mentioned above, next can, in step 244, one or more semiconductor naked cores be fixed to the top surface of substrate 152.The embodiment of Fig. 5 comprises naked core stacking 153 and the controller naked core 161 of four flash memory naked cores 154,156,158 and 160.Memory naked core 154-160 for example can be flash chip (NOR/NAND), although also can imagine the memory naked core of other type.Controller naked core 161 for example can be ASIC.Controller naked core 161 and from it and come Bonding for the sake of clarity omit from other accompanying drawing.
Naked core in naked core stacking 153 can be stacked as and be in alignment with each other generally and (one deck being numbered in Fig. 4 separates to allow naked core bonding welding pad at substrate, and the each naked core in stacking 153 forms Bonding to naked core, as described below by rete 166.In further embodiment, although footprint that can amplification semiconductor device, naked core can be stacked into staggered ledge structure, and can omit rete 166.
After naked core in naked core stacking 153 has been arranged on substrate (or each naked core in naked core is stacking installed after), can in step 250, bonding wire 170 be connected between the naked core bonding welding pad 168 and one or more anchored bond pad 164 on each naked core.One or more anchored bond pad 164 can be separated a minimum range with naked core stacking 153, the risk not contacting with the stacking middle naked core of naked core so that all Bondings can be formed with Bonding capillary (not shown).This comprises that apart from basis the factor of naked core number in naked core stacking 153 changes.In further embodiment, one or more anchored bond pad 164 can be with naked core stacking 153 to be greater than the distance interval of this minimum range.
Although there is no Bonding to contact pad 162,, in one example, bonding wire can directly pass through on the contact pad between naked core bonding welding pad and anchored bond pad.In other words, as visible in the vertical view of Fig. 5 A, in one example, naked core bonding welding pad 168, contact pad 162 and anchored bond pad 164 can be in alignment with each other, thereby contact pad 162 can be connected with the bonding wire of shortest length 170 with corresponding anchored bond pad 164.This bonding wire 170 can directly pass through on contact pad 162.As described below, naked core bonding welding pad 168 can not align with the anchored bond pad being connected by bonding wire 170.
Needn't make anchored bond pad 164 electrically isolated from one with the each bonding wire 170 on each naked core.Therefore, for example, as shown in the embodiment of Fig. 5 B, several naked core bonding welding pads 168 can be connected to single anchored bond pad 164 by many bonding wires 170.
Fig. 6 A shows the panel 176 of semiconductor device 150.On two semiconductor devices 150, show that naked core is stacking 153, contact pad 162 and anchored bond pad 164.Seen in the view of the panel 176 installing in individual semiconductor device 150 and Fig. 6 A in Fig. 5 A, for each semiconductor device 150, on substrate 152, define forbidding region 178.As described below, forbidding region 178 is the regions that can amputate or saw in the time cutting apart monomer semiconductor device 150 from panel on substrate 152.Conventionally, the forbidding region on substrate 152 is the region without the structure such as contact pad.But according to the disclosure, anchored bond pad 164 can be formed in forbidding region 178, and is as described belowly removed during cutting apart.In conventional design, the contact pad of accepting Bonding can not be arranged in this forbidding region, and the size of substrate need to be greater than the technical program, thereby intactly leaves the contact pad of accepting Bonding in the time cutting apart substrate.
Fig. 6 A shows two row semiconductor devices 150, and every a line comprises the forbidding region 178 with anchored bond pad 164.Should be understood that the single forbidding region that can there is a line semiconductor device and comprise anchored bond pad 164.In addition, panel 176 can have the semiconductor device more than two row, and every row comprises the forbidding region with anchored bond pad 164.Although do not illustrate,, between adjacent semiconductor device 150, can there is forbidding region 178 in column, from the perspective view vertical orientation of Fig. 6 A.These vertical forbidding regions 178 also can or comprise the anchored bond pad of adhering to bonding wire 170 to it as selection.
In the embodiment of Fig. 6 A, the each semiconductor device 150 in every row comprises one or more anchored bond pad 164.Fig. 6 B shows the panel 176 according to alternative embodiment, and wherein the semiconductor device 150 of full line is shared an anchored bond pad, and it extends through the width of panel 176 generally.Therefore, comprise in the embodiment of two row semiconductor devices 150 having two anchored bond pad 164 at Fig. 6 B.Fig. 6 C shows the further embodiment of panel 176, and wherein top line semiconductor device is connected to substrate along hemline, and end row semiconductor device is connected to substrate along top line.In such embodiments, the semiconductor device in all semiconductor devices and end row in top line can be shared the single anchored bond pad 164 between row, and the length of extending generally panel 176.Imagine other structure, wherein two or more semiconductor devices 150 are shared the public anchored bond pad 164 in forbidding region 178.
In an embodiment, after bonding wire 170 is formed between the anchored bond pad 164 on naked core and the substrate 152 in naked core stacking 153, can in step 252, substrate and naked core be encapsulated in moulding compound 180, as shown in the end view of Fig. 7 and 8 and vertical view.Although not bery strict for the present invention, moulding compound 180 can be epoxy resin, for example, purchase in Sumitomo company (Sumito Corp.) or Dong electrician company (Nitto Denko Corp.), and the general headquarters of two companies are all in Japan.Also can imagine other moulding compound using from other manufacturer.Moulding compound can apply according to different technique, comprises transfer molding or injection-molded technology.
In further embodiment, encapsulating process can lead to and flows freely thin (FFT, Flow Free Thin) compressing technique and carry out.The compressing technique of such FFT is known, and for example at the Matsutani of the Towa of kyoto, Japan Corporation, H. the name of delivering in the Microelectronics and Packaging Conference of 2009 (microelectronics and encapsulation meeting) is called in the publication of " Compression Molding Solutions For Various High End Package And Cost Savings For Standard Package Applications " and is described, and this publication is incorporated to herein with way of reference entirety.
Moulding compound at least covers naked core in passive component, stacking 153 and bonding wire 170 (these parts be can't see from end-view and vertical view applying after moulding compound 180, but in order to understand the disclosure, have shown them in figure).
In step 252, after the semiconductor device 150 on encapsulated panels 176, can in step 256, cut apart each device from panel.Particularly, panel 176 cuts on vertical and horizontal in can the forbidding region 178 between adjacent semiconductor device 150.Each device 150 can be cut apart by any of various patterning methods, comprises sawing, water jet cutting, laser cutting, Water Jet Guided Laser cutting, the cutting of dry medium and the cutting of diamond coatings line.Although linear incision, by limiting the device 150 of essentially rectangular or square configuration, should be understood that in other embodiments of the invention, device 150 can have except rectangle and square shape.
The semiconductor device of cutting apart 150 with length L is illustrated in respectively in Fig. 9,10 and 11 end view, vertical view and end-view.As shown in the figure, segmentation step can be removed anchored bond pad 164 and cut by the bonding wire 170 of burying underground in moulding compound 180.This leaves the bonding wire 170 of shortening, as Fig. 9 and 10 visible.Also leave along cutting apart otch the tail end that bonding wire 170 exposes from the surface 182 of moulding compound, as shown in figure 11.For example, also as Fig. 9-11 finding, the part cutting apart otch and also can cut contact pad 162, also stays from the tail end of surface 182 exposures.
After cutting apart in step 256, can aerial lug 184 be applied to the outer surface of moulding compound in step 260, thus the tail end that connects the bonding wire 170 exposing to their suitable contact pads 162 to form functional semiconductor device.Aerial lug 184 is illustrated in respectively in Figure 12,13,14 and 15 end view, vertical view, end-view and perspective view.Aerial lug can be formed and can be applied by the whole bag of tricks by various electric conducting materials.As the indefiniteness example of material, aerial lug can be formed by copper, scolder or Ni/Au plating material.As the indefiniteness example of formation method, aerial lug can be by photoetching and other printing process, electroforming and other method for metallising, apply such as thin film deposition and the welding method of physical vapour deposition (PVD) and chemical vapour deposition (CVD).Also can imagine is electric conducting material and the formation method that uses other.
As mentioned above, in one embodiment, on each naked core of bonding wire 170 from naked core stacking 153, the naked core bonding welding pad 168 of vertical alignment extends to public anchored bond pad 164.
Therefore, in such embodiments, by cutting apart, from the alignment that also can be perpendicular to one another of the tail end of the bonding wire 170 of the naked core bonding welding pad of a set of vertical alignment, as shown in figure 11.And in an embodiment, the tail end of these vertical alignments also can align on the contact pad 162 on substrate 152.Therefore, in an embodiment, each aerial lug 184 can connect with length of material single, straight line the suitable tail end of bonding wire 170, as shown in FIG. 14 and 15.As more described in detail below, aerial lug can adopt non-rectilinear material to connect one group of Bonding tail end to contact pad in further embodiment.
Aerial lug 184 can be applied to the surface of multiple semiconductor devices to realize large-scale production and efficiency simultaneously.As shown in the perspective view of Figure 16, after cutting apart, the array of semiconductor device 150 can be in alignment with each other in the array of many row and columns, and wherein exposed surface 182 is accepted all for example, towards the equidirectional aerial lug of (upwards).Then, aerial lug can be applied to the exposed surface 182 of all semiconductor devices in array simultaneously.In one example, 100 semiconductor devices can provide in an array once to accept all aerial lugs, although the quantity of the semiconductor device in array can be more or less in further example.
In an embodiment, the width of aerial lug 184 can be close to the diameter of bonding wire 170, as shown in the figure.But for larger tolerance is provided, aerial lug 184 can have the width of the diameter that is greater than bonding wire 170.Aerial lug 184 can provide such width: allow all suitable bonding wires 170 to be electrically connected to their suitable contact pads 162, and isolate with other aerial lug 184 electricity, and bonding wire is not electrically connected to that contact pad 162.
In an embodiment, forming after aerial lug 184, aerial lug can be coated with protective layer, and it can be conformal coating, ink or adhesive coverage layer, to hide and to protect aerial lug.This protective layer can omit in further embodiment.
Adopt above-mentioned steps, can manufacture semiconductor device, make its footmark be less than the footmark that conventional manufacture method allows.In an example of conventional semiconductor device, the required distance between the stacking edge of naked core (forming Bonding from it) and the adjacently situated surfaces of moulding compound is at least 600 μ m.Adopt the technical program, between the stacking edge of naked core (forming Bonding from it) and the adjacently situated surfaces 182 of moulding compound, this distance can be reduced to 100 μ m.Conventional equipment and be only example according to these quantity of the device of the technical program.In the further embodiment of the technical program, the stacking distance forming between edge of Bonding and the adjacently situated surfaces of moulding compound 182 from it of naked core can be greater than 100 μ m, or is reduced to and is less than 100 μ m.
The benefit that the technical program provides is not only reducing in semiconductor device size.For example, because the bonding wire completing is shorter than conventional design, they can be set to more be close together than conventional design.On this permission naked core, on naked core bonding welding pad and substrate, on contact pad, form the more structure of crypto set.And the technical program is for providing greater flexibility from naked core to the substrate route signal of telecommunication.If conventional design has two-dimentional route (only in the plane of substrate), the technical program can realize three-dimensional route.Route can occur in the plane of substrate, but also can be along the wall of moulding compound (sidewall and roof).Therefore, circuit designers can design the three-dimensional routing plan than conventional semiconductor device design with larger flexibility and possibility.The indefiniteness example of this class design is as described below.
In above-mentioned example, bonding wire 170 forms from the single edge of naked core stacking 153.However, it should be understood that bonding wire 170 can form from naked core stacking 153 two opposite edges or neighboring edge, three edges or all four edges around.In such embodiments, bonding wire 170 can be made for to the anchored bond pad 164 of forbidding in region 178, then truncated during cutting apart as mentioned above.Afterwards, aerial lug can be formed on the each edge that comprises truncated bonding wire 170.In an example shown in Figure 17, bonding wire 170 forms from two neighboring edges.Therefore, in this embodiment, comprise that tail end that two neighboring edges of aerial lug 184 connect this bonding wire 170 is to contact pad 162.
As mentioned above, in the above-described embodiments, Bonding is vertically formed between naked core bonding welding pad, and naked core bonding welding pad is perpendicular to one another and aligns and align with contact pad and anchored bond pad 162,164.But, in further embodiment, can be other situation.For example, as shown in Figure 18,19 and 20 end view, vertical view and end-view, first set bonding wire 170a is formed between the naked core bonding welding pad 168 and anchored bond pad 164 of vertical alignment, but the second cover bonding wire 170b is formed between naked core bonding welding pad 168, and anchored bond pad 164 out of plumb that it is connected with them are alignd.
As the result of inclination bonding wire 170b, in the time that semiconductor device 150 is sealed and cut apart the tail end that leaves the Bonding in surface 182, some tail end is out of plumb alignment on contact pad 162.This example is illustrated in respectively in Figure 21,22 and 23 end view, vertical view and end-view.As Figure 22 and 23 findings, the tail end of the bonding wire 170a of vertical alignment aligns on their relevant contact pads 162, but the out of plumb alignment on their relevant contact pad 162 of the tail end of bonding wire 170b.
Therefore, in this embodiment, the bonding wire 170b of non-alignment can be connected to the discontinuous segment of aerial lug their relevant contact pad 162.For example, Figure 24 shows the tilting section 184b of aerial lug.Figure 21-24 provide an example, and should be understood that aerial lug 184 can have the discontinuous segment of other structure of broad variety in further embodiment.
In another example, all bonding wires 170 can be in naked core be stacking and with each anchored bond pad 164 vertical alignments, thereby cause the tail end of the vertical alignment of bonding wire 170, as shown in the vertical view of Figure 25 and 26 and end-view.But, can make circuit arrangement there is aerial lug, connect a row bonding wire 170 tail end to align with it those outside contact pad 162.Two such examples are illustrated in the end-view of Figure 27 and 28.In the example of Figure 27, two row bonding wires 170 are connected to the contact pad 162 of non-alignment by tilting section 184a.In the example of Figure 28, two row bonding wires 170 are connected to the contact pad 162 of non-alignment by horizontal segment 184a.Aerial lug has increased the flexibility in the circuit arrangement design not possessing in conventional design.
Figure 29 shows further flexibility, and wherein aerial lug 184 can be used for the tail end of connecting lead wire bonding, and just to the contact pad of non-alignment, but is connected to the contact pad of the non-alignment not arranging on ipsilateral completely of semiconductor device 150.In the example shown, aerial lug section 184b connects two row bonding wires to the naked core bonding welding pad 168 in the sides adjacent of semiconductor device 150.In addition, although when it conventionally can be all Bondings in a row Bonding and is all connected to identical contact pad 162, in further example, it can be other situation.The first assembly welding line 170 that Figure 29 shows in a row Bonding is connected to the first contact pad 162a by aerial lug 184c, and in these row second group is connected to the second contact pad 162b by the aerial lug 184d on the not homonymy of semiconductor device 150.Again, as can be seen, aerial lug has increased very large flexibility in the design of circuit layout, and allows to be formed as connecting naked core bonding welding pad 168 to contact pad 162 in the wide in range structure of being connected electrically in of many sizes.Example in Figure 29 shows several examples, but other very many structures is also possible and can imagines.
Once form electrical connection by aerial lug 184, can, in step 264, semiconductor device be tested, be appropriate to determine whether to be encapsulated in function.As known in the art, such test can comprise electricity experiment, burn and other test.
In a word, the technical program relates to a kind of storage device, comprising: substrate, comprises multiple contact pads; One or more semiconductor naked cores, comprise multiple naked core bonding welding pads; Moulding compound, seals one or more semiconductor naked cores; And circuit, the naked core bonding welding pad in a contact pad and multiple naked core bonding welding pad of electrical connection or the multiple contact pads of electric coupling, at least a portion of circuit is formed at least one outer surface of moulding compound.
In another example, the technical program relates to a kind of storage device, comprising: substrate, comprises multiple contact pads; One or more semiconductor naked cores, comprise multiple naked core bonding welding pads; Moulding compound, seals one or more semiconductor naked cores; And outside connection, provide on one or more surfaces of moulding compound, be electrically connected the naked core bonding welding pad in a contact pad and multiple naked core bonding welding pad of multiple contact pads for communication.
In further example, the technical program relates to a kind of storage device, comprising: substrate, comprises multiple contact pads; One or more semiconductor naked cores, comprise multiple naked core bonding welding pads; Moulding compound, seals one or more semiconductor naked cores, and a contact pad of multiple contact pads has the edge exposing on the surface of moulding compound.
In further example, the technical program relates to a kind of storage device, comprising: substrate, comprises multiple contact pads; Multiple semiconductor naked cores, the each naked core in multiple semiconductor naked cores comprises multiple naked core bonding welding pads; Moulding compound, seals one or more semiconductor naked cores; Many bonding wires, each bonding wire has the first end that is electrically connected to the naked core bonding welding pad in multiple naked core bonding welding pads, and each bonding wire has surface second tail end relative with first end that ends at moulding compound; And multiple outside connections, providing on one or more surfaces of moulding compound, multiple outside many bonding wires of electrical connection that connect are to the multiple contact pads on substrate.
In another example, the technical program relates to a kind of method that forms semiconductor device, comprising: one or more semiconductor naked cores (a) are installed on substrate; (b) this semiconductor naked core of Bonding is to this substrate; (c) seal this one or more semiconductor naked cores and bonding wire; (d) cut apart sealed semiconductor naked core by partly cutting off the Bonding forming in described step (b); And (e) Bonding that cuts off of electrical connection to this substrate.
For the object of example and description has presented aforementioned detailed description of the present invention.This has no intention to be exhaustive or to limit the invention to disclosed precise forms.Possible according to instruction many modifications and variations above.Described embodiment is chosen as and explains best principle of the present invention and practical application thereof, therefore make those skilled in the art can utilize best in different embodiment and the present invention with various amendments for being suitable for desired special-purpose.Scope of the present invention is defined by the following claims.

Claims (26)

1. a storage device, comprising:
Substrate, comprises multiple contact pads;
One or more semiconductor naked cores, comprise multiple naked core bonding welding pads;
Moulding compound, seals this one or more semiconductor naked cores; And
Circuit, is electrically connected the naked core bonding welding pad in a contact pad and the plurality of naked core bonding welding pad in the plurality of contact pad, and at least a portion of this circuit is formed at least one outer surface of this moulding compound.
2. device as claimed in claim 1, this part that is wherein formed on this circuit at least one outer surface of this moulding compound is connected to the bonding wire in this outer surface that ends at this moulding compound.
3. device as claimed in claim 2, this part that is wherein formed on this circuit on the outer surface of this moulding compound is connected to the tail end of the bonding wire in this outer surface that ends at this moulding compound.
4. device as claimed in claim 3, wherein this bonding wire comprises the end relative with this tail end, it is electrically connected to a naked core bonding welding pad of the plurality of naked core bonding welding pad.
5. device as claimed in claim 1, this part that is wherein formed on this circuit at least one outer surface of this moulding compound is formed on the single surface of this moulding compound.
6. device as claimed in claim 1, this part that is wherein formed on this circuit at least one outer surface of this moulding compound is formed at least two surfaces of this moulding compound.
7. a storage device, comprising:
Substrate, comprises multiple contact pads;
One or more semiconductor naked cores, comprise multiple naked core bonding welding pads;
Moulding compound, seals this one or more semiconductor naked cores; And
Outside connection, provides on one or more surfaces of this moulding compound, is electrically connected the naked core bonding welding pad in a contact pad and the plurality of naked core bonding welding pad of the plurality of contact pad for communication.
8. device as claimed in claim 7, also comprises a Bonding, and its first end is electrically connected to this naked core bonding welding pad, and second tail end relative with this first end ends at the surface of this moulding compound.
9. device as claimed in claim 7, wherein this aerial lug ends at the contact pad on the first surface of this semiconductor device and starts from this identical first surface.
10. device as claimed in claim 7, wherein this aerial lug ends at the contact pad on the first surface of this semiconductor device and starts from the second surface different from this first surface of this semiconductor device.
11. devices as claimed in claim 7, wherein this connector from start to finish extends to this contact pad and contacts with linear fashion.
12. devices as claimed in claim 7, wherein this connector comprises the Part I extending from its initial point and the Part II that ends at this contact pad, this Part I and this Part II relative to each other extend with discontinuous angle.
13. devices as claimed in claim 7, wherein these one or more semiconductor naked cores comprise at least two stacking semiconductor naked cores.
14. devices as claimed in claim 13, also be included in the electrical lead extending from naked core bonding welding pad in each of these at least two stacking semiconductor naked cores, this electrical lead ends at the surface of this moulding compound, and this aerial lug is electrically connected this electrical lead at least one contact pad to the plurality of contact pad.
15. 1 kinds of storage devices, comprising:
Substrate, comprises multiple contact pads;
One or more semiconductor naked cores, comprise multiple naked core bonding welding pads;
Moulding compound, seals this one or more semiconductor naked cores, and the contact pad in the plurality of contact pad has the edge exposing on the surface of this moulding compound.
16. devices as claimed in claim 15, one or more lip-deep outside connection thing provide at this moulding compound is also provided, is electrically connected a naked core bonding welding pad of this contact pad and the plurality of naked core bonding welding pad for communication.
17. devices as claimed in claim 15, also comprise Bonding, have and are electrically connected to the first end of this naked core bonding welding pad and surperficial second tail end that end at this moulding compound relative with this first end.
18. 1 kinds of storage devices, comprising:
Substrate, comprises multiple contact pads;
Multiple semiconductor naked cores, the each naked core in the plurality of semiconductor naked core comprises multiple naked core bonding welding pads;
Moulding compound, seals this one or more semiconductor naked cores;
Multiple bonding wires, each bonding wire has the first end that is electrically connected to the naked core bonding welding pad in the plurality of naked core bonding welding pad, and each bonding wire has surperficial second tail end that end at this moulding compound relative with this first end; And
Multiple outside connections, provide on one or more surfaces of this moulding compound, and the plurality of outside these many bonding wires of electrical connection that connect are to the plurality of contact pad on this substrate.
19. devices as claimed in claim 18, wherein the plurality of naked core bonding welding pad comprises naked core bonding welding pad group, be made up of a bonding welding pad in the each naked core coming from the plurality of naked core, the each naked core bonding welding pad in this naked core bonding welding pad group is partly electrically connected to the single contact pad in the plurality of contact pad by the aerial lug in the plurality of aerial lug.
20. devices as claimed in claim 19, form the straight line in the surface of this moulding compound jointly from the second tail end of this Bonding of each naked core bonding welding pad in this naked core bonding welding pad group.
21. devices as claimed in claim 19, this aerial lug connects the second tail end from this Bonding of this naked core bonding welding pad group, and this contact pad on this substrate forms straight line substantially.
22. devices as claimed in claim 19, this aerial lug connects the second tail end from this Bonding of this naked core bonding welding pad group, and this contact pad on this substrate forms line of discontinuity.
23. 1 kinds form the method for semiconductor device, comprising:
(a) one or more semiconductor naked cores are installed on substrate;
(b) this semiconductor naked core of Bonding is to this substrate;
(c) seal this one or more semiconductor naked cores and bonding wire;
(d) by being partly breaking at the Bonding forming in described step (b), cut apart sealed semiconductor naked core; And
(e) Bonding that electrical connection is cut off is to this substrate.
24. methods as claimed in claim 23, the Bonding that wherein said electrical connection is cut off is included in the step that forms aerial lug on the surface of this moulding compound to the step (e) of this substrate, the Bonding that this aerial lug is electrically connected this cut-out is to the contact pad on this substrate.
25. methods as claimed in claim 23, this semiconductor naked core of wherein said Bonding comprises the step of this semiconductor naked core of Bonding to the one or more pads on this substrate to the step (b) of this substrate, and these one or more pads are removed in the described step (d) of cutting apart the semiconductor naked core of sealing.
26. methods as claimed in claim 25, the Bonding of wherein said this cut-out of electrical connection comprises that to the step (e) of this substrate the Bonding that connects this cut-out is to the step of contact pad, and this contact pad separates with the middle one or more pads removed of described step (d).
CN201280068657.0A 2012-10-22 2012-10-22 For the tail circuit connector of semiconductor device Expired - Fee Related CN104094401B (en)

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