CN104078442A - Chip structure and manufacturing method thereof - Google Patents
Chip structure and manufacturing method thereof Download PDFInfo
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- CN104078442A CN104078442A CN201310336798.2A CN201310336798A CN104078442A CN 104078442 A CN104078442 A CN 104078442A CN 201310336798 A CN201310336798 A CN 201310336798A CN 104078442 A CN104078442 A CN 104078442A
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- Prior art keywords
- connection pad
- layer
- opening
- insulation layer
- patterned insulation
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000010410 layer Substances 0.000 claims abstract description 221
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000011241 protective layer Substances 0.000 claims abstract description 25
- 238000009413 insulation Methods 0.000 claims description 108
- 238000000034 method Methods 0.000 claims description 32
- 238000000059 patterning Methods 0.000 claims description 30
- 239000000463 material Substances 0.000 claims description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims description 18
- 239000004411 aluminium Substances 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical class O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000006855 networking Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Abstract
The invention provides a chip structure and a manufacturing method thereof. The chip comprises a substrate, a connecting pad arranged on the substrate and a protective layer covering the substrate and exposing the connecting pad. The first patterned insulating layer is disposed on the protective layer and has a first opening exposing a portion of the pad. The redistribution layer is arranged on the first patterned insulating layer and comprises a pad part and a wire part. The pad part is positioned on the first patterned insulating layer and is provided with a plurality of second openings which are independent from each other, positioned around the pad part and expose the first patterned insulating layer. The lead portion is connected with the pad portion and extends into the first opening to be connected with the pad. The second patterned insulating layer is disposed on the first patterned insulating layer, covers the periphery of the wire portion and the pad portion, and extends into the second opening to be connected with the first patterned insulating layer.
Description
Technical field
The invention relates to a kind of chip structure and manufacture method; Manufacture method especially in regard to a kind of chip structure and chip structure.
Background technology
In today of height information society, integrated antenna package technology need coordinate digitlization, networking, the joint area of electronic installation and the trend development that uses hommization.The making flow process of existing chip package is generally prior to forming one first dielectric layer on chip, on the first dielectric layer, form again a patterned circuit, in order to (the redistribution layer of the reconfiguration line layer as connection pad on chip, RDL), then again the second dielectric layer is disposed on the first dielectric layer, make patterned circuit between the first dielectric layer and the second dielectric layer, so that the connection pad position on chip is reshuffled.Yet; because the zygosity between dielectric layer and reconfiguration line layer is not good; and thermal coefficient of expansion (Coefficient of Thermal Expansion; CTE) also different; make the phenomenon that often there will be the second dielectric layer and reconfiguration line layer and the first dielectric layer to peel off in the process of thermal cycle (Thermal Cycle), and then yield and the reliability of impact encapsulation.
Summary of the invention
The invention provides a kind of chip structure, the zygosity between its dielectric layer is higher.
The invention provides a kind of manufacture method of chip structure, it can improve the zygosity between dielectric layer.
The present invention proposes a kind of chip structure, and it comprises a chip, a reconfiguration line layer, one first patterned insulation layer and one second patterned insulation layer.Chip comprises a base material, a connection pad and a protective layer.Connection pad is disposed on base material.Protective layer covering substrates also exposes connection pad.The first patterned insulation layer is disposed on protective layer and has one first opening.The first opening exposes part connection pad.Reconfiguration line layer is disposed on the first patterned insulation layer.Reconfiguration line layer comprises a connection pad portion and a wire portion.Connection pad portion is positioned on the first patterned insulation layer and has a plurality of the second openings independent of each other.The second opening is positioned at the surrounding of connection pad portion and exposes the first patterned insulation layer.Wire portion connects connection pad portion and extends in the first opening, to be connected with connection pad.The second patterned insulation layer is arranged on the first patterned insulation layer and covers wire portion and connection pad portion around, and extends in the second opening to be connected with the first patterned insulation layer.The second patterned insulation layer exposed portion connection pad portion.
The present invention proposes a kind of manufacture method of chip structure, and first it comprise the following steps:, a chip is provided.Chip comprises a base material, a connection pad and a protective layer.Connection pad is in being disposed on base material.Protective layer covering substrates also exposes connection pad.Then, form one first patterned insulation layer on protective layer.The first patterned insulation layer has one first opening.The first opening exposes part connection pad.Then, form a patterning photoresist layer on the first patterned insulation layer.Patterning photoresist layer has a plurality of column photoresistances independent of each other and a patterning opening.Patterning opening exposes the first patterned insulation layer and connection pad and comprises a connection pad pattern openings and a wire pattern opening.Connection pad pattern openings is positioned on the first patterned insulation layer, and column photoresistance is positioned at connection pad pattern openings around.Wire pattern opening connects connection pad pattern openings and extends to the first opening.Afterwards, form a conductive layer in patterning opening.Then, remove patterning photoresist layer, to form a reconfiguration line layer on the first patterned insulation layer.Reconfiguration line layer corresponding pattern melts the second opening a plurality of independent of each other that mouth comprises a connection pad portion, a wire portion and corresponding column photoresistance.The second opening is positioned at the surrounding of connection pad portion and exposes the first patterned insulation layer.Wire portion connects connection pad portion and extends in the first opening, to be connected with connection pad.Afterwards, form one second patterned insulation layer in the first patterned insulation layer and part reconfiguration line layer.The second patterned insulation layer extends in the second opening to be connected to the first patterned insulation layer exposed portion connection pad portion.
In one embodiment of this invention, described connection pad portion is rounded, and the second opening is curved and be jointly surrounded on connection pad portion around respectively.
In one embodiment of this invention, described chip structure more comprises a ball substrate (Under Bump Metallurgic, UBM) layer, is disposed at reconfiguration line layer below, and between reconfiguration line layer and the first patterned insulation layer and connection pad.
In one embodiment of this invention, described ball substrate layer more comprises a plurality of the 3rd openings independent of each other.The 3rd opening is positioned at the below of the second opening and is communicated with respectively the second opening.The second patterned insulation layer extension is filled in the 3rd opening to be connected to the first patterned insulation layer.
In one embodiment of this invention, the material of described connection pad comprises aluminium.
In one embodiment of this invention, the material of described reconfiguration line layer comprises copper.
In one embodiment of this invention, the manufacture method of described chip structure more comprised the following steps: before forming patterning photoresist layer, formed a ball substrate layer on the first patterned insulation layer.Ball substrate layer covers the first patterned insulation layer and connection pad.Remove after patterning photoresist layer, remove ball substrate layer and be not re-equipped the part of putting line layer covering.
In one embodiment of this invention, the method for described formation ball substrate layer on the first patterned insulation layer comprises sputter.
In one embodiment of this invention, the described ball substrate layer that removes is not re-equipped the method for putting the part that line layer covers and comprises etching.
In one embodiment of this invention, the method for described formation conductive layer in patterning opening comprises plating.
Based on above-mentioned, chip structure of the present invention and preparation method thereof arranges a plurality of openings around in the connection pad portion of reconfiguration line layer, the second patterned insulation layer can further be extended in opening to be connected with the first patterned insulation layer, to increase the grasping force between the second patterned insulation layer and reconfiguration line layer and the first patterned insulation layer, thereby reduce the peeling between the first patterned insulation layer and the second patterned insulation layer.Therefore, chip structure provided by the present invention and preparation method thereof can increase the reliability of chip structure and the technique yield of chip structure really.
Accompanying drawing explanation
Figure 1A to Fig. 1 J is the generalized section according to the manufacture method of a kind of chip structure of one embodiment of the invention.
Fig. 2 be according to a kind of chip structure of one embodiment of the invention schematic top plan view.
Fig. 3 be according to a kind of chip structure of another embodiment of the present invention schematic top plan view.
[symbol description]
100 chip structures
110 chips
112 base materials
114 connection pads
116 protective layers
120 first patterned insulation layers
122 first openings
130 reconfiguration line layer, conductive layer
132,232 connection pad portions
132a, 232a the second opening
134 wire portions
140 second insulating barriers
142 second patterned insulation layers
150 ball substrate layers
152 the 3rd openings
160 patterning photoresist layers
160a photoresist layer
162 column photoresistances
164 patterning openings
164a connection pad pattern openings
164b wire pattern opening
Embodiment
Figure 1A to Fig. 1 J is the generalized section according to the manufacture method of a kind of chip structure of one embodiment of the invention.Fig. 2 be according to a kind of chip structure of one embodiment of the invention schematic top plan view.Please refer to Figure 1A, in the present embodiment, first the manufacture method of chip structure comprises the following steps:, a chip 110 is provided, and its chips 110 comprises a base material 112, a connection pad 114 and a protective layer 116(passivation layer).Connection pad 114 is in being disposed on base material 112, and protective layer 116 covering substrates 112 expose at least part connection pad 114.In the present embodiment, connection pad 114 is for example positioned on an active surface of chip 110, and protective layer 116 covers the active surface of chip 110 and exposes at least part connection pad 114.The material of connection pad 114 is for example aluminium, the material of protective layer 116 such as silicon nitride, oxide and oxynitrides etc., and the method for formation protective layer 116 comprises chemical vapour deposition technique or physical vaporous deposition etc., but the present invention is not as limit.Then; please refer to Figure 1B, form one first patterned insulation layer 120 on protective layer 116, wherein the first patterned insulation layer 120 has one first opening 122; and the first opening 122 exposes part connection pad 114, and heat the first patterned insulation layer 120 and make its slaking.
Hold above-mentioned, please continue with reference to Fig. 1 C, form a ball substrate (Under Bump Metallurgic, UBM) layer 150 is on the first patterned insulation layer 120, and ball substrate layer 150 covers the first patterned insulation layer 120 and connection pad 114, using as connection pad 114 and the medium that engages that 130 of reconfiguration line layer are thereon set, and then increase the zygosity between connection pad and reconfiguration line layer 130.In the present embodiment, form the method for ball substrate layer 150 on the first patterned insulation layer 120 and comprise sputter.Then,, referring to Fig. 1 D and Fig. 1 E, form a patterning photoresist layer 160 on the first patterned insulation layer 120.In the present embodiment, the method that forms patterning photoresist layer 160 comprises that a photoresist layer 160a who first forms as shown in Fig. 1 D is on the first patterned insulation layer 120, then carry out again a Patternized technique, to form the patterning photoresist layer 160 as shown in Fig. 1 E, wherein, Patternized technique is for example exposure imaging technique.Patterning photoresist layer 160 has a plurality of column photoresistances 162 independent of each other and a patterning opening 164.Patterning opening 164 exposes the first patterned insulation layer 120 and connection pad 114, and patterning opening 164 comprises a connection pad pattern openings 164a and a wire pattern opening 164b.Connection pad pattern openings 164a is positioned on the first patterned insulation layer 120, and column photoresistance 162 is positioned at connection pad pattern openings 164a around.Wire pattern opening 164b connects connection pad pattern openings 164a and extends in the first opening 122.
Fig. 2 be according to a kind of chip structure of one embodiment of the invention schematic top plan view.Fig. 3 be according to a kind of chip structure of another embodiment of the present invention schematic top plan view.Hold above-mentionedly, please continue with reference to Fig. 1 F, form a conductive layer 130 in patterning opening 164.In the present embodiment, the mode that forms conductive layer 130 comprises plating, and the material of conductive layer 130 comprises copper.Then, referring to Fig. 1 F, Fig. 1 G and Fig. 2, remove patterning photoresist layer 160 and column photoresistance 162 as shown in Figure 1 F, to form reconfiguration line layer 130 as shown in Figure 1 G on the first patterned insulation layer 120, wherein, the shape of reconfiguration line layer 130 and profile can the corresponding vertical views with reference to Fig. 2.Reconfiguration line layer 130 correspondences as shown in Figure 1 F patterning opening 164 comprise a connection pad portion 132, a wire portion 134 and the corresponding second opening 132a a plurality of independent of each other of column photoresistance 162 as shown in Figure 1 F.The second opening 132a is positioned at the surrounding of connection pad portion 132 and exposes the first patterned insulation layer 120.Wire portion 134 connects connection pad portion 132 and extends in the first opening 122, to be connected with connection pad 114, so, can see through wire portion 134 connection pad 114 is electrically connected to connection pad portion 132.In the embodiment shown in Figure 2, connection pad portion 132 is rounded, and the second opening 132a is circular open, jointly around connection pad portion 132 around.Yet in the embodiment shown in fig. 3, connection pad portion 232 is also rounded, but the second opening 232a is curved and be jointly surrounded on connection pad portion 232 around respectively.Certainly, the column photoresistance in the present embodiment is also curved, to form corresponding arc the second opening 232a.At this, the present invention does not limit the shape of connection pad portion and the second opening, as long as the second opening is surrounded on the scope that the surrounding of connection pad portion is all institute of the present invention wish protection independently of one another and jointly.
Then, please refer to Fig. 1 H, remove ball substrate layer 150 and be not re-equipped the part of putting line layer 130 coverings, and corresponding to the second opening 132a, on ball substrate layer 150, form a plurality of the 3rd openings 152 independent of each other, wherein the 3rd opening 152 is positioned at the below of the second opening 132a and is communicated with respectively the second opening 132a and exposes the first patterned insulation layer 120.In the present embodiment, removing ball substrate layer 150 is not re-equipped the method for putting the part that line layer 130 covers and comprises etching.Afterwards, referring to Fig. 1 I and Fig. 1 J, form one second patterned insulation layer 142 in the first patterned insulation layer 120 and part reconfiguration line layer 130, wherein the second patterned insulation layer 142 extends in the second opening 132a and the 3rd opening 152 to be connected to the first patterned insulation layer 120 exposed portion connection pad portion 132.
So, can form the chip structure 100 shown in Fig. 1 J and Fig. 2, and the chip structure 100 completing can utilize the connection pad portion 132 exposing to be connected with for example conductive projection or wire, so that chip structure 100 is seen through and to be electrically connected on extraneous substrate or printed circuit board (PCB) such as modes such as covering crystalline substance or routing joint.In the present embodiment, the method that forms the second patterned insulation layer 142 comprise one second insulating barrier 140 first forming as shown in Figure 1 I make it cover the first patterned insulation layer 120 and reconfiguration line layer 130 and extend to the second opening 132a and the 3rd opening 152 in.Then carry out again a Patternized technique, to form the second patterned insulation layer 142 as shown in Fig. 1 J, expose part connection pad portion 132, afterwards, carry out again heating steps, make the second patterned insulation layer 142 slakings, and see through the 3rd opening 152 and the second opening 132a and the first patterned insulation layer 120 and be bonded to each other, wherein, Patternized technique is for example exposure imaging technique.
Particularly, according to the produced chip structure 100 of above-mentioned technique, it comprises a chip 110, a reconfiguration line layer 130, one first patterned insulation layer 120 and one second patterned insulation layer 142 as shown in Fig. 1 J and Fig. 2.Chip 110 comprises a base material 112, a connection pad 114 and a protective layer 116.Connection pad 114 is disposed on base material 112.Protective layer 116 covering substrates 112 also expose connection pad 114.In the present embodiment, the material of connection pad 114 is for example aluminium, the material of protective layer 116 such as silicon nitride, oxide and oxynitrides etc.The first patterned insulation layer 120 is disposed on protective layer 116 and has one first opening 122.The first opening 122 exposes part connection pad 114.Reconfiguration line layer 130 is disposed on the first patterned insulation layer 120.Reconfiguration line layer 130 comprises a connection pad portion 132 and a wire portion 134.Connection pad portion 132 is positioned on the first patterned insulation layer 120 and has a plurality of the second opening 132a independent of each other.The second opening 132a is positioned at the surrounding of connection pad portion 132 and exposes the first patterned insulation layer 120.Wire portion 134 connects connection pad portion 132 and extends in the first opening 122, to be connected with connection pad 114.The second patterned insulation layer 142 is arranged on the first patterned insulation layer 120 and covers wire portion 134 and connection pad portion 132 around, and extends in the second opening 132a to be connected with the first patterned insulation layer 120.The second patterned insulation layer 142 exposed portion connection pad portions 132.Certainly, in other embodiments of the invention, the second opening 232a is also can be as shown in Figure 3 curved and be jointly surrounded on circular connection pad portion 232 around respectively.At this, the present invention does not limit the shape of connection pad portion and the second opening, as long as the second opening is surrounded on the scope that the surrounding of connection pad portion is all institute of the present invention wish protection independently of one another and jointly.
In the present embodiment, chip structure 100 more comprises a ball substrate layer 150, be disposed at reconfiguration line layer 130 belows, and between reconfiguration line layer 130 and the first patterned insulation layer 120 and connection pad 114, using as connection pad 114 and the medium that engages that 130 of reconfiguration line layer are thereon set, and then increase the zygosity between connection pad 114 and reconfiguration line layer 130.In addition, ball substrate layer 150 more comprises a plurality of the 3rd openings 152 independent of each other, it is positioned at the below of the second opening 132a and is communicated with respectively the second opening 132a to expose the first patterned insulation layer 120, the second patterned insulation layer 142 extension is filled in the second opening 132a and the 3rd opening 152, to be connected to the first patterned insulation layer 120.Chip structure 100 as above, its second patterned insulation layer 142 sees through and extends in the second opening 132a and the 3rd opening 152 and be further connected with the first patterned insulation layer 120, thereby increased the grasping force of 120 of the second patterned insulation layer 142 and reconfiguration line layer 130 and the first patterned insulation layers, thereby can reduce the peeling of 142 of the first patterned insulation layer 120 and the second patterned insulation layers, thereby increase the technique yield of chip structure 100 and the reliability of chip structure 100.
In sum, chip structure of the present invention and preparation method thereof arranges a plurality of openings around in the connection pad portion of reconfiguration line layer, the second patterned insulation layer can further be extended in opening to be connected with the first patterned insulation layer, to increase the grasping force between the second patterned insulation layer and reconfiguration line layer and the first patterned insulation layer, thereby reduce the peeling between the first patterned insulation layer and the second patterned insulation layer.Therefore, chip structure provided by the present invention and preparation method thereof can increase the reliability of chip structure and the technique yield of chip structure really.
Although the present invention discloses as above with embodiment; so it is not in order to limit the present invention; under any, in technical field, have and conventionally know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on the appended claim person of defining.
Claims (10)
1. a chip structure, comprising:
One chip, comprises a base material, a connection pad and a protective layer, and this connection pad is disposed on this base material, and this protective layer covers this base material and exposes this connection pad;
One first patterned insulation layer, is disposed on this protective layer and has one first opening, and this first opening exposes this connection pad of part;
One reconfiguration line layer, be disposed on this first patterned insulation layer, this reconfiguration line layer comprises a connection pad portion and a wire portion, this connection pad portion is positioned on this first patterned insulation layer and has a plurality of the second openings independent of each other, described a plurality of the second opening is positioned at the surrounding of this connection pad portion and exposes this first patterned insulation layer, this wire portion connects this connection pad portion and extends in this first opening, to be connected with this connection pad; And
One second patterned insulation layer, be arranged on this first patterned insulation layer and cover this wire portion and this connection pad portion around, and it is interior to be connected with this first patterned insulation layer to extend to described a plurality of the second opening, this this connection pad portion of the second patterned insulation layer exposed portion.
2. chip structure according to claim 1, is characterized in that, this connection pad portion is rounded, and described a plurality of the second openings are curved and be jointly surrounded on this connection pad portion around respectively.
3. chip structure according to claim 1, is characterized in that, more comprises a ball substrate layer, is disposed at this reconfiguration line layer below, and between this reconfiguration line layer and this first patterned insulation layer and this connection pad.
4. chip structure according to claim 3, it is characterized in that, this ball substrate layer more comprises a plurality of the 3rd openings independent of each other, described a plurality of the 3rd opening is positioned at the below of described a plurality of the second openings and is communicated with respectively described a plurality of the second opening, and this second patterned insulation layer extension is filled in described a plurality of the 3rd opening to be connected to this first patterned insulation layer.
5. chip structure according to claim 1, is characterized in that, the material of this connection pad comprises aluminium.
6. chip structure according to claim 1, is characterized in that, the material of this reconfiguration line layer comprises copper.
7. a manufacture method for chip structure, comprising:
One chip is provided, and this chip comprises a base material, a connection pad and a protective layer, and this connection pad is in being disposed on this base material, and this protective layer covers this base material and exposes this connection pad;
Form one first patterned insulation layer on this protective layer, this first patterned insulation layer has one first opening, and this first opening exposes this connection pad of part;
Form a patterning photoresist layer on this first patterned insulation layer, this patterning photoresist layer has a plurality of column photoresistances independent of each other and a patterning opening, this patterning opening exposes this first patterned insulation layer and this connection pad and comprises a connection pad pattern openings and a wire pattern opening, this connection pad pattern openings is positioned on this first patterned insulation layer, described a plurality of column photoresistance is positioned at this connection pad pattern openings around, and this wire pattern opening connects this connection pad pattern openings and extends in this first opening;
Electroplate and form a conductive layer in this patterning opening;
Remove this patterning photoresist layer, to form a reconfiguration line layer on this first patterned insulation layer, this reconfiguration line layer is to should patterning opening comprising second opening a plurality of independent of each other of a connection pad portion, a wire portion and corresponding described a plurality of column photoresistances, described a plurality of the second opening is positioned at the surrounding of this connection pad portion and exposes this first patterned insulation layer, this wire portion connects this connection pad portion and extends in this first opening, to be connected with this connection pad; And
Form one second patterned insulation layer in this first patterned insulation layer and this reconfiguration line layer of part, this second patterned insulation layer extends in described a plurality of the second opening to be connected to this connection pad portion of this first patterned insulation layer exposed portion.
8. the manufacture method of chip structure according to claim 7, is characterized in that, this connection pad portion is rounded, and described a plurality of the second openings are curved and be jointly surrounded on this connection pad around respectively.
9. the manufacture method of chip structure according to claim 7, is characterized in that, more comprises:
Before forming this patterning photoresist layer, form a ball substrate layer on this first patterned insulation layer, this ball substrate layer covers this first patterned insulation layer and this connection pad; And
Remove after this patterning photoresist layer, remove the part that this ball substrate layer is not covered by this reconfiguration line layer.
10. the manufacture method of chip structure according to claim 9, is characterized in that, forms the method for this ball substrate layer on this first patterned insulation layer and comprises sputter.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW102110696A TWI524488B (en) | 2013-03-26 | 2013-03-26 | Chip structure and the manufacturing method thereof |
| TW102110696 | 2013-03-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN104078442A true CN104078442A (en) | 2014-10-01 |
Family
ID=51599622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310336798.2A Pending CN104078442A (en) | 2013-03-26 | 2013-08-05 | Chip structure and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN104078442A (en) |
| TW (1) | TWI524488B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000195891A (en) * | 1998-12-28 | 2000-07-14 | Samsung Electronics Co Ltd | Manufacture of semiconductor element |
| CN1463037A (en) * | 2002-05-27 | 2003-12-24 | 松下电器产业株式会社 | Semiconductor device and its mfg. method |
| CN102456661A (en) * | 2010-10-19 | 2012-05-16 | 矽品精密工业股份有限公司 | Chip structure with rewired circuit layer and manufacturing method thereof |
-
2013
- 2013-03-26 TW TW102110696A patent/TWI524488B/en active
- 2013-08-05 CN CN201310336798.2A patent/CN104078442A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000195891A (en) * | 1998-12-28 | 2000-07-14 | Samsung Electronics Co Ltd | Manufacture of semiconductor element |
| CN1463037A (en) * | 2002-05-27 | 2003-12-24 | 松下电器产业株式会社 | Semiconductor device and its mfg. method |
| CN102456661A (en) * | 2010-10-19 | 2012-05-16 | 矽品精密工业股份有限公司 | Chip structure with rewired circuit layer and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201438169A (en) | 2014-10-01 |
| TWI524488B (en) | 2016-03-01 |
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