CN104078358A - Method for producing MOS transistor - Google Patents
Method for producing MOS transistor Download PDFInfo
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- CN104078358A CN104078358A CN201310105929.6A CN201310105929A CN104078358A CN 104078358 A CN104078358 A CN 104078358A CN 201310105929 A CN201310105929 A CN 201310105929A CN 104078358 A CN104078358 A CN 104078358A
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- mos transistor
- dielectric layer
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- formation method
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- 238000004519 manufacturing process Methods 0.000 title abstract 3
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 239000004065 semiconductor Substances 0.000 claims abstract description 59
- 239000000243 solution Substances 0.000 claims abstract description 41
- 239000011737 fluorine Substances 0.000 claims abstract description 15
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 15
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 76
- 230000015572 biosynthetic process Effects 0.000 claims description 37
- 239000000463 material Substances 0.000 claims description 30
- 230000008569 process Effects 0.000 claims description 22
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 19
- 229910052739 hydrogen Inorganic materials 0.000 claims description 19
- 238000001039 wet etching Methods 0.000 claims description 14
- 238000000137 annealing Methods 0.000 claims description 13
- CYHANSWJPNHHIE-UHFFFAOYSA-N [Si].[Ni].[Co] Chemical group [Si].[Ni].[Co] CYHANSWJPNHHIE-UHFFFAOYSA-N 0.000 claims description 10
- 238000004140 cleaning Methods 0.000 claims description 10
- 238000003682 fluorination reaction Methods 0.000 claims description 10
- 239000000377 silicon dioxide Substances 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000001312 dry etching Methods 0.000 claims description 6
- 239000011259 mixed solution Substances 0.000 claims description 6
- 238000007669 thermal treatment Methods 0.000 claims description 6
- 229910017052 cobalt Inorganic materials 0.000 claims description 4
- 239000010941 cobalt Substances 0.000 claims description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical group [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 229910004129 HfSiO Inorganic materials 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 25
- 238000002347 injection Methods 0.000 abstract description 9
- 239000007924 injection Substances 0.000 abstract description 9
- 238000004334 fluoridation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 153
- 239000001257 hydrogen Substances 0.000 description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 238000005530 etching Methods 0.000 description 11
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 description 9
- 230000006378 damage Effects 0.000 description 8
- 238000002955 isolation Methods 0.000 description 7
- 239000002210 silicon-based material Substances 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- -1 hexafluoro silicon ammonium Chemical compound 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- VDRSDNINOSAWIV-UHFFFAOYSA-N [F].[Si] Chemical compound [F].[Si] VDRSDNINOSAWIV-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009415 formwork Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- DYCJFJRCWPVDHY-LSCFUAHRSA-N NBMPR Chemical compound O[C@@H]1[C@H](O)[C@@H](CO)O[C@H]1N1C2=NC=NC(SCC=3C=CC(=CC=3)[N+]([O-])=O)=C2N=C1 DYCJFJRCWPVDHY-LSCFUAHRSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910004490 TaAl Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- ZGDWHDKHJKZZIQ-UHFFFAOYSA-N cobalt nickel Chemical compound [Co].[Ni].[Ni].[Ni] ZGDWHDKHJKZZIQ-UHFFFAOYSA-N 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 238000009833 condensation Methods 0.000 description 1
- 230000005494 condensation Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- GPRLSGONYQIRFK-UHFFFAOYSA-N hydron Chemical compound [H+] GPRLSGONYQIRFK-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
Abstract
A method for producing an MOS transistor comprises the steps that a semiconductor substrate is provided, the surface of the semiconductor substrate is provided with dummy grids, side walls and dielectric layers, wherein the side walls are located at the two sides of the dummy grids, the semiconductor substrate and the side walls are covered with the dielectric layers, and the top surfaces of the dielectric layers are flush with the top surfaces of the dummy grids; the dummy grids are removed, so that openings are formed and parts of the surface of the semiconductor substrate are exposed through the openings; fluoridation is conducted on the parts, exposed through the openings, of the surface of the semiconductor substrate through a fluorine-containing solution, so that fluorine-containing surfaces are formed; interface layers are formed on the fluorine-containing surfaces; grid dielectric layers are formed on the interface layers and grid electrodes are formed on the grid dielectric layers. According to the method for producing the MOS transistor, the negative bias temperature instability effect and the hot carrier injection effect are lowered and the reliability of the MOS transistor is high.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of formation method of MOS transistor.
Background technology
Along with the development of semiconductor technology, the characteristic size of MOS transistor is constantly dwindled, and the thickness of the gate dielectric layer of MOS transistor also thins down by the principle of scaled down.Silicon oxide layer has reached its physics limit as gate dielectric layer, utilizes high-K gate dielectric layer replace oxygen SiClx gate dielectric layer, can in the situation that keeping equivalent oxide thickness (EOT) constant, greatly increase its physical thickness, thereby reduce grid leakage current.But because high-K gate dielectric layer is metal ion oxide mostly, and there is no fixing Atomic coordinate, its with silicon substrate between the degree of stability of bonding compared with the degree of stability of bonding between silica and silicon substrate, compare very different, cause between high-K gate dielectric layer and silicon substrate and have a large amount of boundary defects, transistorized integrity problem becomes the emphasis of research.
Negative Bias Temperature Instability (NBTI:negative bias temperature instability) effect usually occurs in PMOS transistor, when the grid of device is in back bias voltage lower time, saturated drain current and the mutual conductance of device constantly reduces, threshold voltage absolute value constantly increases.And this Negative Bias Temperature Instability effect that causes device performance decline, can be along with the increase of the bias voltage on grid and the rising of temperature and more remarkable.
In addition, along with reducing of MOS transistor channel length, in device operation process, it is very strong that the electric field of transistor channel region becomes, and makes the charge carrier ionization that bumps in course of conveying, produces extra electron hole pair, become hot carrier, longitudinal voliage makes part hot carrier injection grid oxide layer, causes the parameters such as threshold voltage of device to be drifted about, and forms comparatively serious hot carrier's effect (HCI:hot carrier injection).Because electronics is different from the mean free path in hole, the probability of electronic injection is high more a lot of than hole, so nmos pass transistor more easily causes hot carrier injection effect.
Therefore, in the MOS transistor that prior art forms, Negative Bias Temperature Instability effect and hot carrier injection effect are obvious, and reliability is not good.
Summary of the invention
The problem that the present invention solves be in the MOS transistor that forms of prior art Negative Bias Temperature Instability effect and hot carrier injection effect obvious, reliability is not good.
For addressing the above problem, the invention provides a kind of formation method of MOS transistor, comprise: Semiconductor substrate is provided, described semiconductor substrate surface has pseudo-grid, be positioned at the side wall of described pseudo-grid both sides, cover the dielectric layer of described Semiconductor substrate and described side wall, the top surface of described dielectric layer flushes with the top surface of described pseudo-grid; Remove described pseudo-grid, form opening, described opening exposes part semiconductor substrate surface; Adopt the part semiconductor substrate surface that fluorine-containing solution exposes described opening to carry out fluorination treatment, form fluorochemical surface; On described fluorochemical surface, form boundary layer; On described boundary layer, form gate dielectric layer, on described gate dielectric layer, form gate electrode.
Optionally, described fluorine-containing solution is HF solution, NH
4f solution or HF and NH
4f mixed solution.
Optionally, HF and H in described HF solution
2the mol ratio of O is 1:100.
Optionally, described boundary layer is oxide layer.
Optionally, the technique that forms described oxide layer is for adopting O
3solution or NH
4oH, H
2o
2and H
2the part semiconductor substrate surface that the mixed solution of O exposes described opening is processed.
Optionally, described pseudo-grid comprise pseudo-gate dielectric layer and pseudo-gate electrode layer, and described pseudo-gate electrode layer is positioned on described pseudo-gate dielectric layer.
Optionally, the material of described pseudo-gate dielectric layer is silica, and the material of described pseudo-gate electrode layer is polysilicon.
Optionally, the technique of removing described pseudo-grid comprises: adopt wet-etching technology or first dry etching again the technique of wet etching remove described pseudo-gate electrode layer; Adopt dry etch process to remove described pseudo-gate dielectric layer.
Optionally, described wet-etching technology adopts tetramethyl ammonium hydroxide solution.
Optionally, the dry etch process of removing described pseudo-gate dielectric layer is silicon cobalt nickel cleaning.
Optionally, described gate dielectric layer is high dielectric constant material.
Optionally, the material of described gate dielectric layer is HfO
2, Al
2o
3, ZrO
2, one or more in HfSiO, HfSiON, HfTaO and HfZrO.
Optionally, the material of described gate electrode is metal.
Optionally, the material of described gate electrode is cobalt.
Optionally, be also included on described boundary layer and form after gate dielectric layer, described gate dielectric layer is annealed.
Optionally, the annealing of described gate dielectric layer is comprised to Millisecond annealing and rapid thermal treatment.
Optionally, the temperature of described rapid thermal treatment is 600 degrees Celsius～800 degrees Celsius.
Optionally, be also included on described boundary layer and form after gate dielectric layer, on described gate dielectric layer, form work function layer.
Optionally, be also included in interior source region and the drain region of forming of Semiconductor substrate of described pseudo-grid both sides.
Compared with prior art, technical solution of the present invention has the following advantages:
In the formation method of the MOS transistor of the embodiment of the present invention, removing pseudo-grid, formation exposes after the opening of part semiconductor substrate surface, adopt the part semiconductor substrate surface that fluorine-containing solution exposes described opening to carry out fluorination treatment, the dangling bonds of the silicon materials of described semiconductor substrate surface react with fluorine ion and form silicon-fluorine (Si-F) key, form fluorochemical surface.Silicon-fluorine bond in described fluorochemical surface can reduce and prevent that the dangling bonds of silicon materials from reacting formation silicon-hydrogen (Si-H) key with hydrogen ion, because the bond energy of silicon-fluorine bond is greater than the bond energy of silicon-hydrogen bond, follow-up in the operating process of MOS transistor, under highfield effect, silicon-fluorine bond is not easy to be interrupted, can not form interface trapped charge, reduce Negative Bias Temperature Instability.In addition, because the bond energy of silicon-fluorine bond is higher, reduce the electron hole pair producing due to ionization by collision in carrier transport process, reduced hot carrier's effect.And while adopting part semiconductor substrate that fluorine-containing solution spills cruelly to described opening to carry out fluorination treatment, can not cause damage to semiconductor substrate surface.Follow-uply on described fluorochemical surface, form boundary layer, described boundary layer can also be as barrier layer, can prevent from overflowing after fluorine ion in fluorochemical surface from forming fluorine molecule again, prevents that the silicon-fluorine bond density in fluorochemical surface from reducing.
Further, in the formation method of the MOS transistor of the embodiment of the present invention, while removing described pseudo-grid, first adopt wet etching to remove pseudo-gate electrode layer, then adopt silicon cobalt nickel cleaning (SiCoNi Clean) technique to remove pseudo-gate dielectric layer.Described wet etching is removed pseudo-gate electrode layer and is adopted tetramethyl ammonium hydroxide solution; due to the higher etching selection ratio of wet etching; in removing the technique of described pseudo-gate electrode layer, pseudo-gate dielectric layer can be used as etching barrier layer, protects the Semiconductor substrate under pseudo-gate dielectric layer to avoid damage.In addition, remove the process using silicon cobalt nickel cleaning of described pseudo-gate dielectric layer, because silicon cobalt nickel cleaning is low intensive oxide chemistry lithographic method, compare with dry etching method, further reduced the damage of plasma bombardment effect to the Semiconductor substrate under pseudo-gate dielectric layer, and the damage of other oxide structures in semiconductor device has also further been reduced.
Accompanying drawing explanation
Fig. 1 to Fig. 6 is the cross-sectional view of forming process of the MOS transistor of the embodiment of the present invention.
Embodiment
From background technology, in the MOS transistor that prior art forms, Negative Bias Temperature Instability effect and hot carrier injection effect are obvious, and reliability is not good.
The present inventor is by the research of Negative Bias Temperature Instability effect in MOS transistor is found, Negative Bias Temperature Instability effect is mainly caused by the variation of silicon and gate dielectric layer interface trapped charge and Oxide trapped charge.In the silicon of grid and gate dielectric layer interface, exist the dangling bonds of some silicon, it is generally acknowledged that these dangling bonds are combined with hydrogen to form silicon-hydrogen (Si-H) key, be called hydrogen passivation.But in the transistor course of work, on grid, form a high electric field, now silicon-hydrogen bond is just easily interrupted, and forms H, H
+or H
2.The dangling bonds of silicon will attract electric charge like this, become interface trapped charge, cause Negative Bias Temperature Instability effect.In addition, in MOS transistor operating process, interface silicon-hydrogen bond bond energy is lower, channel region charge carrier under highfield with semiconductor lattice ionization by collision, easily produce extra electron hole pair, become hot carrier, described hot carrier is injected gate oxide under electric field action, forms hot carrier injection effect.
Based on above research, the present inventor proposes a kind of formation method of MOS transistor, removing pseudo-grid, formation exposes after the opening of part semiconductor substrate surface, adopt the part semiconductor substrate surface that fluorine-containing solution exposes described opening to carry out fluorination treatment, the dangling bonds of the silicon materials of described semiconductor substrate surface react with fluorine ion and form silicon-fluorine bond, form fluorochemical surface.Because the bond energy of silicon-fluorine bond is greater than the bond energy of silicon-hydrogen bond, follow-up in the operating process of MOS transistor, under highfield effect, silicon-fluorine bond is not easy to be interrupted, and can not form interface trapped charge, has reduced Negative Bias Temperature Instability.In addition, because the bond energy of silicon-fluorine bond is higher, reduce the electron hole pair producing due to ionization by collision in carrier transport process, reduced hot carrier's effect.
Below in conjunction with accompanying drawing, describe specific embodiment in detail, above-mentioned object and advantage of the present invention will be clearer.It should be noted that, the object that these accompanying drawings are provided is to contribute to understand embodiments of the invention, and should not be construed as restriction improperly of the present invention.For the purpose of clearer, size shown in figure not drawn on scale, may make and amplify, dwindle or other changes.
Please refer to Fig. 1, Semiconductor substrate 200 is provided, described Semiconductor substrate 200 surfaces have pseudo-grid 202, be positioned at the side wall 203 of described pseudo-grid 202 both sides, cover the dielectric layer 204 of described Semiconductor substrate 200 and described side wall 203, the top surface of described dielectric layer 204 flushes with the top surface of described pseudo-grid 202.
Described Semiconductor substrate 200 can be silicon or silicon-on-insulator (SOI), and described Semiconductor substrate 200 can be also germanium, germanium silicon, GaAs or germanium on insulator.In the present embodiment, described Semiconductor substrate 200 comprises territory, nmos area and PMOS region, and territory, described nmos area is for forming nmos pass transistor within it, and described PMOS region is for forming PMOS transistor within it.In the present embodiment, also comprise the isolation structure 201 between territory, described nmos area and PMOS region, described isolation structure 201 is for the active area in isolation of semiconductor substrate 200.In the present embodiment, described isolation structure 201 is fleet plough groove isolation structure (STI), and the material of described fleet plough groove isolation structure is silica, and the formation method of described fleet plough groove isolation structure please refer to existing technique, does not repeat them here.
Described Semiconductor substrate 200 surfaces have pseudo-grid 202.In rear grid (gate-last) technique, the described pseudo-grid 202 of follow-up removal, in the position of former pseudo-grid 202, form high-dielectric-coefficient grid medium layer and be positioned at the metal gates on described high-dielectric-coefficient grid medium layer again, form high-K metal gate (HKMG:High-K Metal Gate) structure, be conducive to improve breakdown voltage transistor, reduce leakage current, improve transistor performance.In the present embodiment, described pseudo-grid 202 comprise pseudo-gate dielectric layer 202a and pseudo-gate electrode layer 202b, and described pseudo-gate electrode layer 202b is positioned on described pseudo-gate dielectric layer 202a.In the present embodiment, the material of described pseudo-gate dielectric layer 202a is silica, and the material of described pseudo-gate electrode layer 202b is polysilicon.Described pseudo-grid 202 both sides have side wall 203, and the material of described side wall 203 can be silicon nitride, silica or silicon oxynitride.Described Semiconductor substrate 200 and described side wall 203 surface coverage have dielectric layer 204, and the top surface of described dielectric layer 204 flushes with the top surface of described pseudo-grid 202, and the material of described dielectric layer 204 is silica or silicon nitride.
In the present embodiment, also comprise and be located at described pseudo-grid 202 semiconductor substrates on two sides 200 interior formation source region and drain region (not shown).Accordingly, in the present embodiment, the source region in territory, nmos area and drain region are doped with N-type impurity, and the source region in PMOS region and drain region are doped with p type impurity.Described source region and drain region can be embedded source region and drain region, and described embedded source region and drain region form opening by the region in etching source region to be formed and drain region, and in described opening, extension stress material forms.In territory, nmos area, the material that forms described embedded source region and drain region can be carborundum, because the lattice constant of carborundum is less than the lattice constant of silicon, can introduce tensile stress at the channel region of nmos pass transistor, improves electron mobility; In PMOS region, the material that forms described embedded source region and drain region can be germanium silicon, because the lattice constant of germanium silicon is greater than the lattice constant of silicon, can introduce compression stress at the transistorized channel region of PMOS, improves hole mobility.
It should be noted that, the present embodiment be take the formation method of plane MOS transistor as example explanation technical solution of the present invention MOS transistor, but the formation method of the MOS transistor of technical solution of the present invention is equally applicable to form fin formula field effect transistor (Fin FET), should too not limit.
Please refer to Fig. 2, remove described pseudo-grid 202(with reference to figure 1), form opening 205, described opening 205 exposes part semiconductor substrate 200 surfaces.
In the present embodiment, described pseudo-grid 202 comprise pseudo-gate dielectric layer 202a and pseudo-gate electrode layer 202b, and the technique of therefore removing described pseudo-grid 202 comprises removes described pseudo-gate electrode layer 202b and described pseudo-gate dielectric layer 202a.In the present embodiment, the technique of removing described pseudo-gate electrode layer 202b is wet etching, and described wet etching adopts Tetramethylammonium hydroxide (TMAH:(CH
3)
4nOH) solution, in described tetramethyl ammonium hydroxide solution, the mass percent of Tetramethylammonium hydroxide is 1%～5%, solution temperature is 20 degrees Celsius～100 degrees Celsius.Due to tetramethyl ammonium hydroxide solution to the etch rate of polysilicon the etch rate far above silica; therefore in adopting the wet-etching technology of tetramethyl ammonium hydroxide solution; described pseudo-gate dielectric layer 202a, as etching stop layer, can protect the Semiconductor substrate 200 being positioned under described pseudo-gate dielectric layer 202a to avoid damage.In other embodiments, the technique of removing described pseudo-gate electrode layer 202b is first dry etching wet etching again, first adopts dry etch process to remove the described pseudo-gate electrode layer 202b of part, and described dry etching can be reactive ion etching, and etching gas comprises SF
6and Ar; Adopt again wet etching, pseudo-gate electrode layer 202b as described in tetramethyl ammonium hydroxide solution removal residue.
After removing described pseudo-gate electrode layer 202b, remove described pseudo-gate dielectric layer 202a.In the present embodiment, the technique of removing described pseudo-gate dielectric layer 202a is dry etching, and described dry etch process is that silicon cobalt nickel cleans (SiCoNi clean) technique.Silicon cobalt nickel cleaning is a kind of low intensive oxide chemistry lithographic method, and they are different from argon plasma bombardment technique, and silicon cobalt nickel cleaning is removed oxide in the environment that there is no plasma and Ions Bombardment, has reduced the destruction to base material.Described silicon cobalt nickel cleaning comprises: in etching cavity, pass into lower powered NF
3and NH
3plasma, the temperature of described etching cavity is 35 degrees Celsius; Described NF
3and NH
3reaction generates ammonium fluoride NH
4f and fluoram NH
4fHF, NH
4f and NH
4fHF is in the condensation of etching substrate surface, and preferential and oxide (SiO
2) reaction, form solid-state hexafluoro silicon ammonium (NH
4)
2siF
6and H
2o; Heating etching cavity, is elevated to more than 100 degrees Celsius the temperature of described etching substrate, makes solid-state hexafluoro silicon ammonium (NH
4)
2siF
6resolve into SiF
4, NH
3and HF, discharge etching cavity.Thinner thickness due to described pseudo-gate dielectric layer 202a, be generally nanometer scale, adopt silicon cobalt nickel cleaning to remove described pseudo-gate dielectric layer 202a, when can guarantee to remove described pseudo-gate dielectric layer 202a completely, the impact of the Semiconductor substrate 200 that described gate dielectric layer 202a is covered is less, is conducive to promote the performance of the MOS transistor of follow-up formation.In addition, adopt silicon cobalt nickel cleaning to remove described pseudo-gate dielectric layer 202a, can reduce other oxide structures in Semiconductor substrate 200, as the damage of interlayer dielectric layer (ILD:Inter-Layer Dielectric).
Remove after described pseudo-gate electrode layer 202b and pseudo-gate dielectric layer 202a, form opening 205, described opening 205 exposes part semiconductor substrate 200 surfaces.In rear grid technique, described opening 205 is used to form high-dielectric-coefficient grid medium layer and is positioned at the metal gates on described high-dielectric-coefficient grid medium layer.
Please refer to Fig. 3, adopt the part semiconductor substrate 200 that fluorine-containing solution exposes described opening 205 to carry out fluorination treatment, form fluorochemical surface 206.
Because described opening 205 exposes part semiconductor substrate 200 surfaces, if directly at the interior formation gate dielectric layer of described opening 205, there are dangling bonds in the interface under gate dielectric layer and gate dielectric layer, follow-up in device operation process, described dangling bonds can attract electric charge, become interface trapped charge, affect transistorized performance.Therefore in the present embodiment, fluorination treatment is carried out on part semiconductor substrate 200 surfaces that described opening 205 is exposed, and forms fluorochemical surface 206.
The part semiconductor substrate 200 that described opening 205 is exposed carries out fluorination treatment and adopts HF solution, NH
4f solution or HF and NH
4the mixed solution of F (BOE:Buffered Oxide Etch).In the present embodiment, the part semiconductor substrate 200 that adopts HF solution to expose described opening 205 carries out fluorination treatment, HF and H in described HF solution
2the mol ratio of O is 1:100.In the present embodiment, the material of described Semiconductor substrate 200 is silicon, after adopting HF solution to process described semiconductor substrate surface, the dangling bonds of the silicon materials on described Semiconductor substrate 200 surfaces react with fluorine ion and form silicon-fluorine (Si-F) key, form fluorochemical surface 206, prevented that the dangling bonds of silicon materials and hydrogen from forming silicon-hydrogen bond.Because the bond energy of silicon-fluorine bond is greater than the bond energy of silicon-hydrogen bond, follow-up in the operating process of MOS transistor, compared with under highfield, silicon-fluorine bond can be as silicon-hydrogen bond easy interrupting, can not form interface trapped charge, reduce Negative Bias Temperature Instability effect.In addition, because the bond energy of silicon-fluorine bond is higher, reduce the electron hole pair producing due to ionization by collision in carrier transport process, reduced hot carrier's effect.Compare with the method that adopts ion implantation technology to form silicon-fluorine bond in addition, adopt fluorine-containing solution to carry out fluorination treatment and can not cause damage on described Semiconductor substrate 200 surfaces, form defect layer.
Please refer to Fig. 4, on described fluorochemical surface 206, form boundary layer 207.
On described fluorochemical surface 206, form boundary layer 207 and can prevent the fluorine ion effusion in fluorochemical surface 206.In the present embodiment, described boundary layer 207 is oxide layer, and described fluorochemical surface 206 is the structure of monoatomic layer or polyatom layer, forms the technique of described oxide layer for adopting NH
4oH, H
2o
2and H
2process on part semiconductor substrate 200 surfaces that the mixed solution of O (SC1 solution) exposes described opening 205, wherein NH
4oH, H
2o
2and H
2the volume ratio of O is 1:1:5～1:2:7, and solution temperature is 65 degrees Celsius～80 degrees Celsius.In other embodiments, form the process using O of described oxide layer
3solution.Described boundary layer 207 is formed on described fluorochemical surface 206, as barrier layer, has prevented from overflowing after fluorine ion in described fluorochemical surface 206 from forming fluorine molecule again, causes the silicon-fluorine bond density in described fluorochemical surface 206 to reduce.In addition, follow-uply on described boundary layer 207, form high-dielectric-coefficient grid medium layer, described boundary layer 207 can also increase the adhesion between high-dielectric-coefficient grid medium layer and the Semiconductor substrate 200 of its below.
It should be noted that, after forming described fluorochemical surface 206, need on described fluorochemical surface 206, to form boundary layer 207 as early as possible, to reduce the effusion of fluorine ion in fluorochemical surface 206.In the present embodiment, described fluorochemical surface 206 and described boundary layer 207 form in same equipment.
Please refer to Fig. 5, on described boundary layer 207, form gate dielectric layer 208.
Described gate dielectric layer 208 has high-k, and the material of described gate dielectric layer 208 is HfO
2, Al
2o
3, ZrO
2, one or more in HfSiO, HfSiON, HfTaO and HfZrO.In the present embodiment, the material of described gate dielectric layer 208 is HfO
2.Form process chemistry vapour deposition or the ald of described gate dielectric layer 208, described gate dielectric layer 208 covers the surface of described boundary layer 207 and the sidewall of described side wall 203.It should be noted that described gate dielectric layer 208 also can cover the surface of described dielectric layer 204, during follow-up formation gate electrode, by CMP (Chemical Mechanical Polishing) process, remove in the lump the gate dielectric layer 208 that is positioned at described dielectric layer 204 surfaces.Because described gate dielectric layer 208 has higher dielectric constant, compare with silica, higher gate capacitance is provided when same thickness, stronger to the control ability of raceway groove, be conducive to improve transistor performance.
In the present embodiment, on described boundary layer 207, form after gate dielectric layer 208, described gate dielectric layer 208 is annealed.The described deposition after annealing (PDA:Post Deposition Annealing) that is annealed into, comprises Millisecond annealing (MSA:Millisecond Annealing) and rapid thermal treatment (RTA:Rapid Thermal Annealing).Described Millisecond annealing is laser rapid thermal annealing, and annealing temperature is 1000 degrees Celsius～1300 degrees Celsius, and annealing time is 600 milliseconds～800 milliseconds, and shorter annealing time can reduce Impurity Diffusion.The temperature of described quick thermal treatment process is 600 degrees Celsius～800 degrees Celsius.After above-mentioned deposition post growth annealing, the silicon-fluorine bond in fluorochemical surface 206 further strengthens, and fluorine ion can also with gate dielectric layer 208 in ion form chemical bond.In the present embodiment, the material of described gate dielectric layer 208 is hafnium oxide, so the fluorine ion in fluorochemical surface 206 and hafnium ion formation hafnium-fluorine bond (Hf-F).Because the bond energy of hafnium-fluorine bond and silicon-fluorine bond will be higher than the bond energy of hafnium-hydrogen bond and silicon-hydrogen bond, in the transistor course of work, be not easy to produce interfacial state, thereby improved the hot carrier's effect of the transistorized Negative Bias Temperature Instability effect of PMOS and nmos pass transistor.
Please refer to Fig. 6, on described gate dielectric layer 208, form gate electrode 209.
In the present embodiment, form gate electrode 209 on described gate dielectric layer 208 before, on described gate dielectric layer 208, form work function layer (not shown).Because PMOS transistor is different with nmos pass transistor threshold voltage, the transistorized work function layer material of nmos pass transistor and PMOS is also different.In the present embodiment, first form the mask layer that covers PMOS region, form NMOS work function layer on the gate dielectric layer 208 in territory, nmos area, described NMOS work function layer is the stacked structure of TiN and TiC, removes the mask layer that covers PMOS region; Form the mask layer that covers territory, nmos area again, form PMOS work function layer on the gate dielectric layer 208 in PMOS region, described PMOS work function layer is the stacked structure of TiN and TaAl, removes the mask layer that covers territory, nmos area.In other embodiments, can first form PMOS work function layer yet, then form NMOS work function layer, the material of described work function layer and thickness, according to concrete technology Location of requirement, should too not limit.
On described gate dielectric layer 208, form after work function layer, on described work function layer, form gate electrode 209, the material of described gate electrode 209 is metal.Described gate electrode 209 and the common formation high-K metal gate (HKMG) of gate dielectric layer 208 structure with high-k, be conducive to improve breakdown voltage transistor, reduce leakage current, improve transistor performance.In the present embodiment, the material of described gate electrode 209 is cobalt, and in other embodiments, the material of described gate electrode 209 can also be tantalum, tantalum nitride, nickle silicide, cobalt silicide etc.In the present embodiment, the technique that forms described gate electrode 209 comprises: adopt chemical vapor deposition method to form layer of gate electrode material (not shown) on described work function layer, described layer of gate electrode material is filled full described opening 205(with reference to figure 5), adopt CMP (Chemical Mechanical Polishing) process to grind described layer of gate electrode material, until expose the surface of described dielectric layer 204, the layer of gate electrode material that is positioned at described opening 205 forms gate electrode 209.
Follow-uply at MOS transistor source region and drain region correspondence position, form through hole, in described through hole, form conductive plunger, complete the preparation of MOS transistor, its concrete technology can, with reference to prior art, not repeat them here.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (19)
1. a formation method for MOS transistor, is characterized in that, comprising:
Semiconductor substrate is provided, and described semiconductor substrate surface has pseudo-grid, is positioned at the side wall of described pseudo-grid both sides, covers the dielectric layer of described Semiconductor substrate and described side wall, and the top surface of described dielectric layer flushes with the top surface of described pseudo-grid;
Remove described pseudo-grid, form opening, described opening exposes part semiconductor substrate surface;
Adopt the part semiconductor substrate surface that fluorine-containing solution exposes described opening to carry out fluorination treatment, form fluorochemical surface;
On described fluorochemical surface, form boundary layer;
On described boundary layer, form gate dielectric layer, on described gate dielectric layer, form gate electrode.
2. the formation method of MOS transistor as claimed in claim 1, is characterized in that, described fluorine-containing solution is HF solution, NH
4f solution or HF and NH
4the mixed solution of F.
3. the formation method of MOS transistor as claimed in claim 2, is characterized in that, HF and H in described HF solution
2the mol ratio of O is 1:100.
4. the formation method of MOS transistor as claimed in claim 1, is characterized in that, described boundary layer is oxide layer.
5. the formation method of MOS transistor as claimed in claim 4, is characterized in that, forms the technique of described oxide layer for adopting O
3solution or NH
4oH, H
2o
2and H
2the part semiconductor substrate surface that the mixed solution of O exposes described opening is processed.
6. the formation method of MOS transistor as claimed in claim 1, is characterized in that, described pseudo-grid comprise pseudo-gate dielectric layer and pseudo-gate electrode layer, and described pseudo-gate electrode layer is positioned on described pseudo-gate dielectric layer.
7. the formation method of MOS transistor as claimed in claim 6, is characterized in that, the material of described pseudo-gate dielectric layer is silica, and the material of described pseudo-gate electrode layer is polysilicon.
8. the formation method of MOS transistor as claimed in claim 7, is characterized in that, the technique of removing described pseudo-grid comprises: adopt wet-etching technology or the first dry etching described pseudo-gate electrode layer of technique removal of wet etching again; Adopt dry etch process to remove described pseudo-gate dielectric layer.
9. the formation method of MOS transistor as claimed in claim 8, is characterized in that, described wet-etching technology adopts tetramethyl ammonium hydroxide solution.
10. the formation method of MOS transistor as claimed in claim 8, is characterized in that, the dry etch process of removing described pseudo-gate dielectric layer is silicon cobalt nickel cleaning.
The formation method of 11. MOS transistor as claimed in claim 1, is characterized in that, described gate dielectric layer is high dielectric constant material.
The formation method of 12. MOS transistor as claimed in claim 11, is characterized in that, the material of described gate dielectric layer is HfO
2, Al
2o
3, ZrO
2, one or more in HfSiO, HfSiON, HfTaO and HfZrO.
The formation method of 13. MOS transistor as claimed in claim 1, is characterized in that, the material of described gate electrode is metal.
The formation method of 14. MOS transistor as claimed in claim 13, is characterized in that, the material of described gate electrode is cobalt.
The formation method of 15. MOS transistor as claimed in claim 1, is characterized in that, is also included on described boundary layer and forms after gate dielectric layer, and described gate dielectric layer is annealed.
The formation method of 16. MOS transistor as claimed in claim 15, is characterized in that, the annealing of described gate dielectric layer is comprised to Millisecond annealing and rapid thermal treatment.
The formation method of 17. MOS transistor as claimed in claim 16, is characterized in that, the temperature of described rapid thermal treatment is 600 degrees Celsius～800 degrees Celsius.
The formation method of 18. MOS transistor as claimed in claim 1, is characterized in that, is also included on described boundary layer and forms after gate dielectric layer, forms work function layer on described gate dielectric layer.
The formation method of 19. MOS transistor as claimed in claim 1, is characterized in that, is also included in interior source region and the drain region of forming of Semiconductor substrate of described pseudo-grid both sides.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104752168A (en) * | 2015-04-23 | 2015-07-01 | 上海华力微电子有限公司 | Method for removing defects of phosphorus-doped silicon carbide thin films in fin field-effect transistors |
| CN106504984A (en) * | 2015-09-07 | 2017-03-15 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of semiconductor devices |
| CN109065502A (en) * | 2017-06-13 | 2018-12-21 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| CN112563127A (en) * | 2019-09-26 | 2021-03-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
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2013
- 2013-03-28 CN CN201310105929.6A patent/CN104078358A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104752168A (en) * | 2015-04-23 | 2015-07-01 | 上海华力微电子有限公司 | Method for removing defects of phosphorus-doped silicon carbide thin films in fin field-effect transistors |
| CN104752168B (en) * | 2015-04-23 | 2017-10-17 | 上海华力微电子有限公司 | A kind of method of p-doped carborundum films defect in removal fin formula field effect transistor |
| CN106504984A (en) * | 2015-09-07 | 2017-03-15 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of semiconductor devices |
| CN106504984B (en) * | 2015-09-07 | 2019-04-19 | 中芯国际集成电路制造(上海)有限公司 | The preparation method of semiconductor devices |
| CN109065502A (en) * | 2017-06-13 | 2018-12-21 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| CN112563127A (en) * | 2019-09-26 | 2021-03-26 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN112563127B (en) * | 2019-09-26 | 2023-10-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
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Application publication date: 20141001 |