CN103928327A - Fin field effect transistor and forming method thereof - Google Patents
Fin field effect transistor and forming method thereof Download PDFInfo
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- CN103928327A CN103928327A CN201310009265.3A CN201310009265A CN103928327A CN 103928327 A CN103928327 A CN 103928327A CN 201310009265 A CN201310009265 A CN 201310009265A CN 103928327 A CN103928327 A CN 103928327A
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- 239000002184 metal Substances 0.000 claims description 11
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- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 claims description 8
- 229910004129 HfSiO Inorganic materials 0.000 claims description 7
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- 239000000428 dust Substances 0.000 claims description 6
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
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- 230000003071 parasitic effect Effects 0.000 abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 9
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a fin field effect transistor and a forming method thereof. The forming method of the fin field effect transistor comprises: providing a semiconductor substrate, the surface of the semiconductor substrate being provided with a projection fin portion and a grid structure which is disposed on the fin portion and covers a part of the top portion and the side wall of the fin portion; forming a first dielectric layer covering the grid structure; forming a second dielectric layer covering the first dielectric layer, the dielectric constant of the second dielectric layer being smaller than the dielectric constant of the first dielectric layer; etching back the second dielectric layer, and forming a second side wall; and etching the first dielectric layer by taking the second side wall as a mask, and forming a first side wall, the first side wall being provided with a horizontal portion and a vertical portion, the part of the fin portion covered by the first side wall constituting a negative covering zone. According to the invention, the parasitic capacitance between the grid structure of the fin field effect transistor and the conductive plug of a source region and a drain region is small.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of fin formula field effect transistor and forming method thereof.
Background technology
MOS transistor, by applying voltage at grid, regulates and produces switching signal by the electric current of channel region.Along with the development of semiconductor technology, traditional plane formula MOS transistor dies down to the control ability of channel current, causes serious leakage current.Fin formula field effect transistor (Fin FET) is a kind of emerging multiple-grid device, it generally comprises has the semiconductor fin that protrudes from semiconductor substrate surface, the top of fin and the grid structure of sidewall described in cover part, be positioned at source region and the drain region of the fin of described grid structure both sides.
But below 20 nanometer nodes, the thickness of fin formula field effect transistor fin is minimum, and short-channel effect is obvious, if threshold voltage is to changes in channel length sensitivity, carrier velocity saturation effect, hot carrier's effect and Sub-Threshold Characteristic degeneration etc.For addressing the above problem, prior art has proposed a kind of negative fin formula field effect transistor (FinFETs with underlaps) that hides district that has.Please refer to Fig. 1, for thering is the cross-sectional view of the negative fin formula field effect transistor that hides district, comprising: Semiconductor substrate 100; Be positioned at the fin 101 of the protrusion in described Semiconductor substrate 100, described fin 101 is by forming described Semiconductor substrate 100 etchings; The gate dielectric layer 103 on fin 101 surfaces described in cover part; Be positioned at the gate electrode layer 104 on described gate dielectric layer 103; Be positioned at the side wall 105 of described gate dielectric layer 103 and described gate electrode layer 104 both sides; Be positioned at source region and the drain region 102 of the fin 101 of described gate electrode layer 104 both sides; Be positioned at the negative covering district 106 of the fin 101 of described side wall 105 belows, the doping content in described negative covering district 106 is identical with the doping content of described fin formula field effect transistor channel region (not shown).
Have in the negative fin formula field effect transistor that hides district 106 above-mentioned, owing to injecting (Halo Implantation) for described negative covering district 106 not being carried out to lightly doped drain injection (LDD) and halo, the doping content in described negative covering district 106 is identical with the doping content of described fin formula field effect transistor channel region, increase effective channel region length, alleviated short-channel effect.But due to the existence in described negative covering district 106, channel resistance increases, cause the drive current of fin formula field effect transistor to decline, therefore, having in the negative fin formula field effect transistor that hides district 106, described side wall 105 adopts the dielectric material with high dielectric constant to form conventionally, reaches by improving the negative capacitance that hides district 106 object that promotes fin formula field effect transistor drive current.
But the side wall that prior art has the negative fin formula field effect transistor that hides district adopts high dielectric constant material to form, increase the parasitic capacitance between source region and the drain region conductive plunger of gate electrode and follow-up formation, affect transistor performance.
Other are about having the U.S. Patent application that the formation method of the negative fin formula field effect transistor that hides district can also be US2005/0275045A1 with reference to publication number.
Summary of the invention
It is large that the problem that the present invention solves is that prior art has parasitic capacitance between gate electrode and source region and the drain region conductive plunger of the negative fin formula field effect transistor that hides district.
For addressing the above problem, a kind of formation method that the invention provides fin formula field effect transistor, comprising: Semiconductor substrate is provided, and described semiconductor substrate surface has protruding fin, be positioned at the grid structure on described fin, top and the sidewall of fin described in described grid structure cover part; Form the first medium layer that covers described grid structure; Form the second medium layer that covers described first medium layer, the dielectric constant of described second medium layer is less than the dielectric constant of described first medium layer; Return second medium layer described in etching, form the second side wall; Taking described the second side wall as first medium layer described in mask etching, form the first side wall, described the first side wall has horizontal component and vertical component, and the part fin that described the first side wall covers forms the negative district (Gate under lap) that hides.
Optionally, the doping content in described negative covering district is identical with the channel region doping content of fin formula field effect transistor.
Optionally, the length range in described negative covering district is 300 dust ~ 500 dusts.
Optionally, the length range in described negative covering district is 10 dust ~ 50 dusts.
Optionally, also comprise: form the spacer medium layer, the upper surface of described spacer medium layer and the upper surface flush of described grid structure that cover described fin.
Optionally, also comprise: the vertical component of described the first side wall is carried out to Implantation, reduce the dielectric constant of the vertical component of described the first side wall.
Optionally, the injection ion of described ion implantation technology is hydrogen ion.
Optionally, also comprise: on described second medium layer, form the 3rd dielectric layer, return described in etching after the 3rd dielectric layer, form the 3rd side wall.
Optionally, the material of described the 3rd dielectric layer is silicon nitride.
Optionally, be also included in interior embedded source region and the drain region of forming of fin of described grid structure both sides.
Optionally, the material in described embedded source region and drain region is silicon, germanium silicon or carborundum.
Optionally, described embedded source region and drain region are doped with N-type or p type impurity.
Optionally, the material of described first medium layer is HfO
2, Al
2o
3, ZrO
2, one or more in HfSiO, HfSiON, HfTaO and HfZrO.
Optionally, the material of described second medium layer is one or more in SiCN, SiCON, SiBCN and SiBOCN.
Optionally, described grid structure is dummy grid.
Optionally, also comprise: remove described dummy grid, form the second opening, and form high-dielectric-coefficient grid medium layer and metal gates in described the second opening.
Corresponding, the present invention also provides a kind of fin formula field effect transistor, comprising: Semiconductor substrate, and described semiconductor substrate surface has protruding fin; Be positioned at the grid structure on described fin, top and the sidewall of fin described in described grid structure cover part; Be positioned at the first side wall of described grid structure both sides, described the first side wall has horizontal component and vertical component; Be positioned at the second side wall of described the first side wall both sides, described the second side wall is positioned on the horizontal component of described the first side wall, and the dielectric constant of described the second side wall is less than the dielectric constant of described the first side wall; Be positioned at the negative covering district of the part fin under described the first side wall.
Optionally, the doping content in described negative covering district is identical with the channel region doping content of fin formula field effect transistor.
Optionally, the material of described the first side wall is HfO
2, Al
2o
3, ZrO
2, one or more in HfSiO, HfSiON, HfTaO and HfZrO, the material of described the second side wall is one or more in SiCN, SiCON, SiBCN and SiBOCN.
Optionally, also comprise the 3rd side wall that is positioned at described the second side wall both sides, the material of described the 3rd side wall is silicon nitride.
Compared with prior art, the present invention has the following advantages:
In the formation method of the fin formula field effect transistor of the embodiment of the present invention, form and cover the first medium layer of described grid structure and be positioned at the second medium layer on described first medium layer, return second medium layer described in etching and form the second side wall, taking described the second side wall as first medium layer described in mask etching, form the first side wall, make described the first side wall there is horizontal component and vertical component.Because described the first side wall has horizontal component, and described the first side wall has higher dielectric constant, can improve the negative capacitance that hides district, to promote the drive current of fin formula field effect transistor.In addition, because the dielectric constant of described the second side wall is less than the dielectric constant of described the first side wall, after the conductive plunger in follow-up formation source region and drain region, can reduce the parasitic capacitance between grid structure and source region and drain region conductive plunger.The first side wall and the second sidewall structure that are the embodiment of the present invention can, in increasing negative covering district capacitance, reduce the parasitic capacitance between grid structure and source region and drain region.
Further, in the embodiment of the present invention, forming after spacer medium layer, the vertical component of described the first side wall is carried out to Implantation, the injection ion of described ion implantation technology is hydrogen ion, because hydrogen ion can react with the dielectric layer material of high-k, generates hydrogeneous layer of dielectric material, reduce the dielectric constant of the first side wall vertical component, can further reduce the parasitic capacitance of grid structure and source region and drain region conductive plunger.And because described the first Implantation is only for the vertical component of the first side wall, can not reduce the dielectric constant of the horizontal component of the first side wall, therefore can not affect the negative capacitance that hides district.
Corresponding, the fin formula field effect transistor of the embodiment of the present invention also has advantages of and reduces parasitic capacitance between grid structure and source region and the conductive plunger in drain region.
Brief description of the drawings
Fig. 1 is the perspective view of the fin formula field effect transistor of prior art;
Fig. 2 to Fig. 9 is the structural representation of the forming process of the fin formula field effect transistor of the embodiment of the present invention.
Embodiment
From background technology, the parasitic capacitance between gate electrode and source region and the drain region conductive plunger with the negative fin formula field effect transistor that hides district of prior art formation is large.
The present inventor has the formation method of the negative fin formula field effect transistor that hides district by research prior art, find that the side wall of high-k is to cause the large main cause of parasitic capacitance between gate electrode and source region and drain region conductive plunger.From formula C=ε S/4 π kd, in capacity plate antenna, capacitance size C and polar plate spacing d are inversely proportional to, and between pole plate, the DIELECTRIC CONSTANT ε of dielectric layer is inversely proportional to, and therefore can reduce the parasitic capacitance between gate electrode and source region and drain region by reducing the dielectric constant of spacer material.But due to having in the negative fin formula field effect transistor that hides district, it is in order to increase the negative electric capacity that hides district that described side wall adopts the object of dielectric layer of high dielectric constant, to improve the drive current of fin formula field effect transistor, therefore, can not simply described side wall be replaced with to the material of low-k, and need to adopt rational sidewall structure, in not reducing negative covering district electric capacity, reduce the parasitic capacitance between gate electrode and source region and drain region.
Based on above research, the present inventor has proposed a kind of formation method of fin formula field effect transistor, first on described grid structure, form first medium layer and be positioned at the second medium layer on first medium layer, the dielectric constant of described the second side wall is less than the dielectric constant of described the first side wall, return second medium layer described in etching and form the second side wall, taking described the second side wall as first medium layer described in mask etching, form the first side wall, make described the first side wall there is horizontal component and vertical component.The horizontal component of described the first side wall has higher dielectric constant, can improve the negative dielectric constant that hides district.The vertical component of described the second side wall and described the first side wall, between described grid structure and source region and the conductive plunger in drain region, because the dielectric constant of described the second side wall is less, can reduce the parasitic capacitance between grid structure and source region and drain region conductive plunger.
Describe specific embodiment in detail below in conjunction with accompanying drawing, above-mentioned object and advantage of the present invention will be clearer.
Fig. 2 to Fig. 9 is the structural representation of the forming process of the fin formula field effect transistor of the embodiment of the present invention.
Please refer to Fig. 2, Semiconductor substrate 200 is provided, described Semiconductor substrate 200 surfaces have protruding fin 202, are positioned at the grid structure 204 on described fin 202, top and the sidewall of fin 202 described in described grid structure 204 cover parts.
Described Semiconductor substrate 200 can be silicon or silicon-on-insulator (SOI), and described Semiconductor substrate 200 can be also germanium, germanium silicon, GaAs or germanium on insulator.Described Semiconductor substrate 200 surfaces have protruding fin 202, and described fin 202 can be one with the connected mode of described Semiconductor substrate 200, and for example described fin 202 is by the bulge-structure forming after described Semiconductor substrate 200 etchings.
Described grid structure 204 is positioned on described fin 202, top and the sidewall of fin 202 described in described grid structure 204 cover parts.In the present embodiment, described grid structure 204 is dummy grid, and the material of described dummy grid 204 is polysilicon.Described dummy grid 204 forms in technique at the rear grid of high-dielectric-coefficient grid medium layer and metal gates (HKMG), for reducing the high-dielectric-coefficient grid medium layer of follow-up formation and the heat budget of metal gates, is conducive to regulate the threshold voltage of MOS transistor.In subsequent technique, remove after described dummy grid 204, form successively gate dielectric layer and the metal gates of high-k in the position of dummy grid 204.
In another embodiment, described grid structure comprises gate dielectric layer and gate electrode layer, the material oxidation silicon of described gate dielectric layer, and the material of described gate electrode layer is polysilicon.
In the present embodiment, also comprise and be positioned at described Semiconductor substrate 200 surfaces, and the fleet plough groove isolation structure 201(STI of fin 202 sidewalls described in cover part), for the different fins in described Semiconductor substrate 200 are isolated, the material of described fleet plough groove isolation structure 201 is silica, the formation method of described fleet plough groove isolation structure 201 can, with reference to existing technique, not repeat them here.
Please refer to Fig. 3, Fig. 3 forms in the process of fin formula field effect transistor on the basis of Fig. 2, along the cross-sectional view of AA1 direction, forms the first medium layer 205 that covers described grid structure 204.
Concrete, adopt physical vapour deposition (PVD), chemical vapour deposition (CVD) or atom layer deposition process to form first medium layer 205 on described grid structure 204.Described first medium layer 205 is used to form the first side wall in subsequent technique.The material of described first medium layer 205 has higher dielectric constant, and for example material of described first medium layer is HfO
2, Al
2o
3, ZrO
2, one or more in HfSiO, HfSiON, HfTaO and HfZrO.Because described first medium layer 205 has higher dielectric constant, after follow-up formation the first side wall, can increase the negative capacitance that hides district (Gate under lap), improve the drive current of fin formula field effect transistor.
Please refer to Fig. 4, form the second medium layer 206 that covers described first medium layer 205, the dielectric constant of described second medium layer 206 is less than the dielectric constant of described first medium layer 205.
Concrete, adopt physical vapour deposition (PVD), chemical vapour deposition (CVD) or atom layer deposition process to form second medium layer 206 on described first medium layer 205.Described second medium layer 206 is used to form the second side wall in subsequent technique.The material of described second medium layer 206 has lower dielectric constant, and for example material of described second medium layer is one or more in SiCN, SiCON, SiBCN and SiBOCN.Because described second medium layer 206 has lower dielectric constant, after follow-up formation the second side wall, can reduce the parasitic capacitance between grid structure 204 and source region and drain region conductive plunger.
In another embodiment of the present invention, forming after the second medium layer that covers described first medium layer, also on described second medium layer, form the 3rd dielectric layer, the material of described the 3rd dielectric layer is silicon nitride, and the 3rd dielectric layer forms the 3rd side wall described in follow-up time etching.Described the 3rd side wall can, in the connector process in follow-up formation source region and drain region, as the etching barrier layer of via etch, reduce the damage of etching technics to grid structure.
Please refer to Fig. 5, return described in etching second medium layer 206(with reference to figure 4), form the second side wall 207.
Concrete, adopt dry etch process to return second medium layer 206 described in etching, in the present embodiment, adopt reactive ion etching process to return second medium layer 206 described in etching.Because reactive ion etching has good directivity, without forming mask, return described in etching after second medium layer 206, the second medium layer 206 that is only positioned at described grid structure 204 both sides retains formation the second side wall 207, and the second medium layer 206 that is positioned at described grid structure 204 tops and all the other regions is removed.On the one hand, the dielectric constant of described the second side wall 207 is lower, can reduce the parasitic capacitance between grid structure 204 and source region and drain region conductive plunger; On the other hand, described side wall 207 is positioned on described first medium layer 205, in the time that subsequent etching first medium layer 205 forms the first side wall, can be used as etch mask, makes the second side wall forming have horizontal component and vertical component.
Please refer to Fig. 6, taking described the second side wall 207 as first medium layer 205(described in mask etching is with reference to figure 5), form the first side wall 208, described the first side wall 208 has horizontal component 208a and vertical component 208b.
Concrete, adopt dry etch process to return first medium layer 205 described in etching, in the present embodiment, adopt first medium layer 205 described in reactive ion etching process etching.Because the part surface of described first medium layer 205 is covered by described the second side wall 207, therefore, taking described the second side wall 207 after first medium layer 205 described in mask etching forms the second side wall 208, the first medium layer 205 that is positioned at described grid structure 204 both sides forms the vertical component 208b of the second side wall 208, and the first medium layer 205 that is positioned at described the second side wall 207 belows forms the horizontal component 208a of the second side wall 208.
It should be noted that, second medium layer forms the technique that first medium layer described in the second side wall and etching forms the first side wall and can in same step etching technics, complete described in etching, and also etching technics completes in two steps.
Form after described the first side wall 208, the part fin 202 that described the first side wall 208 covers forms the negative district 209(Gate under lap of covering), the doping content in described negative covering district 209 is identical with the channel region (not shown) doping content of the fin formula field effect transistor of follow-up formation.Owing to can not carrying out in described negative covering district 209 subsequent techniques, lightly doped drain is injected and halo injects, and the doping content in described negative covering district 209 is lower, can increase the effective channel region length of fin formula field effect transistor, alleviates short-channel effect.
Low in order to solve negative covering district 209 doping contents, cause fin formula field effect transistor drive current to reduce, in prior art, conventionally need to adopt the side wall of high-k to improve the negative capacitance that hides district, but the side wall of high-k bring the adverse effect that between grid structure and source region and drain region conductive plunger, parasitic capacitance increases.In the present embodiment, adopt the bilateral wall construction of the first side wall 208 and the second side wall 207, the dielectric constant of described the second side wall 207 is less than the dielectric constant of described the first side wall 208, and described the first side wall 208 has horizontal component 208a and vertical component 208b.First side wall 208 of the present embodiment and the second side wall 207 can be realized by an etching technics, and technique is simple; Described the second side wall 207 has less dielectric constant can reduce the parasitic capacitance between the source region of grid structure 204 and follow-up formation and the conductive plunger in drain region; The horizontal component 208a of described the first side wall 208 has higher dielectric constant, can improve the negative capacitance that hides district 209, promotes the drive current of fin formula field effect transistor;
In the present embodiment, the length range in described negative covering district 209 is 10 dust ~ 50 dusts.Because the width in described negative covering district 209 is relevant with the threshold voltage of the fin formula field effect transistor of follow-up formation, therefore when the length in described negative covering district 209 hour, the threshold voltage of the fin formula field effect transistor of follow-up formation is less, be usually used in using as the transistor of logic region, to reduce power consumption.The length in described negative covering district 209 and the thickness of described first medium floor and second medium floor with close, therefore the thickness that the length range in described negative covering district 209 can deposit first medium floor and second medium floor by control regulates, and obtains the less negative covering district 209 of length.
In another embodiment, the thickness of described first medium layer and second medium layer is thicker, and the length range in the negative covering district 209 forming is 300 dust ~ 500 dusts.The fin formula field effect transistor of follow-up formation has higher threshold voltage, and the transistor that is usually used in input/input area uses, and makes it have higher threshold voltage and puncture voltage.
Please refer to Fig. 7, in the described grid structure embedded source region of the interior formation of 204 both sides fin 202 and drain region 210.
Concrete, the fin 202 of grid structure 204 both sides described in etching, form the first opening (not shown), and in described the first opening, adopt selective epitaxial process to form embedded source region and drain region 210, described selective epitaxial process can be chemical vapour deposition (CVD) or molecular beam epitaxy.
In the present embodiment, the material in described embedded source region and drain region 210 is silicon or carborundum, and for NMOS fin formula field effect transistor, described silicon or silicon carbide doped have N-type impurity.In the time that the material in described embedded source region and drain region 210 is silicon, the embedded source region forming and drain region volume are greater than the volume of the fin 202 being etched, be conducive to the formation of conductive plunger on follow-up source region and drain region, prevent due to the too small loose contact that causes metal plug and source region and drain region of fin 202 volumes.In the time that the material in described embedded source region and drain region 210 is carborundum, the embedded source region forming and drain region 210 are not only conducive to the formation of conductive plunger on follow-up source region and drain region, also be less than the lattice constant of silicon materials due to the lattice constant of carbofrax material, can introduce tensile stress at the channel region of NMOS fin formula field effect transistor, improve electron mobility.
In another embodiment, the material in described embedded source region and drain region 210 is silicon or germanium silicon, and for PMOS fin formula field effect transistor, described silicon or germanium silicon doping have p type impurity.In the time that the material in described embedded source region and drain region 210 is silicon, the embedded source region forming and the volume in drain region 210 are greater than the volume of the fin 202 being etched, be conducive to the formation of conductive plunger on follow-up source region and drain region, prevent the too small loose contact that causes conductive plunger and source region and drain region of volume due to fin 202.In the time that the material in described embedded source region and drain region 210 is germanium silicon, compression stress can also be introduced at the transistorized channel region of PMOS in the embedded source region of formation and drain region 210, improves hole mobility.
Please refer to Fig. 8, form the spacer medium layer 211 that covers described embedded source region and drain region 210, the upper surface flush of the upper surface of described spacer medium layer 211 and described grid structure 204.
In the present embodiment, adopt the technique of physical vapour deposition (PVD) or chemical vapour deposition (CVD) to form the spacer medium material layer that covers described embedded source region and drain region 210.Spacer medium material layer described in the polishing of employing CMP (Chemical Mechanical Polishing) process, taking the upper surface of described grid structure 204 as polishing stop layer, make the surface of described spacer medium material layer and the upper surface flush of described grid structure 204, described spacer medium material layer forms spacer medium layer 211.Described spacer medium layer 211 is for isolating described fin formula field effect transistor and external devices.
In another embodiment, be also included in and form after described spacer medium layer, the vertical component of described the first side wall is carried out to Implantation, reduce the dielectric constant of the vertical component of described the first side wall.The injection ion of described ion implantation technology is hydrogen ion, because hydrogen ion can react with the layer of dielectric material of high-k, generates the lower hydrogeneous layer of dielectric material of dielectric constant.For example, when the material of described the first side wall is HfO
2time, hydrogen ion with react, generate Hf or HfO
xh
y, Hf and HfO
xh
ydielectric constant be less than HfO
2.Due to the reduced dielectric constant of the vertical component of described the first side wall, can further reduce the parasitic capacitance between the conductive plunger on source region and the drain region of grid structure and follow-up formation.
Please refer to Fig. 9, remove described grid structure 204(with reference to figure 8), form the second opening (not shown), in described the second opening, form high-dielectric-coefficient grid medium layer 212 and metal gates 213.
In the present embodiment, described grid structure 204 is dummy grid, removes after described dummy grid, forms the second opening.Adopt chemical vapor deposition method or atom layer deposition process in described the second opening, to form the gate dielectric material layer of high-k, the material of described high-dielectric-constant gate dielectric material layer is HfO
2, Al
2o
3, ZrO
2, one or more in HfSiO, HfSiON, HfTaO and HfZrO.On the gate dielectric material layer of described high-k, form metal gate material layer, the material of described metal gate material layer is W, Al, Cu, Ti, Ta, TaN, NiSi, CoSi, TiN, one or more in TiAl and TaSiN.Metal gate material layer and high-dielectric-constant gate dielectric material layer described in the polishing of employing CMP (Chemical Mechanical Polishing) process, taking described spacer medium layer 211 as polishing stop layer, form high-dielectric-coefficient grid medium layer 212 and metal gates 213.
In another embodiment, described grid structure has comprised gate dielectric layer and gate electrode layer, adopts first grid technique (Gate first) to form, without removing described grid structure.
The follow-up through hole that exposes described embedded source region and surface, drain region that forms in described spacer medium layer forms the conductive plunger in source region and drain region in described through hole.Because the dielectric constant of described the second side wall is lower, reduce the parasitic capacitance between grid structure and source region and the conductive plunger in drain region.
Corresponding, please refer to Fig. 9, the present embodiment also provides a kind of fin formula field effect transistor, comprising: Semiconductor substrate 200, described semiconductor substrate surface has protruding fin 202; Be positioned at the grid structure on described fin 202, top and the sidewall of fin 202 described in described grid structure cover part, described grid structure comprises gate dielectric layer 212 and is positioned at the gate electrode layer 213 on described gate dielectric layer 212; The first side wall 208 that is positioned at described grid structure both sides, described the first side wall has horizontal component 208a and vertical component 208b; Be positioned at the second side wall 207 of described the first side wall 208 both sides, described the second side wall position 207 is upper in the horizontal component 208a of described the first side wall, and the dielectric constant of described the second side wall 207 is less than the dielectric constant of described the first side wall 208; Be positioned at the negative covering district 209 of the part fin 202 under described the first side wall 208.
In the present embodiment, the doping content in described negative covering district 209 is identical with the channel region (not shown) doping content of fin formula field effect transistor.
In the present embodiment, the material of described the first side wall 208 is HfO
2, Al
2o
3, ZrO
2, one or more in HfSiO, HfSiON, HfTaO and HfZrO, the material of described the second side wall 207 is one or more in SiCN, SiCON, SiBCN and SiBOCN.
In another embodiment, described fin formula field effect transistor also comprises the 3rd side wall that is positioned at described the second side wall both sides, and the material of described the 3rd side wall is silicon nitride.
Corresponding, the fin formula field effect transistor of the present embodiment adopts the formation method of above-mentioned fin formula field effect transistor to form, and therefore the fin formula field effect transistor of the present embodiment also has advantages of parasitic capacitance between the conductive plunger reducing on grid structure and source region and drain region.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology of above-mentioned announcement to make possible variation and amendment to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (20)
1. a formation method for fin formula field effect transistor, is characterized in that, comprising:
Semiconductor substrate is provided, and described semiconductor substrate surface has protruding fin, is positioned at the grid structure on described fin, top and the sidewall of fin described in described grid structure cover part;
Form the first medium layer that covers described grid structure;
Form the second medium layer that covers described first medium layer, the dielectric constant of described second medium layer is less than the dielectric constant of described first medium layer;
Return second medium layer described in etching, form the second side wall;
Taking described the second side wall as first medium layer described in mask etching, form the first side wall, described the first side wall has horizontal component and vertical component, and the part fin that described the first side wall covers forms the negative district that hides.
2. the formation method of fin formula field effect transistor as claimed in claim 1, is characterized in that, the doping content in described negative covering district is identical with the channel region doping content of fin formula field effect transistor.
3. the formation method of fin formula field effect transistor as claimed in claim 2, is characterized in that, the length range in described negative covering district is 300 dust ~ 500 dusts.
4. the formation method of fin formula field effect transistor as claimed in claim 2, is characterized in that, the length range in described negative covering district is 10 dust ~ 50 dusts.
5. the formation method of fin formula field effect transistor as claimed in claim 1, is characterized in that, also comprises: form the spacer medium layer, the upper surface of described spacer medium layer and the upper surface flush of described grid structure that cover described fin.
6. the formation method of fin formula field effect transistor as claimed in claim 5, is characterized in that, also comprises: the vertical component of described the first side wall is carried out to Implantation, reduce the dielectric constant of the vertical component of described the first side wall.
7. the formation method of fin formula field effect transistor as claimed in claim 6, is characterized in that, the injection ion of described ion implantation technology is hydrogen ion.
8. the formation method of fin formula field effect transistor as claimed in claim 1, is characterized in that, also comprises: on described second medium layer, form the 3rd dielectric layer, return described in etching after the 3rd dielectric layer, form the 3rd side wall.
9. the formation method of fin formula field effect transistor as claimed in claim 8, is characterized in that, the material of described the 3rd dielectric layer is silicon nitride.
10. the formation method of fin formula field effect transistor as claimed in claim 1, is characterized in that, is also included in interior embedded source region and the drain region of forming of fin of described grid structure both sides.
The formation method of 11. fin formula field effect transistors as claimed in claim 10, is characterized in that, the material in described embedded source region and drain region is silicon, germanium silicon or carborundum.
The formation method of 12. fin formula field effect transistors as claimed in claim 10, is characterized in that, described embedded source region and drain region are doped with N-type or p type impurity.
The formation method of 13. fin formula field effect transistors as claimed in claim 1, is characterized in that, the material of described first medium layer is HfO
2, Al
2o
3, ZrO
2, one or more in HfSiO, HfSiON, HfTaO and HfZrO.
The formation method of 14. fin formula field effect transistors as claimed in claim 1, is characterized in that, the material of described second medium layer is one or more in SiCN, SiCON, SiBCN and SiBOCN.
The formation method of 15. fin formula field effect transistors as claimed in claim 1, is characterized in that, described grid structure is dummy grid.
The formation method of 16. fin formula field effect transistors as claimed in claim 15, is characterized in that, also comprises: remove described dummy grid, form the second opening, and form high-dielectric-coefficient grid medium layer and metal gates in described the second opening.
17. 1 kinds of fin formula field effect transistors, is characterized in that, comprising:
Semiconductor substrate, described semiconductor substrate surface has protruding fin;
Be positioned at the grid structure on described fin, top and the sidewall of fin described in described grid structure cover part;
Be positioned at the first side wall of described grid structure both sides, described the first side wall has horizontal component and vertical component;
Be positioned at the second side wall of described the first side wall both sides, described the second side wall is positioned on the horizontal component of described the first side wall, and the dielectric constant of described the second side wall is less than the dielectric constant of described the first side wall;
Be positioned at the negative covering district of the part fin under described the first side wall.
18. fin formula field effect transistors as claimed in claim 17, is characterized in that, the doping content in described negative covering district is identical with the channel region doping content of fin formula field effect transistor.
19. fin formula field effect transistors as claimed in claim 17, is characterized in that, the material of described the first side wall is HfO
2, Al
2o
3, ZrO
2, one or more in HfSiO, HfSiON, HfTaO and HfZrO, the material of described the second side wall is one or more in SiCN, SiCON, SiBCN and SiBOCN.
20. fin formula field effect transistors as claimed in claim 17, is characterized in that, also comprise the 3rd side wall that is positioned at described the second side wall both sides, and the material of described the 3rd side wall is silicon nitride.
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