CN104063341A - TBT (thunderbolt) chip integration system and method - Google Patents

Abstract

The invention discloses a TBT (thunderbolt) chip integration system and method which are applied to a processor of a mainboard. The mainboard comprises a PCIe (peripheral component interface express) slot, a system bus and a BIOS (basic input-output system), wherein the mainboard is connected with a PCIe external card through the PCIe slot. The system comprises an integration module, a setting module and a control module, wherein the integration module is used for integrating a TBT chip, a micro-control unit and an EEPROM (electrically erasable programmable read-only memory) on the PCIe external card and inserting the PCIe external card into the PCIe slot, so that the TBT chip and the micro-control unit are connected onto the system bus; the setting module is used for defining the micro-control unit to support a TBT protocol parameter table of the TBT chip and setting required GPIO (general purpose input/output) signal parameters for supporting the TBT chip through the BIOS; and the control module is used for associating signal pins of the micro-control unit with the TBT chip according to the GPIO signal parameters and controlling the TBT chip to execute a corresponding TBT protocol function through the GPIO signals output by the system bus.

Description

TBT chip integration system and method

technical field

The invention relates to an I/O port integration system and method, in particular to a TBT chip integration system and method.

Background technique

Thunderbolt (TBT for short) is a connector standard published by Intel. The TBT chip is a high-speed I/O port with a very high data transmission rate. It has the characteristics of fast data transmission speed and diversified functions, including high-performance peripheral equipment (PCI Express, PCIe) functions and high-resolution display functions. If it is necessary to fully support all functions of the TBT chip on the motherboard, an additional seven lines are required to be pulled to the GPIO of the North-South Bridge (PCH) for processing.

At present, the design of the TBT chip is generally designed on the motherboard (TBT On Board). Although this design is convenient, it will occupy a set of PCIe slots (Slot), which lacks the flexibility of PCIe expansion, and the motherboard is a special Motherboards that support TBT. In the conventional technology, the design carrying the TBT chip can also be integrated on an external card (TBT On Card). Referring to FIG. 1, the TBT chip 10 is integrated on the PCIe external card 1. When the PCIe external card 1 is inserted into the PCIe slot 21 of the motherboard 2, seven additional lines (Fly-Wire) must be pulled to the north-south bridge (PCH ) 22 GPIO to handle. This design will result in the assembly of the design of the main board 2, which requires an extra external wire for packaging seven lines, such as the external wire Cable-2 shown in FIG. 1 .

Contents of the invention

In view of the above, it is necessary to provide a TBT chip integration system and method, which can integrate the TBT chip on a standard PCIe external card without connecting additional external wires, and update the BIOS of the standard PCIe motherboard to support the TBT protocol function .

The TBT chip integrated system is integrated in the processor of the motherboard, and the motherboard includes a PCIe slot, a system bus and a BIOS system, and the motherboard is connected with a PCIe external card through the PCIe slot. Described TBT chip integrated system comprises: integrated module, is used for integrating TBT chip, micro control unit and EEPROM on the PCIe external card, and PCIe external card is inserted in the PCIe slot so that TBT chip and micro control unit are connected to On the system bus of the motherboard; the setting module is used to define the TBT protocol parameter table of the TBT chip supported by the micro-control unit, store the TBT protocol parameter table in the EEPROM, and set the micro-control unit support according to the TBT protocol parameter table through the BIOS system The GPIO signal parameters required by the TBT chip; the control module is used to associate each signal pin of the micro-control unit with the TBT chip according to the set GPIO signal parameters to support the TBT protocol function, and output GPIO signal control through the system bus The TBT chip executes the corresponding TBT protocol functions.

The TBT chip integration method is applied to the processor of the motherboard, and the motherboard includes a PCIe slot, a system bus and a BIOS system, and the motherboard is connected with a PCIe external card through the PCIe slot. The method includes: integrating the TBT chip, the micro control unit and the EEPROM on the PCIe external card; inserting the PCIe external card into the PCIe slot to connect the TBT chip and the micro control unit to the system bus of the main board; defining the support of the micro control unit The TBT protocol parameter table of the TBT chip, and store the TBT protocol parameter table in the EEPROM; set the GPIO signal parameters required by the micro-control unit to support the TBT chip through the BIOS system according to the TBT protocol parameter table; according to the set GPIO signal parameters Correlating each signal pin Pin of the micro control unit with the TBT chip to support the TBT protocol function; and outputting the GPIO signal through the system bus to control the TBT chip to execute the corresponding TBT protocol function.

Compared with the prior art, the TBT chip integration system and method of the present invention can integrate the TBT chip on a standard PCIe external card, and set the signal parameter output of each signal pin of the micro control unit by updating the BIOS Various GPIO signals required by the TBT chip. This design enables the PCIe motherboard to support the TBT protocol function without connecting additional external wires.

Description of drawings

FIG. 1 is a schematic diagram of integrating a TBT chip on an external card in the prior art.

Fig. 2 is a schematic diagram of the operating environment of a preferred embodiment of the TBT chip integrated system of the present invention.

FIG. 3 is a flow chart of a flow chart of a preferred embodiment of the TBT chip integration method of the present invention.

Fig. 4 is a schematic diagram of a TBT protocol parameter table supporting the TBT protocol function in the present invention.

Description of main component symbols

PCIe add-on card 1

TBT chip 10

microcontroller unit 11

EEPROM 12

motherboard 2

TBT chip integrated system 20

Integrated modules 201

Setup Module 202

control module 203

PCIe slot 21

North and South Bridges 22

BIOS system 23

storage unit 24

Processor 25

SMbus bus 26

Detailed ways

Referring to FIG. 2 , it is a schematic diagram of an operating environment of a preferred embodiment of a TBT (short for Thunderbolt) chip integrated system 20 of the present invention. In this embodiment, the TBT chip integration system 20 is executed by a processor (CPU) 25, and the processor 25 is integrated in the motherboard 2, and the motherboard 2 is installed in an electronic device. The electronic device is a server, a personal computer, a mobile phone, or a PDA (Personal Digital Assistant, personal digital assistant) and the like. The motherboard 2 includes, but is not limited to, a PCIe slot (PCIe-slot) 21, a north-south bridge (PCH) 22, a Basic Input-Output System (BIOS system for short) 23, a storage unit 24 and a processor 25 . The PCIe slot 21 is connected to the North and South Bridges 22 through a system bus (SMbus) 26 , and the BIOS system 23 and the processor 25 communicate with each other through the SMbus 26 and the North and South Bridges 22 .

In this embodiment, the motherboard 2 is connected with a PCIe external card (PCI Express) 1 through a PCIe slot 21 , and the PCIe external card 1 includes a TBT chip 10 , a micro control unit (MCU) 11 and an EEPROM 12 . The PCIe external card 1 can enable the TBT chip 10 of the PCIe external card 1 to communicate with the SMbus bus 26 and the motherboard 2 through the SMbus bus 26 . The TBT chip 10 is a high-speed I/O port (Supper I/O Port) conforming to connector standards. The TBT chip 10 is characterized by extremely high data transmission rate and multiple functions, including high-efficiency peripherals equipped with PCIe functions and high-resolution display functions.

In the present embodiment, the described TBT chip integration system 20 updates each signal pin Pin parameter setting of the micro-control unit 11 through the BIOS system 23 to control the high-speed I/O function of the TBT chip 10, that is, the PCIe function and high-resolution Display function. The TBT chip integration system 20 includes an integration module 201 , a setting module 202 and a control module 203 . The function module referred to in the present invention refers to a series of program instruction segments that can be executed by the processor 25 and can complete fixed functions, which are stored in the storage unit 24 .

The integrated module 201 is used to integrate the TBT chip 10, the micro control unit 11 and the EEPROM 12 on the PCIe external card 1, and insert the PCIe external card 1 into the PCIe slot 21 of the motherboard 2, so that the TBT chip 10 and the micro The control unit 11 is connected to the SMBus 26 of the motherboard 2 .

The setting module 202 is used to define the TBT protocol parameter table supported by the TBT chip 10 by the MCU 11, and store the TBT protocol parameter table in the EEPROM12. Referring to FIG. 4 , it is a TBT protocol parameter table supporting the TBT protocol function. The TBT protocol parameter table stores signal parameters of each signal pin Pin of the MCU 11 in different working modes. For example, when the microcontroller unit 11 is in the normal mode (Normal mode with NHI), the signal parameters of the Sim-Pin3 pin, Sim-Pin6 pin and Sim-Pin7 pin are respectively set to logic "0", "1" and "1". When the MCU 11 is in the TBT test mode (TBTDebug), the signal parameters of the Sim-Pin3 pin, Sim-Pin6 pin and Sim-Pin7 pin are all set to logic “1”.

The setting module 202 is also used to set the GPIO signal parameters required by the MCU 11 to support the TBT chip 10 through the BIOS system 23 according to the defined TBT protocol parameter table. In this embodiment, the GPIO signal parameters include PCIe signal parameters for the TBT chip 10 to perform a high-efficiency peripheral configuration function and display signal parameters for the TBT chip 10 to perform a high-resolution display function.

The control module 203 is used to associate each signal pin Pin of the micro-control unit 11 with the TBT chip 10 according to the set GPIO signal parameters to support the TBT protocol function, and output the GPIO signal through the SMBus bus 26 to control the TBT chip 10 Execute the corresponding TBT protocol function. For example, when the SMBus bus 26 is connected with a network card, the micro-control unit 11 outputs a network transmission signal to control the TBT chip 10 to perform the PCIe function; when the SMBus bus 26 is connected to a display device (Monitor), the micro-control unit 11 outputs a display signal to control the TBT chip 10 Execute the high resolution display function.

Referring to FIG. 3 , it is a flow chart of a flow chart of a preferred embodiment of the TBT chip integration method of the present invention. In this embodiment, the method can integrate the TBT chip 10 on a standard PCIe external card 1, and set the signal parameters of each signal pin Pin of the micro control unit 11 by updating the BIOS system to provide the TBT chip 10. Various GPIO signals required. This design does not need to connect additional external wires (the external wire Cable-2 shown in FIG. 1 ), allowing the standard PCIe motherboard 2 to support the TBT protocol function by updating the BIOS system 23 .

Step S31 , the integration module 201 integrates the TBT chip 10 , the micro control unit 11 and the EEPROM 12 on the PCIe external card 1 .

Step S32 , the integrated module 201 inserts the PCIe external card into the PCIe slot 21 of the motherboard 2 , so that the TBT chip and the MCU are connected to the SMBus 26 of the motherboard 2 .

Step S33 , the setting module 202 defines the TBT protocol parameter table supported by the TBT chip 10 by the MCU 11 , and stores the TBT protocol parameter table in the EEPROM 12 . Referring to FIG. 4 , the TBT protocol parameter table includes signal parameters of each signal pin (Pin) of the MCU 11 in different working modes. For example, when the microcontroller unit 11 is in the normal mode (Normal mode with NHI), the signal parameters of the Sim-Pin3 pin, Sim-Pin6 pin and Sim-Pin7 pin are respectively set to logic "0", "1" and "1". When the MCU 11 is in the TBT test mode (TBT Debug), the signal parameters of the Sim-Pin3 pin, Sim-Pin6 pin and Sim-Pin7 pin are all set to logic “1”.

Step S34 , the setting module 202 sets the GPIO signal parameters required by the MCU 11 to support the TBT chip 10 through the BIOS system 23 according to the defined TBT protocol parameter table. The GPIO signal parameters include PCIe signal parameters for the TBT chip 10 to perform high-efficiency peripheral equipment functions and display signal parameters for the TBT chip 10 to perform high-resolution display.

Step S35 , the control module 203 associates each signal pin Pin of the MCU 11 with the TBT chip 10 according to the set GPIO signal parameters to support the TBT protocol function.

Step S36 , the control module 203 outputs a GPIO signal through the SMBus 26 to control the TBT chip 10 to execute corresponding TBT protocol functions. For example, when the SMBus bus 26 is connected with a network card, the micro-control unit 11 outputs a network transmission signal to control the TBT chip 10 to perform the PCIe function; when the SMBus bus 26 is connected to a display device (Monitor), the micro-control unit 11 outputs a display signal to control the TBT chip 10 Execute the high resolution display function.

The above embodiments are only used to illustrate the technical solutions of the present invention without limitation. Although the present invention has been described in detail with reference to the above preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced All should not deviate from the spirit and scope of the technical solution of the present invention.

Claims (10)

1. a TBT integrated chip system, be integrated in the processor of mainboard, described mainboard comprises that PCIe slot, system bus and BIOS system, this mainboard are connected with a PCIe add-on card by PCIe slot, it is characterized in that, described TBT integrated chip system comprises:

Integration module, for TBT chip, micro-control unit and EEPROM are integrated in to PCIe add-on card, and inserts PCIe adapter card in PCIe slot TBT chip and micro-control unit is connected on the system bus of mainboard;

Module is set, for defining micro-control unit, support the TBT protocol parameter table of TBT chip, this TBT protocol parameter table is stored in EEPROM, and by BIOS system, according to TBT protocol parameter table, sets micro-control unit and support the required GPIO signal parameter of TBT chip;

Control module, for according to the GPIO signal parameter of setting, each signal pin Pin of micro-control unit being carried out to the associated TBT protocol function of supporting with TBT chip, and by system bus, export GPIO signal controlling TBT chip and carry out corresponding TBT protocol function.

2. TBT integrated chip system as claimed in claim 1, is characterized in that, described TBT chip is a kind of High Speed I/O port that meets connector standards, and it has the characteristic of high data rate and function diversification.

3. TBT integrated chip system as claimed in claim 1, is characterized in that, described TBT protocol function comprises that high-effect periphery is equipped with PCIe function and high-resolution Presentation Function.

4. TBT integrated chip system as claimed in claim 1, is characterized in that, described GPIO signal parameter comprises that TBT chip carries out PCIe signal parameter and the TBT chip that high-effect periphery is equipped with PCIe function and carry out the display parameter that high-resolution shows.

5. TBT integrated chip system as claimed in claim 1, is characterized in that, described TBT protocol parameter table stores the signal parameter of each signal pin Pin of micro-control unit under different working modes.

6. a TBT integrated chip method, is applied in the processor of mainboard, and described mainboard comprises that PCIe slot, system bus and BIOS system, this mainboard are connected with a PCIe add-on card by PCIe slot, it is characterized in that, the method comprises:

TBT chip, micro-control unit and EEPROM are integrated in PCIe add-on card;

PCIe adapter card is inserted in PCIe slot TBT chip and micro-control unit are connected on the system bus of mainboard;

Definition micro-control unit is supported the TBT protocol parameter table of TBT chip, and this TBT protocol parameter table is stored in EEPROM;

By BIOS system, according to TBT protocol parameter table, set micro-control unit and support the required GPIO signal parameter of TBT chip;

According to the GPIO signal parameter of setting, each signal pin Pin of micro-control unit is carried out to the associated TBT protocol function of supporting with TBT chip;

By system bus, export GPIO signal controlling TBT chip and carry out corresponding TBT protocol function.

7. TBT integrated chip method as claimed in claim 6, is characterized in that, described TBT chip is a kind of High Speed I/O port that meets connector standards, and it has the characteristic of high data rate and function diversification.

8. TBT integrated chip method as claimed in claim 6, is characterized in that, described TBT protocol function comprises that high-effect periphery is equipped with PCIe function and high-resolution Presentation Function.

9. TBT integrated chip method as claimed in claim 6, is characterized in that, described GPIO signal parameter comprises that TBT chip carries out PCIe signal parameter and the TBT chip that high-effect periphery is equipped with PCIe function and carry out the display parameter that high-resolution shows.

10. TBT integrated chip method as claimed in claim 6, is characterized in that, described TBT protocol parameter table stores the signal parameter of each signal pin Pin of micro-control unit under different working modes.