CN103226537A - Programmable logic device for implementing hardware interface of mobile phone - Google Patents
Programmable logic device for implementing hardware interface of mobile phone Download PDFInfo
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- CN103226537A CN103226537A CN2013101699752A CN201310169975A CN103226537A CN 103226537 A CN103226537 A CN 103226537A CN 2013101699752 A CN2013101699752 A CN 2013101699752A CN 201310169975 A CN201310169975 A CN 201310169975A CN 103226537 A CN103226537 A CN 103226537A
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Abstract
The invention discloses a programmable logic device for implementing a hardware interface of a mobile phone and belongs to the technical field of hardware interfaces of mobile phones. The programmable logic device comprises a data transmitting component, a data receiving component, a clock frequency-dividing component, a sequential control component, an output buffering component and a registering component, wherein the data receiving component is connected with the sequential control component; the data transmitting component is connected with the sequential control component; the sequential control component is connected with the output buffering component; the clock frequency-dividing component is connected with the sequential control component; the registering component is connected with the data transmitting component and the data receiving component respectively; and the data transmitting component is also connected with the output buffering component. The programmable logic device adopting the technical scheme has the benefits that through the programmable logic device, a user can define the hardware interface of the mobile phone and expand the application range of the interface of the mobile phone, so that the development design of the intelligent mobile phone system is greatly facilitated; and the integrity of high-speed signals and the compatibility of port levels are greatly improved, and the driving capability is also greatly improved.
Description
Technical field
The present invention relates to mobile phone hardware interfacing field, relate in particular to a kind of programmable logic device (PLD) that realizes the mobile phone hardware interface.
Background technology
In the hardware design of smart mobile phone, often run into owing to the hardware platform interface resource-constrained, a lot of function development are restricted during design.In addition, also often run into the device conversion that peripheral components such as peripherals such as display screen, camera, touch-screen, sensor cause owing to reason or the product demand change of supplying, but these conversion are often because the new device interface definition during with hardware design is inconsistent, or lack compatibility during hardware design and cause causing the corresponding to cataclysm of whole hardware design, cabling, making sheet.
And smart mobile phone hardware design in the market mainly by the chip platform manufacturers design at chip internal, mobile phones design company is difficult to the product according to own product demand exploitation personalization, causes the machine-made situation of smart mobile phone in the market.Some company's autonomous innovation, but, abandons platform interface because not supporting, use the GPIO(General Purpose Input Output of arm processor in some design, general I/O) simulation external interface sequential, speed but is subjected to very big restriction, has also wasted a lot of system resources simultaneously.
Be illustrated in figure 1 as the processor interface framework that present smart mobile phone generally adopts, in the drawings, this processor connects UART(Universal Asynchronous Receiver/Transmitter respectively, universal asynchronous reception/transmission) interfacing equipment, I2C(Inter-Integrated Circuit, the internal integration circuit) interfacing equipment and SDIO(Secure Digital Input and Output Card, the secure digital input-output card) multiple interfaces equipment such as interfacing equipment, when the interface of certain product demand wherein is not in the interface range that chip provides, must use the GPIO simulation.But the GPIO simulation can't be satisfied the situation that peripheral apparatus is had relatively high expectations to transmission speed, and can cause the function of this interface correspondence to realize this moment.
Summary of the invention
According to the defective that exists in the prior art, a kind of technical scheme that realizes the programming device of mobile phone hardware interface now is provided, specifically comprise:
A kind of programmable logic device (PLD) that realizes the mobile phone hardware interface is applicable to the hardware interface expansion of smart mobile phone, and described smart mobile phone has a processor, and described programmable logic device (PLD) is positioned at the outside of described processor; Wherein, described programmable logic device (PLD) comprises data unit, Data Receiving parts, clock division parts, sequential control parts, output buffer unit and register component; The described sequential control parts of the two-way connection of described Data Receiving parts, the described sequential control parts of the two-way connection of described data unit, described sequential control parts connect described output buffer unit, described clock division parts connect described sequential control parts, and described register component connects described data unit and described Data Receiving parts respectively; Described data unit also connects described output buffer unit;
Described data unit is used for output data; Described Data Receiving parts are used to receive data; Described clock division parts are used to export clock signals of different frequencies; Described sequential control parts are used for controlling the time sequencing of described each program run of programmable logic device (PLD); Described output data is read and handled to described output buffer unit in advance for external unit; Described register component provides described programmable logic device (PLD) and deposits function;
Described programmable logic device (PLD) is connected with described processor with data line by address wire;
Described programmable logic device (PLD) is connected with the equipment interface of an input pin with the outside by an output pin; Described output pin is used for output data, and described input pin is used to receive data.
Preferably, this realizes the programmable logic device (PLD) of mobile phone hardware interface, and wherein, described programmable logic device (PLD) is the FPGA device.
Preferably, this realizes the programmable logic device (PLD) of mobile phone hardware interface, and wherein, described programmable logic device (PLD) is the CPLD device.
Preferably, this realizes the programmable logic device (PLD) of mobile phone hardware interface, wherein, be connected to the clock control line between described programmable logic device (PLD) and the described processor, described processor is by the described programmable logic device (PLD) tranmitting data register of described clock control alignment control signal.
Preferably, this realizes the programmable logic device (PLD) of mobile phone hardware interface, wherein, be connected to the control line that resets between described programmable logic device (PLD) and the described processor, described processor sends reseting controling signal by the described control line that resets to described programmable logic device (PLD).
Preferably, this realizes the programmable logic device (PLD) of mobile phone hardware interface, wherein, be connected to the route selection control line between described programmable logic device (PLD) and the described processor, described processor sends the route selection control signal by described route selection control line to described programmable logic device (PLD).
Preferably, this realizes the programmable logic device (PLD) of mobile phone hardware interface, wherein, be connected to read-write control line between described programmable logic device (PLD) and the described processor, described processor sends read-write control signal by described read-write control line to described programmable logic device (PLD).
Preferably, the programmable logic device (PLD) that this realizes the mobile phone hardware interface wherein, is connected to the acknowledge character control line between described programmable logic device (PLD) and the described processor; Described programmable logic device (PLD) is returned acknowledge character by described acknowledge character control line to described processor.
Preferably, this realizes the programmable logic device (PLD) of mobile phone hardware interface, and wherein, the described processor of described smart mobile phone is an arm processor.
The beneficial effect of technique scheme is: by programmable logic device (PLD), and the hardware interface that the user can user-defined mobile phone, the range of application of extended mobile phone interface has greatly made things convenient for the development and Design of intelligent mobile phone system.
In addition, use the interconnecting module of programmable logic device (PLD) as processor and peripheral hardware, to the integrality of high speed signal, the compatibility of port level and raising driving force etc. all has very big castering action.
Description of drawings
Fig. 1 is the structural representation that the mobile phone hardware interface connects external unit in the prior art;
Fig. 2 is a structure and performance of programmable logic device synoptic diagram in the embodiments of the invention;
Fig. 3 is the structural representation that the mobile phone hardware interface connects external unit in the embodiments of the invention.
Embodiment
The invention will be further described below in conjunction with the drawings and specific embodiments, but not as qualification of the present invention.
Programmable logic device (PLD), i.e. PLD(programmable logic device), PLD produces as a kind of universal integrated circuit, and his logic function is determined device programming according to the user.The integrated level of general PLD is very high, is enough to satisfy the needs of the general digital display circuit of design.So just can by the designer programme voluntarily and a digital display circuit " integrated " on a slice PLD, and needn't go for chip maker design and make special-purpose integrated circuit (IC) chip
As shown in Figure 2, the present invention adopts PLD as the interconnecting module between smart mobile phone processor and the peripheral apparatus, by hardware description language (VHDL, Very-High-Speed Integrated Circuit HardwareDescription Language), can realize timing Design easily at the hardware interface of each external unit.In one embodiment of the invention, be example to adopt above-mentioned PLD device switching handset processes device and exterior I 2C equipment, the structure of PLD device specifically comprises:
Data unit and Data Receiving parts, clock division parts, sequential control parts, output buffer unit and register component; Data Receiving parts and data unit two-way connection sequential control parts (be that data communication between data unit/Data Receiving parts and the sequential control parts is two-way, comprise data output and import) respectively wherein; The unidirectional connection of sequential control parts output buffer unit (be the sequential control assembly and data communication between the output buffer unit is unidirectional, data are exported buffer unit from unidirectional the outputing to of sequential control parts); The unidirectional connection sequential control of clock division parts parts; Register component connects data unit and Data Receiving parts respectively; The unidirectional connection output of data unit buffer unit.
In the said structure, data unit and Data Receiving parts provide the function of data output and input respectively, the clock division parts are sent to the sequential control parts respectively with clock signals of different frequencies, sequential control parts and data unit and Data Receiving parts carry out the data transmission interaction, and send different pieces of information to exporting buffer unit according to sequential control in different time sections; To the peripheral hardware output data time, the output buffer unit plays and reads the also effect of this output data of pre-service in advance; Register component is a registers group, is the register in the programmable logic device (PLD).
Above-mentioned programmable logic device (PLD) is connected the processor of smart mobile phone with data line (data) by address wire (addr), in an embodiment of the present invention, the processor of smart mobile phone is an arm processor, carries out exchanges data by data line between processor and the programmable logic device (PLD); Programmable logic device (PLD) is connected outside I2C interfacing equipment by an output pin (scl_pin) with an input pin (sda_pin), programmable logic device (PLD) is carried out exchanges data by the interfacing equipment of above-mentioned output pin and input pin and outside.
Between the processor of programmable logic device (PLD) and smart mobile phone, also comprise several control buss, comprising the clock control line (clk) that is used for to the programmable logic device (PLD) input clock signal, be used for the control line that resets (rst_1) to programmable logic device (PLD) input reset signal, be used for route selection control line (cs_1) to programmable logic device (PLD) input line selection signal, be used for read-write control line (rd_wr_1), and programmable logic device (PLD) is returned the acknowledge character symbol control line (ack_1) of reading really to processor to programmable logic device (PLD) input read-write.
Above-mentioned programmable logic device (PLD) can adopt FPGA(Field-Programmable Gate Array, field programmable gate array) device and CPLD(Complex Programmable Logic Device, CPLD) device makes.Wherein the FPGA device is gate array device, and is larger, and performance is more powerful, but the cost of chip is higher comparatively speaking; And the integrated level of CPLD device is lower, and the resources of chip performance is limited, but the manufacturing cost of chip is also relatively low, and the CPLD device can satisfy the form and function that conventional arm processor+programmable logic device (PLD) is formed.Therefore, the user can select different programmable logic device (PLD) as the interconnecting module between mobile phone and external unit according to the different purposes of smart mobile phone.
Programmable logic device structure among first embodiment of the present invention is applicable to the situation of the interfacing equipment that inserts other type fully.As shown in Figure 3, in other embodiments of the invention, adopt above-mentioned programmable logic device (PLD) as interconnecting module, smart mobile phone can insert other equally as UART equipment or SDIO equipment, the user is by downloading or other means, change the timing Design (finishing) of the chip internal of programmable logic device (PLD) by the sequential control parts by hardware description languages such as Verilog or VHDL, artificially each physical interface is carried out custom programming, thereby the access demand that meets each independent hardware interface has greatly made things convenient for the system development and the design of smart mobile phone.
The above only is preferred embodiment of the present invention; be not so restriction embodiments of the present invention and protection domain; to those skilled in the art; should recognize that being equal to that all utilizations instructions of the present invention and diagramatic content done replace and the resulting scheme of conspicuous variation, all should be included in protection scope of the present invention.
Claims (9)
1. a programmable logic device (PLD) that realizes the mobile phone hardware interface is applicable to the hardware interface expansion of smart mobile phone, and described smart mobile phone has a processor, and described programmable logic device (PLD) is positioned at the outside of described processor; It is characterized in that described programmable logic device (PLD) comprises data unit, Data Receiving parts, clock division parts, sequential control parts, output buffer unit and register component; The described sequential control parts of the two-way connection of described Data Receiving parts, the described sequential control parts of the two-way connection of described data unit, described sequential control parts connect described output buffer unit, described clock division parts connect described sequential control parts, and described register component connects described data unit and described Data Receiving parts respectively; Described data unit also connects described output buffer unit;
Described data unit is used for output data; Described Data Receiving parts are used to receive data; Described clock division parts are used to export clock signals of different frequencies; Described sequential control parts are used for controlling the time sequencing of described each program run of programmable logic device (PLD); Described output data is read and handled to described output buffer unit in advance for external unit; Described register component provides described programmable logic device (PLD) and deposits function;
Described programmable logic device (PLD) is connected with described processor with data line by address wire;
Described programmable logic device (PLD) is connected with the equipment interface of an input pin with the outside by an output pin; Described output pin is used for output data, and described input pin is used to receive data.
2. the programmable logic device (PLD) of realization mobile phone hardware interface as claimed in claim 1 is characterized in that, described programmable logic device (PLD) is the FPGA device.
3. the programmable logic device (PLD) of realization mobile phone hardware interface as claimed in claim 1 is characterized in that, described programmable logic device (PLD) is the CPLD device.
4. the programmable logic device (PLD) of realization mobile phone hardware interface as claimed in claim 1, it is characterized in that, be connected to the clock control line between described programmable logic device (PLD) and the described processor, described processor is by the described programmable logic device (PLD) tranmitting data register of described clock control alignment control signal.
5. the programmable logic device (PLD) of realization mobile phone hardware interface as claimed in claim 1, it is characterized in that, be connected to the control line that resets between described programmable logic device (PLD) and the described processor, described processor sends reseting controling signal by the described control line that resets to described programmable logic device (PLD).
6. the programmable logic device (PLD) of realization mobile phone hardware interface as claimed in claim 1, it is characterized in that, be connected to the route selection control line between described programmable logic device (PLD) and the described processor, described processor sends the route selection control signal by described route selection control line to described programmable logic device (PLD).
7. the programmable logic device (PLD) of realization mobile phone hardware interface as claimed in claim 1, it is characterized in that, be connected to read-write control line between described programmable logic device (PLD) and the described processor, described processor sends read-write control signal by described read-write control line to described programmable logic device (PLD).
8. the programmable logic device (PLD) of realization mobile phone hardware interface as claimed in claim 1 is characterized in that, is connected to the acknowledge character control line between described programmable logic device (PLD) and the described processor; Described programmable logic device (PLD) is returned acknowledge character by described acknowledge character control line to described processor.
9. the programmable logic device (PLD) of realization mobile phone hardware interface as claimed in claim 1 is characterized in that, the described processor of described smart mobile phone is an arm processor.
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Application publication date: 20130731 Assignee: Hangzhou Bolian Intelligent Technology Co.,Ltd. Assignor: Hangzhou Jiji Intellectual Property Operation Co.,Ltd. Contract record no.: X2021330000761 Denomination of invention: A programmable logic device for realizing mobile phone hardware interface Granted publication date: 20170919 License type: Common License Record date: 20211117 Application publication date: 20130731 Assignee: ZHEJIANG SUPCON TECHNOLOGY Co.,Ltd. Assignor: Hangzhou Jiji Intellectual Property Operation Co.,Ltd. Contract record no.: X2021330000762 Denomination of invention: A programmable logic device for realizing mobile phone hardware interface Granted publication date: 20170919 License type: Common License Record date: 20211117 |
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