CN104048592B - Method for detecting depth of etched groove through current change - Google Patents
Method for detecting depth of etched groove through current change Download PDFInfo
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- CN104048592B CN104048592B CN201410174912.0A CN201410174912A CN104048592B CN 104048592 B CN104048592 B CN 104048592B CN 201410174912 A CN201410174912 A CN 201410174912A CN 104048592 B CN104048592 B CN 104048592B
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Abstract
The invention discloses a method for detecting the depth of an etched groove through the current change. A special detection region is designed, so that the depth of the etched groove is reflected in real time. The detection region is prepared through the MEMS processing technique and signals are read through a current meter. According to the method, a function region and the detection region are well isolated electrically through an SOI silicon wafer and the MEMS processing technique and the function region is prevented from being damaged through detection current. Meanwhile, through pattern transfer, etched windows of the function region are copied in the detection region and it is guaranteed that the etching conditions of the detection region tend to be identical to those of the function region. Strict electricity modeling calculation is conducted on the deep groove structure of the detection region, the relation between the etching depth and current signals is acquired, and on the basis, the depth of the etched groove is monitored in real time through detection of the current meter.
Description
Technical field
The invention belongs to microelectromechanical systems (MEMS) processing technique field, by etching deep trouth at needs
Design detection region on the silicon chip of structure, utilizes Weak current gauge to measure the electric current passed through in detection structure big
Little, and as standard, determine the instant degree of depth of etching on silicon chip, reach the purpose of moment observation etching groove depth.
Background technology
Microelectromechanical systems (MEMS) is microelectric technique development and an important directions of application, and carves
Erosion technology is to realize material in MEMS processing technique to remove, and prepared by image transfer and core texture important
Means.Existing lithographic technique is broadly divided into wet etching and dry etching, owing to wet etching is difficult to obtain relatively
High depth-to-width ratio, therefore often apply when realizing deep groove structure is dry etching technology.And in dry etching skill
In art, the most most widely used is plasma reaction lithographic technique.The course of reaction of this type of lithographic technique is
Occur in special airtight etching cavity, due to plasma self property and intracavity electromagnetism, fluid environment
Complexity, is difficult to obtain an instant and accurate etch rate in course of reaction.Therefore, present stage is to quarter
The estimation of degree of corrosion relies primarily in conventional experience, and after substantially etch period completes, by etching silicon wafer
Take out from etching apparatus, be placed in basis of microscopic observation, differentiate whether etching completes with this.This method is behaviour
On work complex, and etching silicon wafer passes in and out etching apparatus repeatedly, it is not only possible to make etching silicon wafer be contaminated,
It is also possible to introduce polluter in thinking etching cavity.Be gradually reduced along with etching yardstick simultaneously, etching depth-to-width ratio by
Cumulative greatly, by ordinary optical microscope observe etching groove depth be difficult to the most all the more.And in addition,
MEMS etching process can use means at quarter toward contact, i.e. on the basis of previous experiences etch rate, will
Etch period adjusts to slightly larger than required time, solves, with this, the problem that etching depth is inadequate.And this kind of method
Etching the most substantially can be made to complete between result and design result and to produce deviation.
Summary of the invention
The purpose of the present invention is to propose to a kind of method utilizing curent change detection etch groove depth, special by design
Detection region realizes the method immediately reflecting etching depth, while not interrupting etching process, accomplishes to carve
Erosion deep conversion is the signal of telecommunication, and is immediately read by detecting instrument.
The method utilizing curent change detection etch groove depth of present invention design, comprises the steps:
1) select soi wafer as chip substrate；
2) lithographic definition etch the independent detection region with functional area electrical insulation on substrate；
3) be fabricated in above-mentioned detection region to detecting electrode；
4) on detecting electrode, protective layer is made；
5) the detection etch window of size and shape the same with functional area etching window is made by lithography in detection region
Mouthful；
6) functional area and detection region at substrate perform etching simultaneously, form detection etch groove；
7) ammeter is utilized to measure size of current between detecting electrode after having etched；
8) size of current measurement obtained and theoretical curve contrast, obtain the etching groove degree of depth.
Above-mentioned steps 2) and 6) in etching use MEMS etching technics, selected from reactive ion etching (RIE),
One in reaction ion deep etching (DRIE) and advanced silicon etching (ASE) technological means.
Above-mentioned steps 2) in, etching depth value is soi wafer front side silicon layer thickness, utilizes etching technics to cut through
Front side silicon layer.
Above-mentioned steps 2) in, if functional area exists multiple different size etching window, multiple independence will be etched
Detection region is (if there is the etching window of multiple formed objects, then and functional area of etching in functional area
The independent detection region of electrical insulation).
Above-mentioned steps 3) in, by photoetching electrode position, use low-pressure chemical vapor phase deposition (LPCVD) side
Legal system makees detecting electrode, and the material making detecting electrode is preferably polysilicon (Poly Si).
Above-mentioned steps 4) in, by detection region photoetching, defining and protect detecting electrode, shape with photoresist
Become detecting electrode protective layer.
Above-mentioned steps 4) in, after being additionally included in deposit detecting electrode protective layer, substrate is put in N2Atmosphere
Lower annealing.
Above-mentioned steps 5) in, the number of detection etch window is consistent with the number of functional area etching window, its
The position of middle detection etch window is between two detecting electrodes.
Above-mentioned steps 8) in, use location mode that electric current impact between etching groove is modeled by the etching groove degree of depth,
Obtain theoretical curve；Concrete modeling process is as follows: wherein in etching process each parameter as shown in Figures 2 and 3,
Wherein h is etching depth, and U is institute's making alive, and I is detection electric current, r1For sidewall direction resistance, r2For carving
Erosion groove is just to bottom resistance, r3For contact resistance, r is body silicon resistivity, and W is etching groove width, and L is detection
The zone length of etching window, R is overall resistance, and h0 is soi wafer upper layer of silicon layer thickness, and △ h is etching
Degree of depth h distribution step-length, if Rn is the n-th step solves resistance sizes, then region all-in resistance can be by following mistake
Journey programming realization solves:
R1=r1+r2+r1=2r × (WL)/△ h+r × (L △ h)/W
R2=2r1+1/(1/r2+1/R1)
R=Rn=2r3+1/(1/r2+1/RN-1)
Wherein n=(h0-h)/△ h, according to above modeling process, i.e. can get detection zone territory resistance and
Functional relation R (h) of etching depth h, it is clear that when △ h value is less, the method can be more accurate
Matching detection region resistance sizes.
Current curve is then obtained by I=U/R (h).
The present invention proposes a kind of method being realized by design special detection region and immediately reflecting etching groove depth,
Use MEMS processing technique preparation detection region, utilize galvanometer to realize signal-obtaining.The method is passed through
Soi wafer and MEMS processing technique is used to achieve functional area and detect the electric isolation that region is good,
Avoid detecting electric current functional device district is caused damage.Meanwhile, function is realized by figure transfer in detection region
The duplication of region etch window, it is ensured that etching condition and the functional area in detection region reach unanimity.Finally to inspection
Survey region deep groove structure and carry out strictly electricity Modeling Calculation, it is thus achieved that the pass between etching depth and current signal
System, and realize the immediately monitoring to etching groove depth with this by galvanometric detection.
Compared with prior art, the detection method that the present invention proposes has the advantage that
The most convenient and accurate, the signal of telecommunication can be obtained intuitively by galvanometer, it is possible to immediately determine
The etching groove degree of depth, it is not necessary to interrupt etching process；
2. it is beneficial to immediately monitoring, it is possible to more accurate assurance etching process, it is to avoid structure is caused by over etching
Infringement；
3. it is beneficial to the development trend of size reduction, owing to detection signal is the signal of telecommunication, not by depth-to-width ratio and size
Restriction to optical reflection, still can keep detection stable in small size and deep trouth situation；
Accompanying drawing explanation
Fig. 1 (a)～Fig. 1 (g) is the method technological process utilizing curent change detection etch groove depth in specific embodiment
Schematic diagram, wherein:
Fig. 1 (a) is the schematic diagram of SOI Substrate；
Fig. 1 (b) is that substrate DRIE etches isolation detection device groove figure；
Fig. 1 (c) is deposit detecting electrode schematic diagram；
Fig. 1 (d) is photoresist shield electrode schematic diagram；
Fig. 1 (e)～Fig. 1 (g) etches schematic diagram with functional area with window size for detection region；
Specifically there are 1 SOI Substrate, 2 functional areas, 3 detection regions, 4 polysilicon electrodes, 5 inspections
Survey electrode protecting layer, 6 detection etch windows, 7 detection etch deep trouths.
Fig. 2 (a) is detection region schematic cross-section.
Fig. 2 (b) is detection region schematic top plan view.
Fig. 3 is detection region electric resistive distribution schematic diagram.
Detailed description of the invention
Below by specific embodiment, and coordinate accompanying drawing, the present invention is described in detail.
Embodiment 1:
The method utilizing curent change detection etch groove depth of the present embodiment implements technique such as Fig. 1 (a)～figure
Shown in 1 (g), it is described as follows:
1, standby sheet: SOI Substrate 1 is as the substrate of chip, as shown in Fig. 1 (a).
2, on substrate, use MEMS technology photoetching and define detection region 3, utilizing etching technics to isolate
Detection region 3 and functional area 2, including:As shown in Fig. 1 (b).
Etching depth value is soi wafer front side silicon layer thickness, utilizes etching technics to cut through front side silicon layer, it is achieved inspection
Survey region 3 and the electrical insulation of functional area 2.
It is to say, by oxygen buried layer isolating device functional area and detection region in the present invention, isolating
Etching in, etching depth must be that oxygen buried layer is exposed, and the groove in Fig. 1 (b) is isolation channel, and the degree of depth must reach
Burying oxygen, the etching depth of detection etch deep trouth 7 below can be arbitrary.
3, utilize LPCVD deposition techniques polysilicon, detecting region 3 photoetching and etching paired detection electricity
Pole polysilicon electrode 4, including: LPCVD Si 30 μm, DRIE Si 30 μm；As shown in Fig. 1 (c).
4, in detection region 3 photoetching, define and protect detecting electrode with photoresist, form detecting electrode protection
Layer 5；As shown in Fig. 1 (d).
5, substrate is put in N2Anneal under atmosphere 1min.
At N2Carrying out annealing under atmosphere can make polysilicon electrode finer and close, reduces electrode contact and introduces
Error；
6, between the paired electrode in detection region 3, detection etch window of a size with functional area 2 is made by lithography
Mouth 6, as shown in Fig. 1 (e), functional area 2 and detection region 3 at substrate carry out relevant etching simultaneously subsequently；
Form detection etch deep trouth 7, as shown in Fig. 1 (f).
Etch period, pressure, the process conditions such as voltage are determined by functional area 2 processing technology.
7, remove photoresist, as shown in Fig. 1 (g).Utilize ammeter to measure size of current between detecting electrode, and with modeling
Get parms and contrast, obtain etching groove depth information.
Concrete modeling process is as follows: wherein in etching process each parameter as shown in Figures 2 and 3, wherein h
For etching depth, U is institute's making alive, and I is detection electric current, r1For sidewall direction resistance, r2For etching groove just
To bottom resistance, r3For contact resistance, r is body silicon resistivity, and W is etching groove width, and L is detection etch window
The zone length of mouth, R is overall resistance, and h0 is soi wafer upper layer of silicon layer thickness, and △ h is etching depth h
Distribution step-length, if Rn is the n-th step solves resistance sizes, then region all-in resistance can be programmed by procedure below
Realization solves:
R1=r1+r2+r1=2r × (WL)/△ h+r × (L △ h)/W
R2=2r1+1/(1/r2+1/R1)
R=Rn=2r3+1/(1/r2+1/RN-1)
Wherein n=(h0-h)/△ h, according to above modeling process, i.e. can get detection zone territory resistance and
Functional relation R (h) of etching depth h, it is clear that when △ h value is less, the method can be more accurate
Matching detection region resistance sizes.
Current curve is then obtained by I=U/R (h).
Referring in particular to model above, due to for detect under different process conditions the body silicon resistivity in region and
Region length and width all have large change, are programmed just can facilitating by matlab in specific implementation process
To numerical curve.
Claims (10)
1. the method utilizing curent change detection etch groove depth, comprises the steps:
1) select soi wafer as chip substrate；
2) lithographic definition etch the independent detection region with functional area electrical insulation on substrate；
3) be fabricated in above-mentioned detection region to detecting electrode；
4) on detecting electrode, protective layer is made；
5) the detection etch window of size and shape the same with functional area etching window is made by lithography in detection region；
6) functional area and detection region at substrate perform etching simultaneously, form detection etch groove；
7) ammeter is utilized to measure size of current between detecting electrode after having etched；
8) size of current measurement obtained and theoretical curve contrast, obtain the etching groove degree of depth.
The method utilizing curent change detection etch groove depth the most as claimed in claim 1, it is characterised in that step 2) and 6) in
Etching use MEMS etching technics, in reactive ion etching, reaction ion deep etching and advanced silicon etching technological means
One.
The method utilizing curent change detection etch groove depth the most as claimed in claim 1, it is characterised in that step 2) in, etching
Depth value is soi wafer front side silicon layer thickness, utilizes etching technics to cut through front side silicon layer.
The method utilizing curent change detection etch groove depth the most as claimed in claim 1, it is characterised in that step 2) in, if merit
Multiple different size etching window can be there is in region, then etch multiple independent detection region.
The method utilizing curent change detection etch groove depth the most as claimed in claim 1, it is characterised in that step 3) in, pass through
Photoetching electrode position, uses low-pressure chemical vapor phase deposition method to make detecting electrode.
The method utilizing curent change detection etch groove depth the most as claimed in claim 1, it is characterised in that step 3) in, make
The material of detecting electrode is polysilicon.
The method utilizing curent change detection etch groove depth the most as claimed in claim 1, it is characterised in that step 4) in, pass through
In detection region photoetching, define and protect detecting electrode with photoresist, form detecting electrode protective layer.
The method utilizing curent change detection etch groove depth the most as claimed in claim 1, it is characterised in that step 4) in, also wrap
Include after deposit detecting electrode protective layer, substrate is put in N2Anneal under atmosphere.
The method utilizing curent change detection etch groove depth the most as claimed in claim 1, it is characterised in that step 5) in, described
The number of detection etch window is consistent with the number of functional area etching window, and wherein the position of detection region etching window is positioned at two
Between detecting electrode.
10. the method utilizing curent change detection etch groove depth as described in as arbitrary in claim 19, it is characterised in that step 8)
In, use location mode that electric current impact between etching groove is modeled by the etching groove degree of depth, obtain theoretical curve；Concrete modeling
Process is as follows: wherein h is etching depth, and U is institute's making alive, and I is detection electric current, r1For sidewall direction resistance, r2For carving
Erosion groove is just to bottom resistance, r3For contact resistance, r is body silicon resistivity, and W is etching groove width, and L is detection etch window
Zone length, R is overall resistance, and h0 is soi wafer upper layer of silicon layer thickness, and △ h is that etching depth h is distributed step-length, if Rn
Be that the n-th step solves resistance sizes, then region all-in resistance is solved by procedure below programming realization:
R1=r1+r2+r1=2r × (WL)/△ h+r × (L △ h)/W
R2=2r1+1/(1/r2+1/R1)
......
R=Rn=2r3+1/(1/r2+1/RN-1)
Wherein n=(h0-h)/△ h, according to above modeling process, i.e. can get detection zone territory resistance and etching depth h
Functional relation R (h), it is clear that when △ h value is less, the method can more accurate matching detection region resistance sizes；
Current curve is then obtained by I=U/R (h).
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| CN106477517B (en) * | 2015-09-02 | 2018-08-28 | 北京大学 | A method of characterizing silicon chip surface roughness using current value |
| CN110148568A (en) * | 2019-05-07 | 2019-08-20 | 深圳市华星光电技术有限公司 | The metal etch endpoint determination method of thin film transistor base plate metal layer |
| CN113119329B (en) * | 2019-12-30 | 2023-04-25 | 苏州阿特斯阳光电力科技有限公司 | Cutting method and cutting device for crystalline silicon |
| CN111430255B (en) * | 2020-03-31 | 2021-04-02 | 无锡物联网创新中心有限公司 | Method for detecting etching depth |
| CN113611626B (en) * | 2021-08-04 | 2024-02-27 | 上海信及光子集成技术有限公司 | Method for detecting etching depth of silicon groove on line |
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| US20030129843A1 (en) * | 2001-10-05 | 2003-07-10 | Yongming Cai | Planarizing recess etch |
| CN103165486B (en) * | 2011-12-08 | 2015-09-02 | 中芯国际集成电路制造(上海)有限公司 | The detection method of silicon through hole detection architecture and correspondence |
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