CN104038089A - Device for improving output voltage of Z-source three-level neutral point clamped inverter and method - Google Patents

Abstract

The invention discloses a device for improving output voltage of a Z-source three-level neutral point clamped inverter and a method. The device comprises a first direct current power supply and a second direct current power supply, wherein the positive electrode of the first direct current power supply is electrically connected with the positive electrode of a first diode; the negative electrode of the first diode and the negative electrode of the first direct current power supply are electrically connected with a first Z-source network with a first switch inductor and a second switch inductor; the positive electrode of the second direct current power supply is electrically connected with the positive electrode of a second diode; the negative electrode of the second diode and the negative electrode of the second direct current power supply are electrically connected with a second Z-source network with a third switch inductor and a fourth switch inductor; the first Z-source network and the second Z-source network are both electrically connected with the three-level neutral point clamped (NPC) inversion circuit; and the three-level neutral point clamped (NPC) inversion circuit is electrically connected with the A phase, the B phase and the C phase of three-phase electricity. The method can overcome the defect that no reliable and effective method in the prior art can improve the output voltage of the Z-source three-level inverter.

Description

Improve the device and method of Z source three level neutral-point-clamped formula inverter output voltages

Technical field

The invention belongs to a clamping type inverter technology field, be specifically related to a kind of Z of raising source three level neutral-point-clamped formula inverters output voltage device and method.

Background technology

Multi-electrical level inverter has advantages of that withstand voltage level is high, transfer power is large, switching loss is little, output harmonic wave content is low, but multi-electrical level inverter is generally voltage-dropping type inverter, for the voltage of raising system output need to increase prime loop, cause system loss to increase and control difficulty increase.Z source neutral-point-clamped inverter is applied to characteristic in three-level inverter, can effectively improve the output voltage of three-level inverter.The scope of Z source network can reach infinitely great in theory, but due to straight-through duty ratio D and the modulation degree M existence relation of restriction mutually, when system requirements very Gao Shihui causes modulation degree M too small, affects the stability of system.But also there is no the method for the output voltage of reliable and effective raising Z source three-level inverter now.

Summary of the invention

Object of the present invention provides the device and method of a kind of Z of raising source three level neutral-point-clamped formula inverter output voltages, comprise the first DC power supply and the second DC power supply, the positive pole of the first DC power supply is electrically connected with the positive pole of the first diode, the negative pole of the first described diode and the negative pole of the first DC power supply are with being electrically connected with a Z source network of the first switched inductors and second switch inductance, the positive pole of the second DC power supply is electrically connected with the positive pole of the second diode, the negative pole of the second described diode and the negative pole of the second DC power supply are with being electrically connected with the 2nd Z source network of the 3rd switched inductors and the 4th switched inductors, the one Z source network and the 2nd Z source network are all electrically connected with three level NPC inverter circuits, three level NPC inverter circuits are with the A phase of three-phase electricity, B phase is electrically connected mutually with C.Such structure has been avoided the defect of the method for the output voltage that also there is no reliable and effective raising Z source three-level inverter in prior art now in conjunction with its method.

In order to overcome deficiency of the prior art, the invention provides the solution of the method for the output voltage of a kind of Z of raising source three level neutral-point-clamped formula inverters, specific as follows:

A device that improves the output voltage of Z source three level neutral-point-clamped formula inverters, comprises the first DC power supply U _dc1with the second DC power supply U _dc2, the first DC power supply U _dc1positive pole with the first diode D _inpositive pole be electrically connected, the first described diode D _innegative pole and the first DC power supply U _dc1negative pole with being electrically connected with a Z source network of the first switched inductors and second switch inductance, the second DC power supply U _dc2positive pole with the second diode D ^, _inpositive pole be electrically connected, the second described diode D ^, _innegative pole and the second DC power supply U _dc2negative pole with being electrically connected with the 2nd Z source network of the 3rd switched inductors and the 4th switched inductors, the one Z source network and the 2nd Z source network are all electrically connected with three level NPC inverter circuits, and three level NPC inverter circuits are electrically connected with A phase load, B phase load and C phase load.

A described Z source network comprises the first capacitor C ₁with the second capacitor C ₂, the first described capacitor C ₁one extremely with the first inductance L ₁a utmost point, the first diode D _innegative pole and the 3rd diode D ₁positive pole be electrically connected, the first inductance L ₁another extremely with the 4th diode D ₂anodal and the 5th diode D ₃positive pole be electrically connected, the 4th diode D ₂negative pole with the 3rd diode D ₁negative pole and the second inductance L ₂a utmost point be electrically connected, the 5th described diode D ₃negative pole with the second capacitor C ₂a utmost point and the second inductance L ₂another utmost point be electrically connected, the first inductance L ₁, the second inductance L ₂, the 3rd diode D ₁, the 4th diode D ₂and the 5th diode D ₃form the first switched inductors; The first described capacitor C ₁another extremely with the 3rd inductance L ₃a utmost point and the 6th diode D ₄positive pole be electrically connected, the 6th described diode D ₄negative pole with the 7th diode D ₅negative pole and the 4th inductance L ₄a utmost point be electrically connected, the 7th described diode D ₅positive pole with the 8th diode D ₆anodal and the 3rd inductance L ₃another utmost point be electrically connected, the 8th described diode D ₆negative pole with the second capacitor C ₂another utmost point, the first DC power supply U _dc1negative pole and the 4th inductance L ₄another utmost point be electrically connected, the 3rd inductance L ₃, the 4th inductance L ₄, the 6th diode D ₄, the 7th diode D ₅and the 8th diode D ₆form second switch inductance.

The 2nd described Z source network comprise the 3rd capacitor C ' ₁with the 4th capacitor C ' ₂, the 3rd described electric capacity

C' ₁one extremely with the 5th inductance L ' ₁a utmost point, the second diode D' _innegative pole and the 9th diode D' ₁positive pole be electrically connected, the 5th inductance L ' ₁another extremely with the tenth diode D' ₂anodal and the 11 diode D' ₃positive pole be electrically connected, the tenth diode D' ₂negative pole with the 9th diode D' ₁negative pole and the 6th inductance L ' ₂a utmost point be electrically connected, the 11 described diode D' ₃negative pole with the 4th capacitor C ' ₂a utmost point and the 6th inductance L ' ₂another utmost point be electrically connected, the 5th inductance L ' ₁, the 6th inductance L ' ₂, the 9th diode D' ₁, the tenth diode D' ₂and the 11 diode D' ₃form the 3rd switched inductors; Described the 3rd capacitor C ' ₁another extremely with the 7th inductance L ' ₃a utmost point and the 12 diode D' ₄positive pole be electrically connected, the 12 described diode D' ₄negative pole with the 13 diode D' ₅negative pole and the 8th inductance L ' ₄a utmost point be electrically connected, the 13 described diode D' ₅positive pole with the 14 diode

D' ₆anodal and the 7th inductance L ' ₃another utmost point be electrically connected, the 14 described diode D' ₆negative pole with the 4th capacitor C ' ₂another utmost point, the second DC power supply U _dc2negative pole and the 8th inductance L ' ₄another utmost point be electrically connected, the 7th inductance L ' ₃, the 8th inductance L ' ₄, the 12 diode D' ₄, the 13 diode D' ₅and the 14 diode D' ₆form the 4th switched inductors.

Three described level NPC inverter circuits comprise the one or three level NPC inverse variation circuit, the two or three level NPC inverse variation circuit and the three or three level NPC inverse variation circuit parallel with one another, and wherein the one or three level NPC inverse variation circuit comprises the first switch transistor T _a1, the first switch transistor T _a1collector electrode be electrically connected with the negative pole of the 17 diode 17, the first switch transistor T _a1emitter with negative pole, the negative pole of the 18 diode 18, the second switch pipe T of the 15 diode 15 _a2collector electrode and the positive pole of the 17 diode 17 be electrically connected, second switch pipe T _a2emitter with positive pole, the 3rd switch transistor T of the 18 diode 18 _a3collector electrode, negative pole and the A phase load of the 19 diode 19 be electrically connected, the 3rd switch transistor T _a3emitter with positive pole, the 4th switch transistor T of the 19 diode 19 _a4collector electrode, the 20 negative pole of diode 20 and the positive pole of the 16 diode 16 be electrically connected, the 4th switch transistor T _a4emitter be electrically connected with the positive pole of the 20 diode 20; The two or three level NPC inverse variation circuit comprises the 5th switch transistor T _b1, the 5th switch transistor T _b1collector electrode be electrically connected with the negative pole of the 23 diode 23, the 5th switch transistor T _b1emitter with negative pole, the negative pole of the 24 diode 24, the 6th switch transistor T of the 21 diode 21 _b2collector electrode and the positive pole of the 23 diode 23 be electrically connected, the 6th switch transistor T _b2emitter with positive pole, the 7th switch transistor T of the 24 diode 24 _b3collector electrode, negative pole and the B phase load of the 25 diode 19 be electrically connected, the 7th switch transistor T _b3emitter with positive pole, the 8th switch transistor T of the 25 diode 25 _b4collector electrode, the 26 negative pole of diode 26 and the positive pole of the 22 diode 22 be electrically connected, the 8th switch transistor T _b4emitter be electrically connected with the positive pole of the 26 diode 26; The three or three level NPC inverse variation circuit comprises the 9th switch transistor T _c1, the 9th switch transistor T _c1collector electrode be electrically connected with the negative pole of the 29 diode 29, the 9th switch transistor T _c1emitter with negative pole, the negative pole of the 30 diode 30, the tenth switch transistor T of the 27 diode 27 _c2collector electrode and the positive pole of the 29 diode 29 be electrically connected, the tenth switch transistor T _c2emitter with positive pole, the 11 switch transistor T of the 30 diode 30 _c3collector electrode, negative pole and the C phase load of the 31 diode 31 be electrically connected, the 11 switch transistor T _c3emitter close pipe T with the positive pole of the 31 diode 31, twelvemo _c4collector electrode, the 32 negative pole of diode 32 and the positive pole of the 28 diode 28 be electrically connected, twelvemo close pipe T _c4emitter be electrically connected with the positive pole of the 32 diode 32; The first described switch transistor T _a1collector electrode, the 5th switch transistor T _b1collector electrode and the 9th switch transistor T _c1collector electrode with the second described capacitor C ₂a utmost point be electrically connected; The 4th described switch transistor T _a4collector electrode, the 8th switch transistor T _b4collector electrode and twelvemo close pipe T _c4collector electrode with the 3rd described capacitor C ' ₁a utmost point be electrically connected; The 11 described diode D' ₃negative pole and the 6th diode D ₄positive pole be electrically connected with the negative pole of the positive pole of the 15 diode 15, the 16 diode 16, the positive pole of the 21 diode 21, the negative pole of the 22 diode 22, the negative pole anodal and the 28 diode 28 of the 27 diode 27.

The first described inductance L ₁inductance value, the second inductance L ₂inductance value, the 3rd inductance L ₃inductance value, the 4th inductance L ₄inductance value, the 5th inductance L ' ₁inductance value, the 6th inductance L ' ₂inductance value, the 7th inductance L ' ₃inductance value and the 8th inductance L ' ₄inductance value be L, L is greater than zero real number, the first described capacitor C ₁capacitance, the second capacitor C ₂capacitance, the 3rd capacitor C ' ₁capacitance and the 4th capacitor C ' ₂capacitance be C, C is greater than zero real number, the first described DC power supply U _dc1magnitude of voltage and the second DC power supply U _dc2magnitude of voltage be U _dc, U _dcfor real number, so just can meet the condition of following formula group (1):

$\left\{\begin{array}{c}{U}_{L1}=U_{L2}=U_{L3}=U_{L4}=U_L\\ U_{L1}^{\′}=U_{L2}^{\′}=U_{L3}^{\′}=U_{L4}^{\′}=U_L^{\′}\\ U_{C1}=U_{C2}=U_C\\ U_{C1}^{\′}=U_{C2}^{\′}=U_C^{\′}\end{array}\right.---\left(1\right)$

Wherein U _l1it is the first inductance L ₁inductive drop value, U _l2it is the second inductance L ₂inductive drop value, U _l3it is the 3rd inductance L ₃inductive drop value, U _l4it is the 4th inductance L ₄inductive drop value, U' _l1be the 5th inductance L ' ₁inductive drop value, U' _l2be the 6th inductance L ' ₂inductive drop value, U' _l3be the 7th inductance L ' ₃inductive drop value, U' _l4be the 8th inductance L ' ₄inductive drop value, U _c1it is the first capacitor C ₁capacitance voltage value, U _c2it is the second capacitor C ₂capacitance voltage value, U' _c1be the 3rd capacitor C ' ₁capacitance voltage value, U' _c2be the 4th capacitor C ' ₂capacitance voltage value, U _l1, U _l2, U _l3and U _l4equate and be U _l, U' _l1, U' _l2, U' _l3and U' _l4equate and be U' _l, U _c1and U _c2equate and be U _c, U' _c1and U' _c2equate and be U' _c, U _l, U' _l, U _cand U' _cbe real number value.

The method of the raising output voltage of the device of the output voltage of described raising Z source three level neutral-point-clamped formula inverters, as follows:

When at the first diode D _inwith the second diode D ^, _inconducting the first DC power supply U respectively _dc1with the second DC power supply U _dc2condition under, in a switch periods, in the first switch transistor T _a1with second switch pipe T _a2for conducting state the 3rd switch transistor T _a3with the 4th switch transistor T _a4under off state, for the output voltage of A phase load just in non-straight-through+1 state; At second switch pipe T _a2with the 3rd switch transistor T _a3for conducting state the first switch transistor T _a1with the 4th switch transistor T _a4under off state, for the output voltage of A phase load just in non-straight-through 0 state; In the first switch transistor T _a1with second switch pipe T _a2for off state the 3rd switch transistor T _a3with the 4th switch transistor T _a4under conducting state, for the output voltage of A phase load just in non-straight-through-1 state;

When at the first diode D _inwith the second diode D ^, _inconducting the first DC power supply U respectively _dc1with the second DC power supply U _dc2condition under, in a switch periods, in the 5th switch transistor T _b1with the 6th switch transistor T _b2for conducting state the 7th switch transistor T _b3with the 8th switch transistor T _b4under off state, for the output voltage of B phase load just in non-straight-through+1 state; In the 6th switch transistor T _b2with the 7th switch transistor T _b3for conducting state the 5th switch transistor T _b1with the 8th switch transistor T _b4under off state, for the output voltage of B phase load just in non-straight-through 0 state; In the 5th switch transistor T _b1with the 6th switch transistor T _b2for off state the 7th switch transistor T _b3with the 8th switch transistor T _b4under conducting state, for the output voltage of B phase load just in non-straight-through-1 state;

When at the first diode D _inwith the second diode D ^, _inconducting the first DC power supply U respectively _dc1with the second DC power supply U _dc2condition under, in a switch periods, in the 9th switch transistor T _c1with the tenth switch transistor T _c2for conducting state the 11 switch transistor T _c3close pipe T with twelvemo _c4under off state, for the output voltage of C phase load just in non-straight-through+1 state; In the tenth switch transistor T _c2with the 11 switch transistor T _c3for conducting state the 9th switch transistor T _c1close pipe T with twelvemo _c4under off state, for the output voltage of C phase load just in non-straight-through 0 state; In the 9th switch transistor T _c1with the tenth switch transistor T _c2for off state the 11 switch transistor T _c3close pipe T with twelvemo _c4under conducting state, for the output voltage of C phase load just in non-straight-through-1 state;

Work as at the first diode D like this _inwith the second diode D ^, _inconducting the first DC power supply U respectively _dc1with the second DC power supply U _dc2condition under, in a switch periods, also just met as the condition in formula (2) group:

$\left\{\begin{array}{c}{2U}_L=U_{\mathrm{dc}}-U_C\\ U_i/2=U_C-{2U}_L\\ U_{+N}=U_i/2,U_N=0,U_{-N}=-U_i/2\end{array}\right.---\left(2\right)$

Wherein U _lrepresent equal U _l1, U _l2, U _l3and U _l4value, U _crepresent equal U _c1and U _c2value, U _land U _cbe real number value, U _l1it is the first inductance L ₁inductive drop value, U _l2it is the second inductance L ₂inductive drop value, U _l3it is the 3rd inductance L ₃inductive drop value, U _l4it is the 4th inductance L ₄inductive drop value, U _c1it is the first capacitor C ₁capacitance voltage value, U _c2it is the second capacitor C ₂capacitance voltage value, U _ifor the direct-current chain crest voltage value of the Z source three level neutral-point-clamped formula inverters in the device of the output voltage of described raising Z source three level neutral-point-clamped formula inverters, U _{+ N}for working as at the first diode D _inwith the second diode D ^, _inconducting the first DC power supply U respectively _dc1with the second DC power supply U _dc2condition under in non-straight-through+1 state for the output voltage values of A phase load, in non-straight-through+1 state for the output voltage values of B phase load or the output voltage values for C phase load in non-straight-through+1 state, U _nfor working as at the first diode D _inwith the second diode D ^, _inconducting the first DC power supply U respectively _dc1with the second DC power supply U _dc2condition under in non-straight-through 0 state for the output voltage values of A phase load, in non-straight-through 0 state for the output voltage values of B phase load or the output voltage values for C phase load in non-straight-through 0 state, U _-Nfor working as at the first diode D _inwith the second diode D ^, _inconducting the first DC power supply U respectively _dc1with the second DC power supply U _dc2condition under in non-straight-through-1 state for the output voltage values of A phase load, in non-straight-through-1 state for the output voltage values of B phase load or the output voltage values for C phase load in non-straight-through-1 state;

When at the first diode D _inturn-off and the second diode D ^, _inconducting the second DC power supply U _dc2condition under, in a switch periods, the first switch transistor T _a1, second switch pipe T _a2with the 3rd switch transistor T _a3for conducting state the 4th switch transistor T _a4under off state, for the output voltage of A phase load just in upper pass-through state;

When at the first diode D _inturn-off and the second diode D ^, _inconducting the second DC power supply U _dc2condition under, in a switch periods, the 5th switch transistor T _b1, the 6th switch transistor T _b2with the 7th switch transistor T _b3for conducting state the 8th switch transistor T _b4under off state, for the output voltage of B phase load just in upper pass-through state;

When at the first diode D _inturn-off and the second diode D ^, _inconducting the second DC power supply U _dc2condition under, in a switch periods, the 9th switch transistor T _c1, the tenth switch transistor T _c2with the 11 switch transistor T _c3for conducting state twelvemo is closed pipe T _c4under off state, for the output voltage of C phase load just in upper pass-through state;

Work as at the first diode D like this _inturn-off and the second diode D ^, _inconducting the second DC power supply U _dc2condition under, in a switch periods, also just met as the condition in formula (3) group:

$\left\{\begin{array}{c}{U}_{C1}=U_{C2}=U_C\\ U_{L1}=U_{L2}=U_{L3}=U_{L4}=U_L\\ U_C=U_L\\ U_i=U_C-{2U}_L\\ U_u=-U_i\end{array}\right.---\left(3\right)$

Wherein U _lrepresent equal U _l1, U _l2, U _l3and U _l4value, U _crepresent equal U _c1and U _c2value, U _land U _cbe real number value, U _l1it is the first inductance L ₁inductive drop value, U _l2it is the second inductance L ₂inductive drop value, U _l3it is the 3rd inductance L ₃inductive drop value, U _l4it is the 4th inductance L ₄inductive drop value, U _c1it is the first capacitor C ₁capacitance voltage value, U _c2it is the second capacitor C ₂capacitance voltage value, U _ifor the direct-current chain crest voltage value of the Z source three level neutral-point-clamped formula inverters in the device of the output voltage of described raising Z source three level neutral-point-clamped formula inverters, U _ufor working as at the first diode D _inturn-off and the second diode D ^, _inconducting the second DC power supply U _dc2condition under in upper pass-through state for the output voltage values of A phase load, in upper pass-through state for the output voltage values of B phase load or the output voltage values for C phase load in upper pass-through state;

When at the second diode D ^, _inturn-off and the first diode D _inconducting the first DC power supply U _dc2condition under, in a switch periods, the first switch transistor T _a1for off state second switch pipe T _a2, the 3rd switch transistor T _a3with the 4th switch transistor T _a4under conducting state, for the output voltage of A phase load just in lower pass-through state;

When at the second diode D ^, _inturn-off and the first diode D _inconducting the first DC power supply U _dc2condition under, in a switch periods, the 5th switch transistor T _b1for off state the 6th switch transistor T _b2, the 7th switch transistor T _b3with the 8th switch transistor T _b4under conducting state, for the output voltage of B phase load just in lower pass-through state;

When at the second diode D ^, _inturn-off and the first diode D _inconducting the first DC power supply U _dc2condition under, in a switch periods, the 9th switch transistor T _c1for off state the tenth switch transistor T _c2, the 11 switch transistor T _c3close pipe T with twelvemo _c4under conducting state, for the output voltage of C phase load just in lower pass-through state;

Such the second diode D ^, _inturn-off and the first diode D _inconducting the first DC power supply U _dc2condition under, in a switch periods, also just met as the condition in formula (4) group:

$\left\{\begin{array}{c}{U}_{C1}^{\′}=U_{C2}^{\′}=U_C^{\′}\\ U_{L1}^{\′}=U_{L2}^{\′}=U_{L3}^{\′}=U_{L4}^{\′}=U_L^{\′}\\ U_C=U_L\\ U_i=U_C-{2U}_L\\ U_d=U_i\end{array}\right.---\left(4\right)$

Wherein U' _l1be the 5th inductance L ' ₁inductive drop value, U' _l2be the 6th inductance L ' ₂inductive drop value, U' _l3be the 7th inductance L ' ₃inductive drop value, U' _l4be the 8th inductance L ' ₄inductive drop value, U' _c1be the 3rd capacitor C ' ₁capacitance voltage value, U' _c2be the 4th capacitor C ' ₂capacitance voltage value, U' _l1, U' _l2, U' _l3and U' _l4equate and be U' _l, U' _c1and U' _c2equate and be U' _c, U _l, U' _l, U _cand U' _cbe real number value, U _ifor the direct-current chain crest voltage value of the Z source three level neutral-point-clamped formula inverters in the device of the output voltage of described raising Z source three level neutral-point-clamped formula inverters, U _dfor working as at the second diode D ^, _inturn-off and the first diode D _inconducting the second DC power supply U _dc2condition under in lower pass-through state for the output voltage values of A phase load, in lower pass-through state for the output voltage values of B phase load or the output voltage values for C phase load in lower pass-through state;

In addition in a switch periods, according to inductance weber equilibrium relation system meet formula (5):

$U_{C}D+\frac{1}{2}(U_{\mathrm{dc}}-U_C)(1-D)=0---\left(5\right)$

Can release formula (6) by formula (5)

$U_C=\frac{1-D}{1-3D}{U}_{\mathrm{dc}}---\left(6\right)$

Wherein D is straight-through duty ratio;

According to formula (2), formula (3), formula (4), formula (5) and formula (6), the finally U under non-straight-through-1 state, non-straight-through 0 state and non-straight-through+1 state _ivalue is u under upper pass-through state or lower pass-through state _ivalue is so just realize and improved the DC-link voltage of Z source three level neutral-point-clamped formula inverters, and then improved the output voltage of system, and then improved the output voltage of system.

Apply such scheme of the present invention, effectively improved Z source three level neutral-point-clamped formula inverter output voltages.

Brief description of the drawings

Figure l is structural representation of the present invention.

Embodiment

Below in conjunction with accompanying drawing, summary of the invention is described further:

Shown in Fig. 1, improve the device of the output voltage of Z source three level neutral-point-clamped formula inverters, comprise the first DC power supply U _dc1with the second DC power supply U _dc2, the first DC power supply U _dc1positive pole with the first diode D _inpositive pole be electrically connected, the first described diode D _innegative pole and the first DC power supply U _dc1negative pole with being electrically connected with a Z source network of the first switched inductors and second switch inductance, the second DC power supply U _dc2positive pole with the second diode D ^, _inpositive pole be electrically connected, the second described diode D ^, _innegative pole and the second DC power supply U _dc2negative pole with being electrically connected with the 2nd Z source network of the 3rd switched inductors and the 4th switched inductors, the one Z source network and the 2nd Z source network are all electrically connected with three level NPC inverter circuits, and three level NPC inverter circuits are electrically connected with A phase load, B phase load and C phase load.A described Z source network comprises the first capacitor C ₁with the second capacitor C ₂, the first described capacitor C ₁one extremely with the first inductance L ₁a utmost point, the first diode D _innegative pole and the 3rd diode D ₁positive pole be electrically connected, the first inductance L ₁another extremely with the 4th diode D ₂anodal and the 5th diode D ₃positive pole be electrically connected, the 4th diode D ₂negative pole with the 3rd diode D ₁negative pole and the second inductance L ₂a utmost point be electrically connected, the 5th described diode D ₃negative pole with the second capacitor C ₂a utmost point and the second inductance L ₂another utmost point be electrically connected, the first inductance L ₁, the second inductance L ₂, the 3rd diode D ₁, the 4th diode D ₂and the 5th diode D ₃form the first switched inductors; The first described capacitor C ₁another extremely with the 3rd inductance L ₃a utmost point and the 6th diode D ₄positive pole be electrically connected, the 6th described diode D ₄negative pole with the 7th diode D ₅negative pole and the 4th inductance L ₄a utmost point be electrically connected, the 7th described diode D ₅positive pole with the 8th diode D ₆anodal and the 3rd inductance L ₃another utmost point be electrically connected, the 8th described diode D ₆negative pole with the second capacitor C ₂another utmost point, the first DC power supply U _dc1negative pole and the 4th inductance L ₄another utmost point be electrically connected, the 3rd inductance L ₃, the 4th inductance L ₄, the 6th diode D ₄, the 7th diode D ₅and the 8th diode D ₆form second switch inductance.The 2nd described Z source network comprise the 3rd capacitor C ' ₁with the 4th capacitor C ' ₂, described the 3rd capacitor C ' ₁one extremely with the 5th inductance L ' ₁a utmost point, the second diode D' _innegative pole and the 9th diode D' ₁positive pole be electrically connected, the 5th inductance L ' ₁another extremely with the tenth diode D' ₂anodal and the 11 diode D' ₃positive pole be electrically connected, the tenth diode D' ₂negative pole with the 9th diode D' ₁negative pole and the 6th inductance L ' ₂a utmost point be electrically connected, the 11 described diode D' ₃negative pole with the 4th capacitor C ' ₂a utmost point and the 6th inductance L ' ₂another utmost point be electrically connected, the 5th inductance L ' ₁, the 6th inductance L ' ₂, the 9th diode D' ₁, the tenth diode D' ₂and the 11 diode D' ₃form the 3rd switched inductors; Described the 3rd capacitor C ' ₁another extremely with the 7th inductance L ' ₃a utmost point and the 12 diode D' ₄positive pole be electrically connected, the 12 described diode D' ₄negative pole with the 13 diode D' ₅negative pole and the 8th inductance L ' ₄a utmost point be electrically connected, the 13 described diode D' ₅positive pole with the 14 diode D' ₆anodal and the 7th inductance L ' ₃another utmost point be electrically connected, the 14 described diode D' ₆negative pole with the 4th capacitor C ' ₂another utmost point, the second DC power supply U _dc2negative pole and the 8th inductance L ' ₄another utmost point be electrically connected, the 7th inductance L ' ₃, the 8th inductance L ' ₄, the 12 diode D' ₄, the 13 diode D' ₅and the 14 diode D' ₆form the 4th switched inductors.Three described level NPC inverter circuits comprise the one or three level NPC inverse variation circuit, the two or three level NPC inverse variation circuit and the three or three level NPC inverse variation circuit parallel with one another, and wherein the one or three level NPC inverse variation circuit comprises the first switch transistor T _a1, the first switch transistor T _a1collector electrode be electrically connected with the negative pole of the 17 diode 17, the first switch transistor T _a1emitter with negative pole, the negative pole of the 18 diode 18, the second switch pipe T of the 15 diode 15 _a2collector electrode and the positive pole of the 17 diode 17 be electrically connected, second switch pipe T _a2emitter with positive pole, the 3rd switch transistor T of the 18 diode 18 _a3collector electrode, negative pole and the A phase load of the 19 diode 19 be electrically connected, the 3rd switch transistor T _a3emitter with positive pole, the 4th switch transistor T of the 19 diode 19 _a4collector electrode, the 20 negative pole of diode 20 and the positive pole of the 16 diode 16 be electrically connected, the 4th switch transistor T _a4emitter be electrically connected with the positive pole of the 20 diode 20; The two or three level NPC inverse variation circuit comprises the 5th switch transistor T _b1, the 5th switch transistor T _b1collector electrode be electrically connected with the negative pole of the 23 diode 23, the 5th switch transistor T _b1emitter with negative pole, the negative pole of the 24 diode 24, the 6th switch transistor T of the 21 diode 21 _b2collector electrode and the positive pole of the 23 diode 23 be electrically connected, the 6th switch transistor T _b2emitter with positive pole, the 7th switch transistor T of the 24 diode 24 _b3collector electrode, negative pole and the B phase load of the 25 diode 19 be electrically connected, the 7th switch transistor T _b3emitter with positive pole, the 8th switch transistor T of the 25 diode 25 _b4collector electrode, the 26 negative pole of diode 26 and the positive pole of the 22 diode 22 be electrically connected, the 8th switch transistor T _b4emitter be electrically connected with the positive pole of the 26 diode 26; The three or three level NPC inverse variation circuit comprises the 9th switch transistor T _c1, the 9th switch transistor T _c1collector electrode be electrically connected with the negative pole of the 29 diode 29, the 9th switch transistor T _c1emitter with negative pole, the negative pole of the 30 diode 30, the tenth switch transistor T of the 27 diode 27 _c2collector electrode and the positive pole of the 29 diode 29 be electrically connected, the tenth switch transistor T _c2emitter with positive pole, the 11 switch transistor T of the 30 diode 30 _c3collector electrode, negative pole and the C phase load of the 31 diode 31 be electrically connected, the 11 switch transistor T _c3emitter close pipe T with the positive pole of the 31 diode 31, twelvemo _c4collector electrode, the 32 negative pole of diode 32 and the positive pole of the 28 diode 28 be electrically connected, twelvemo close pipe T _c4emitter be electrically connected with the positive pole of the 32 diode 32; The first described switch transistor T _a1collector electrode, the 5th switch transistor T _b1collector electrode and the 9th switch transistor T _c1collector electrode with the second described capacitor C ₂a utmost point be electrically connected; The 4th described switch transistor T _a4collector electrode, the 8th switch transistor T _b4collector electrode and twelvemo close pipe T _c4collector electrode with the 3rd described capacitor C ' ₁a utmost point be electrically connected; The 11 described diode D' ₃negative pole and the 6th diode D ₄positive pole be electrically connected with the negative pole of the positive pole of the 15 diode 15, the 16 diode 16, the positive pole of the 21 diode 21, the negative pole of the 22 diode 22, the negative pole anodal and the 28 diode 28 of the 27 diode 27.The first described inductance L ₁inductance value, the second inductance L ₂inductance value, the 3rd inductance L ₃inductance value, the 4th inductance L ₄inductance value, the 5th inductance L ' ₁inductance value, the 6th inductance L ' ₂inductance value, the 7th inductance L ' ₃inductance value and the 8th inductance L ' ₄inductance value be L, L is greater than zero real number, the first described capacitor C ₁capacitance, the second capacitor C ₂capacitance, the 3rd capacitor C ' ₁capacitance and the 4th capacitor C ' ₂capacitance be C, C is greater than zero real number, the first described DC power supply U _dc1magnitude of voltage and the second DC power supply U _dc2magnitude of voltage be U _dc, U _dcfor real number, so just can meet the condition of following formula group (1):

$\left\{\begin{array}{c}{U}_{L1}=U_{L2}=U_{L3}=U_{L4}=U_L\\ U_{L1}^{\′}=U_{L2}^{\′}=U_{L3}^{\′}=U_{L4}^{\′}=U_L^{\′}\\ U_{C1}=U_{C2}=U_C\\ U_{C1}^{\′}=U_{C2}^{\′}=U_C^{\′}\end{array}\right.---\left(1\right)$

Wherein U _l1it is the first inductance L ₁inductive drop value, U _l2it is the second inductance L ₂inductive drop value, U _l3it is the 3rd inductance L ₃inductive drop value, U _l4it is the 4th inductance L ₄inductive drop value, U' _l1be the 5th inductance L ' ₁inductive drop value, U' _l2be the 6th inductance L ' ₂inductive drop value, U' _l3be the 7th inductance L ' ₃inductive drop value, U' _l4be the 8th inductance L ' ₄inductive drop value, U _c1it is the first capacitor C ₁capacitance voltage value, U _c2it is the second capacitor C ₂capacitance voltage value, U' _c1be the 3rd capacitor C ' ₁capacitance voltage value, U' _c2be the 4th capacitor C ' ₂capacitance voltage value, U _l1, U _l2, U _l3and U _l4equate and be U _l, U' _l1, U' _l2, U' _l3and U' _l4equate and be U' _l, U _c1and U _c2equate and be U _c, U' _c1and U' _c2equate and be U' _c, U _l, U' _l, U _cand U' _cbe real number value.

The method of the raising output voltage of the device of the output voltage of described raising Z source three level neutral-point-clamped formula inverters, as follows:

When at the first diode D _inwith the second diode D ^, _inconducting the first DC power supply U respectively _dc1with the second DC power supply U _dc2condition under, in a switch periods, in the first switch transistor T _a1with second switch pipe T _a2for conducting state the 3rd switch transistor T _a3with the 4th switch transistor T _a4under off state, for the output voltage of A phase load just in non-straight-through+1 state; At second switch pipe T _a2with the 3rd switch transistor T _a3for conducting state the first switch transistor T _a1with the 4th switch transistor T _a4under off state, for the output voltage of A phase load just in non-straight-through 0 state; In the first switch transistor T _a1with second switch pipe T _a2for off state the 3rd switch transistor T _a3with the 4th switch transistor T _a4under conducting state, for the output voltage of A phase load just in non-straight-through-1 state;

When at the first diode D _inwith the second diode D ^, _inconducting the first DC power supply U respectively _dc1with the second DC power supply U _dc2condition under, in a switch periods, in the 5th switch transistor T _b1with the 6th switch transistor T _b2for conducting state the 7th switch transistor T _b3with the 8th switch transistor T _b4under off state, for the output voltage of B phase load just in non-straight-through+1 state; In the 6th switch transistor T _b2with the 7th switch transistor T _b3for conducting state the 5th switch transistor T _b1with the 8th switch transistor T _b4under off state, for the output voltage of B phase load just in non-straight-through 0 state; In the 5th switch transistor T _b1with the 6th switch transistor T _b2for off state the 7th switch transistor T _b3with the 8th switch transistor T _b4under conducting state, for the output voltage of B phase load just in non-straight-through-1 state;

When at the first diode D _inwith the second diode D ^, _inconducting the first DC power supply U respectively _dc1with the second DC power supply U _dc2condition under, in a switch periods, in the 9th switch transistor T _c1with the tenth switch transistor T _c2for conducting state the 11 switch transistor T _c3close pipe T with twelvemo _c4under off state, for the output voltage of C phase load just in non-straight-through+1 state; In the tenth switch transistor T _c2with the 11 switch transistor T _c3for conducting state the 9th switch transistor T _c1close pipe T with twelvemo _c4under off state, for the output voltage of C phase load just in non-straight-through 0 state; In the 9th switch transistor T _c1with the tenth switch transistor T _c2for off state the 11 switch transistor T _c3close pipe T with twelvemo _c4under conducting state, for the output voltage of C phase load just in non-straight-through-1 state;

Work as at the first diode D like this _inwith the second diode D ^, _inconducting the first DC power supply U respectively _dc1with the second DC power supply U _dc2condition under, in a switch periods, also just met as the condition in formula (2) group:

$\left\{\begin{array}{c}{2U}_L=U_{\mathrm{dc}}-U_C\\ U_i/2=U_C-{2U}_L\\ U_{+N}=U_i/2,U_N=0,U_{-N}=-U_i/2\end{array}\right.---\left(2\right)$

Wherein U _lrepresent equal U _l1, U _l2, U _l3and U _l4value, U _crepresent equal U _c1and U _c2value, U _land U _cbe real number value, U _l1it is the first inductance L ₁inductive drop value, U _l2it is the second inductance L ₂inductive drop value, U _l3it is the 3rd inductance L ₃inductive drop value, U _l4it is the 4th inductance L ₄inductive drop value, U _c1it is the first capacitor C ₁capacitance voltage value, U _c2it is the second capacitor C ₂capacitance voltage value, U _ifor the direct-current chain crest voltage value of the Z source three level neutral-point-clamped formula inverters in the device of the output voltage of described raising Z source three level neutral-point-clamped formula inverters, U _{+ N}for working as at the first diode D _inwith the second diode D ^, _inconducting the first DC power supply U respectively _dc1with the second DC power supply U _dc2condition under in non-straight-through+1 state for the output voltage values of A phase load, in non-straight-through+1 state for the output voltage values of B phase load or the output voltage values for C phase load in non-straight-through+1 state, U _nfor working as at the first diode D _inwith the second diode D ^, _inconducting the first DC power supply U respectively _dc1with the second DC power supply U _dc2condition under in non-straight-through 0 state for the output voltage values of A phase load, in non-straight-through 0 state for the output voltage values of B phase load or the output voltage values for C phase load in non-straight-through 0 state, U _-Nfor working as at the first diode D _inwith the second diode D ^, _inconducting the first DC power supply U respectively _dc1with the second DC power supply U _dc2condition under in non-straight-through-1 state for the output voltage values of A phase load, in non-straight-through-1 state for the output voltage values of B phase load or the output voltage values for C phase load in non-straight-through-1 state;

When at the first diode D _inturn-off and the second diode D ^, _inconducting the second DC power supply U _dc2condition under, in a switch periods, the first switch transistor T _a1, second switch pipe T _a2with the 3rd switch transistor T _a3for conducting state the 4th switch transistor T _a4under off state, for the output voltage of A phase load just in upper pass-through state;

When at the first diode D _inturn-off and the second diode D ^, _inconducting the second DC power supply U _dc2condition under, in a switch periods, the 5th switch transistor T _b1, the 6th switch transistor T _b2with the 7th switch transistor T _b3for conducting state the 8th switch transistor T _b4under off state, for the output voltage of B phase load just in upper pass-through state;

When at the first diode D _inturn-off and the second diode D ^, _inconducting the second DC power supply U _dc2condition under, in a switch periods, the 9th switch transistor T _c1, the tenth switch transistor T _c2with the 11 switch transistor T _c3for conducting state twelvemo is closed pipe T _c4under off state, for the output voltage of C phase load just in upper pass-through state;

Work as at the first diode D like this _inturn-off and the second diode D ^, _inconducting the second DC power supply U _dc2condition under, in a switch periods, also just met as the condition in formula (3) group:

$\left\{\begin{array}{c}{U}_{C1}=U_{C2}=U_C\\ U_{L1}=U_{L2}=U_{L3}=U_{L4}=U_L\\ U_C=U_L\\ U_i=U_C-{2U}_L\\ U_u=-U_i\end{array}\right.---\left(3\right)$

Wherein U _lrepresent equal U _l1, U _l2, U _l3and U _l4value, U _crepresent equal U _c1and U _c2value, U _land U _cbe real number value, U _l1it is the first inductance L ₁inductive drop value, U _l2it is the second inductance L ₂inductive drop value, U _l3it is the 3rd inductance L ₃inductive drop value, U _l4it is the 4th inductance L ₄inductive drop value, U _c1it is the first capacitor C ₁capacitance voltage value, U _c2it is the second capacitor C ₂capacitance voltage value, U _ifor the direct-current chain crest voltage value of the Z source three level neutral-point-clamped formula inverters in the device of the output voltage of described raising Z source three level neutral-point-clamped formula inverters, U _ufor working as at the first diode D _inturn-off and the second diode D ^, _inconducting the second DC power supply U _dc2condition under in upper pass-through state for the output voltage values of A phase load, in upper pass-through state for the output voltage values of B phase load or the output voltage values for C phase load in upper pass-through state;

When at the second diode D ^, _inturn-off and the first diode D _inconducting the first DC power supply U _dc2condition under, in a switch periods, the first switch transistor T _a1for off state second switch pipe T _a2, the 3rd switch transistor T _a3with the 4th switch transistor T _a4under conducting state, for the output voltage of A phase load just in lower pass-through state;

When at the second diode D ^, _inturn-off and the first diode D _inconducting the first DC power supply U _dc2condition under, in a switch periods, the 5th switch transistor T _b1for off state the 6th switch transistor T _b2, the 7th switch transistor T _b3with the 8th switch transistor T _b4under conducting state, for the output voltage of B phase load just in lower pass-through state;

When at the second diode D ^, _inturn-off and the first diode D _inconducting the first DC power supply U _dc2condition under, in a switch periods, the 9th switch transistor T _c1for off state the tenth switch transistor T _c2, the 11 switch transistor T _c3close pipe T with twelvemo _c4under conducting state, for the output voltage of C phase load just in lower pass-through state;

Such the second diode D ^, _inturn-off and the first diode D _inconducting the second DC power supply U _dc2condition under, in a switch periods, also just met as the condition in formula (4) group:

$\left\{\begin{array}{c}{U}_{C1}^{\′}=U_{C2}^{\′}=U_C^{\′}\\ U_{L1}^{\′}=U_{L2}^{\′}=U_{L3}^{\′}=U_{L4}^{\′}=U_L^{\′}\\ U_C=U_L\\ U_i=U_C-{2U}_L\\ U_d=U_i\end{array}\right.---\left(4\right)$

Wherein U' _l1be the 5th inductance L ' ₁inductive drop value, U' _l2be the 6th inductance L ' ₂inductive drop value, U' _l3be the 7th inductance L ' ₃inductive drop value, U' _l4be the 8th inductance L ' ₄inductive drop value, U' _c1be the 3rd capacitor C ' ₁capacitance voltage value, U' _c2be the 4th capacitor C ' ₂capacitance voltage value, U' _l1, U' _l2, U' _l3and U' _l4equate and be U' _l, U' _c1and U' _c2equate and be U' _c, U _l, U' _l, U _cand U' _cbe real number value, U _ifor the direct-current chain crest voltage value of the Z source three level neutral-point-clamped formula inverters in the device of the output voltage of described raising Z source three level neutral-point-clamped formula inverters, U _dfor working as at the second diode D ^, _inturn-off and the first diode D _inconducting the second DC power supply U _dc2condition under in lower pass-through state for the output voltage values of A phase load, in lower pass-through state for the output voltage values of B phase load or the output voltage values for C phase load in lower pass-through state;

In addition in a switch periods, according to inductance weber equilibrium relation also meet formula (5):

$U_{C}D+\frac{1}{2}(U_{\mathrm{dc}}-U_C)(1-D)=0---\left(5\right)$

Can release formula (6) by formula (5)

$U_C=\frac{1-D}{1-3D}{U}_{\mathrm{dc}}---\left(6\right)$

Wherein D is straight-through duty ratio;

According to formula (2), formula (3), formula (4), formula (5) and formula (6), the finally U under non-straight-through-1 state, non-straight-through 0 state and non-straight-through+1 state _ivalue is u under upper pass-through state or lower pass-through state _ivalue is so just realize the raising output voltage that improves the device of the output voltage of Z source three level neutral-point-clamped formula inverters.

Under equal straight-through duty ratio, apparatus and method of the present invention will improve more than 35% than the output voltage of prior art like this.

The above, it is only preferred embodiment of the present invention, not the present invention is done to any pro forma restriction, although the present invention discloses as above with preferred embodiment, but not in order to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when can utilizing the technology contents of above-mentioned announcement to make a little change or being modified to the equivalent embodiment of equivalent variations, in every case be not depart from technical solution of the present invention content, according to technical spirit of the present invention, within the spirit and principles in the present invention, the any simple amendment that above embodiment is done, be equal to replacement and improvement etc., within all still belonging to the protection range of technical solution of the present invention.

Claims (6)

1. one kind is improved the device of the output voltage of Z source three level neutral-point-clamped formula inverters, it is characterized in that comprising the first DC power supply and the second DC power supply, the positive pole of the first DC power supply is electrically connected with the positive pole of the first diode, the negative pole of the first described diode and the negative pole of the first DC power supply are with being electrically connected with a Z source network of the first switched inductors and second switch inductance, the positive pole of the second DC power supply is electrically connected with the positive pole of the second diode, the negative pole of the second described diode and the negative pole of the second DC power supply are with being electrically connected with the 2nd Z source network of the 3rd switched inductors and the 4th switched inductors, the one Z source network and the 2nd Z source network are all electrically connected with three level NPC inverter circuits, three level NPC inverter circuits are with A phase load, B phase load and C phase load are electrically connected.

2. the device of the output voltage of raising according to claim 2 Z source three level neutral-point-clamped formula inverters, it is characterized in that a described Z source network comprises the first electric capacity and the second electric capacity, one utmost point of one extremely same the first inductance of the first described electric capacity, the positive pole of the negative pole of the first diode and the 3rd diode is electrically connected, another of the first inductance is extremely electrically connected with the positive pole anodal and the 5th diode of the 4th diode, the negative pole of the 4th diode is electrically connected with the negative pole of the 3rd diode and a utmost point of the second inductance, the negative pole of the 5th described diode is electrically connected with a utmost point of the second electric capacity and another utmost point of the second inductance, the first inductance, the second inductance, the 3rd diode, the 4th diode and the 5th diode have formed the first switched inductors, another of the first described electric capacity is extremely electrically connected with a utmost point of the 3rd inductance and the positive pole of the 6th diode, the negative pole of the 6th described diode is electrically connected with the negative pole of the 7th diode and a utmost point of the 4th inductance, the positive pole of the 7th described diode is electrically connected with another utmost point anodal and the 3rd inductance of the 8th diode, the negative pole of the 8th described diode is with another utmost point of the second electric capacity, another utmost point of the negative pole of the first DC power supply and the 4th inductance is electrically connected, the 3rd inductance, the 4th inductance, the 6th diode, the 7th diode and the 8th diode have formed second switch inductance.

3. the device of the output voltage of raising according to claim 2 Z source three level neutral-point-clamped formula inverters, it is characterized in that the 2nd described Z source network comprises the 3rd electric capacity and the 4th electric capacity, one utmost point of one extremely same the 5th inductance of the 3rd described electric capacity, the positive pole of the negative pole of the second diode and the 9th diode is electrically connected, another of the 5th inductance is extremely electrically connected with the positive pole anodal and the 11 diode of the tenth diode, the negative pole of the tenth diode is electrically connected with the negative pole of the 9th diode and a utmost point of the 6th inductance, the negative pole of the 11 described diode is electrically connected with a utmost point of the 4th electric capacity and another utmost point of the 6th inductance, the 5th inductance, the 6th inductance, the 9th diode, the tenth diode and the 11 diode have formed the 3rd switched inductors, another of the 3rd described electric capacity is extremely electrically connected with a utmost point of the 7th inductance and the positive pole of the 12 diode, the negative pole of the 12 described diode is electrically connected with the negative pole of the 13 diode and a utmost point of the 8th inductance, the positive pole of the 13 described diode is electrically connected with another utmost point anodal and the 7th inductance of the 14 diode, the negative pole of the 14 described diode is with another utmost point of the 4th electric capacity, another utmost point of the negative pole of the second DC power supply and the 8th inductance is electrically connected, the 7th inductance, the 8th inductance, the 12 diode, the 13 diode and the 14 diode have formed the 4th switched inductors.

4. the device of the output voltage of raising according to claim 3 Z source three level neutral-point-clamped formula inverters, it is characterized in that three described level NPC inverter circuits comprise the one or three level NPC inverse variation circuit parallel with one another, the two or three level NPC inverse variation circuit and the three or three level NPC inverse variation circuit, wherein the one or three level NPC inverse variation circuit comprises the first switching tube, the collector electrode of the first switching tube is electrically connected with the negative pole of the 17 diode, the emitter of the first switching tube is with the negative pole of the 15 diode, the negative pole of the 18 diode, the collector electrode of second switch pipe and the positive pole of the 17 diode are electrically connected, the emitter of second switch pipe is with the positive pole of the 18 diode, the collector electrode of the 3rd switching tube, the negative pole of the 19 diode and A phase load are electrically connected, the emitter of the 3rd switching tube is with the positive pole of the 19 diode, the collector electrode of the 4th switching tube, the 20 negative pole of diode and the positive pole of the 16 diode are electrically connected, the 4th switch transistor T _a4emitter be electrically connected with the positive pole of the 20 diode, the two or three level NPC inverse variation circuit comprises the 5th switching tube, the collector electrode of the 5th switching tube is electrically connected with the negative pole of the 23 diode, the emitter of the 5th switching tube is with the negative pole of the 21 diode, the negative pole of the 24 diode, the 6th collector electrode of switching tube and the positive pole of the 23 diode are electrically connected, the emitter of the 6th switching tube is with the positive pole of the 24 diode, the collector electrode of the 7th switching tube, the negative pole of the 25 diode and B phase load are electrically connected, the emitter of the 7th switching tube is with the positive pole of the 25 diode, the collector electrode of the 8th switching tube, the 26 negative pole of diode and the positive pole of the 22 diode are electrically connected, the emitter of the 8th switching tube is electrically connected with the positive pole of the 26 diode, the three or three level NPC inverse variation circuit comprises the 9th switching tube, the collector electrode of the 9th switching tube is electrically connected with the negative pole of the 29 diode, the emitter of the 9th switching tube is with the negative pole of the 27 diode, the negative pole of the 30 diode, the tenth collector electrode of switching tube and the positive pole of the 29 diode are electrically connected, the emitter of the tenth switching tube is with the positive pole of the 30 diode, the collector electrode of the 11 switching tube, the negative pole of the 31 diode and C phase load are electrically connected, the emitter of the 11 switching tube is with the positive pole of the 31 diode, twelvemo is closed the collector electrode of pipe, the 32 negative pole of diode and the positive pole of the 28 diode are electrically connected, the emitter that twelvemo is closed pipe is electrically connected with the positive pole of the 32 diode, the collector electrode of the collector electrode of the first described switching tube, the collector electrode of the 5th switching tube and the 9th switching tube is electrically connected with a utmost point of the second described electric capacity, the collector electrode that the collector electrode of the 4th described switching tube, the collector electrode of the 8th switching tube and twelvemo are closed pipe is electrically connected with a utmost point of the 3rd described electric capacity, the negative pole of the 11 described diode and the positive pole of the 6th diode are electrically connected with the positive pole of the 15 diode, the negative pole of the 16 diode, the positive pole of the 21 diode, the negative pole of the 22 diode, the negative pole anodal and the 28 diode of the 27 diode.

5. the device of the output voltage of raising according to claim 4 Z source three level neutral-point-clamped formula inverters, is characterized in that the first described inductance L ₁inductance value, the second inductance L ₂inductance value, the inductance value of the 3rd inductance, the inductance value of the 4th inductance, the inductance value of the 5th inductance, inductance value, the inductance value of the 7th inductance and the inductance value of the 8th inductance of the 6th inductance be L, L is greater than zero real number, the first described capacitor C ₁capacitance, the second capacitor C ₂capacitance, the 3rd capacitor C ' ₁capacitance and the 4th capacitor C ' ₂capacitance be C, C is greater than zero real number, the magnitude of voltage of the first described DC power supply and the magnitude of voltage of the second DC power supply are U _dc, U _dcfor real number, so just can meet the condition of following formula group (1):

$\left\{\begin{array}{c}{U}_{L1}=U_{L2}=U_{L3}=U_{L4}=U_L\\ U_{L1}^{\′}=U_{L2}^{\′}=U_{L3}^{\′}=U_{L4}^{\′}=U_L^{\′}\\ U_{C1}=U_{C2}=U_C\\ U_{C1}^{\′}=U_{C2}^{\′}=U_C^{\′}\end{array}\right.---\left(1\right)$

Wherein U _l1it is the first inductance L ₁inductive drop value, U _l2be the second inductance inductive drop value, U _l3be the 3rd inductance inductive drop value, U _l4be the inductive drop value of the 4th inductance, U' _l1be the inductive drop value of the 5th inductance, U' _l2be the inductive drop value of the 6th inductance, U' _l3be the inductive drop value of the 7th inductance, U' _l4be the inductive drop value of the 8th inductance, U _c1be the capacitance voltage value of the first electric capacity, U _c2be the capacitance voltage value of the second electric capacity, U' _c1be the capacitance voltage value of the 3rd electric capacity, U' _c2be the capacitance voltage value of the 4th electric capacity, U _l1, U _l2, U _l3and U _l4equate and be U _l, U' _l1, U' _l2, U' _l3and U' _l4equate and be U' _l, U _c1and U _c2equate and be U _c, U' _c1and U' _c2equate and be U' _c, U _l, U' _l, U _cand U' _cbe real number value.

6. the method for the raising output voltage of the device of the output voltage of described raising Z source three level neutral-point-clamped formula inverters according to claim 5, is characterized in that as follows:

When under the condition in the first diode and the second diode difference conducting the first DC power supply and the second DC power supply, in a switch periods, be conducting state and the 3rd switching tube and the 4th switching tube are under off state at the first switching tube and second switch pipe, for the output voltage of A phase load just in non-straight-through+1 state; Be conducting state and the first switching tube and the 4th switching tube are under off state at second switch pipe and the 3rd switching tube, for the output voltage of A phase load just in non-straight-through 0 state; Be off state and the 3rd switching tube and the 4th switching tube are under conducting state at the first switching tube and second switch pipe, for the output voltage of A phase load just in non-straight-through-1 state;

When under the condition in the first diode and the second diode difference conducting the first DC power supply and the second DC power supply, in a switch periods, be conducting state and the 7th switching tube and the 8th switching tube are under off state at the 5th switching tube and the 6th switching tube, for the output voltage of B phase load just in non-straight-through+1 state; Be conducting state and the 5th switching tube and the 8th switching tube are under off state at the 6th switching tube and the 7th switching tube, for the output voltage of B phase load just in non-straight-through 0 state; Be off state and the 7th switching tube and the 8th switching tube are under conducting state at the 5th switching tube and the 6th switching tube, for the output voltage of B phase load just in non-straight-through-1 state;

When under the condition in the first diode and the second diode difference conducting the first DC power supply and the second DC power supply, in a switch periods, be conducting state and the 11 switching tube and twelvemo are closed pipe under off state at the 9th switching tube and the tenth switching tube, for the output voltage of C phase load just in non-+ 1 state that leads directly to; Be conducting state and the 9th switch transistor T at the tenth switching tube and the 11 switching tube _c1close pipe under off state with twelvemo, for the output voltage of C phase load just in non-0 state that leads directly to; Be off state and the 11 switching tube and twelvemo are closed pipe under conducting state at the 9th switching tube and the tenth switching tube, for the output voltage of C phase load just in non--1 state that leads directly to;

When under the condition in the first diode and the second diode difference conducting the first DC power supply and the second DC power supply, in a switch periods, also just meet as the condition in formula (2) group like this:

$\left\{\begin{array}{c}{2U}_L=U_{\mathrm{dc}}-U_C\\ U_i/2=U_C-{2U}_L\\ U_{+N}=U_i/2,U_N=0,U_{-N}=-U_i/2\end{array}\right.---\left(2\right)$

Wherein U _lrepresent equal U _l1, U _l2, U _l3and U _l4value, U _crepresent equal U _c1and U _c2value, U _land U _cbe real number value, U _l1be the inductive drop value of the first inductance, U _l2be the inductive drop value of the second inductance, U _l3be the inductive drop value of the 3rd inductance, U _l4be the inductive drop value of the 4th inductance, U _c1be the capacitance voltage value of the first electric capacity, U _c2be the capacitance voltage value of the second electric capacity, U _ifor the direct-current chain crest voltage value of the Z source three level neutral-point-clamped formula inverters in the device of the output voltage of described raising Z source three level neutral-point-clamped formula inverters, U _{+ N}for when the first diode and the second diode respectively under the condition of conducting the first DC power supply and the second DC power supply in non-straight-through+1 state for the output voltage values of A phase load, in non-straight-through+1 state for the output voltage values of B phase load or the output voltage values for C phase load in non-straight-through+1 state, U _nfor when the first diode and the second diode respectively under the condition of conducting the first DC power supply and the second DC power supply in non-straight-through 0 state for the output voltage values of A phase load, in non-straight-through 0 state for the output voltage values of B phase load or the output voltage values for C phase load in non-straight-through 0 state, U _-Nfor when the first diode and the second diode respectively under the condition of conducting the first DC power supply and the second DC power supply in non-straight-through-1 state for the output voltage values of A phase load, in non-straight-through-1 state for the output voltage values of B phase load or the output voltage values for C phase load in non-straight-through-1 state;

When under the condition in the first diode shutoff and second diode current flow the second DC power supply, in a switch periods, the first switching tube, second switch pipe and the 3rd switching tube are conducting state and the 4th switching tube is under off state, for the output voltage of A phase load just in upper pass-through state;

When under the condition in the first diode shutoff and second diode current flow the second DC power supply, in a switch periods, the 5th switching tube, the 6th switching tube and the 7th switching tube are conducting state and the 8th switching tube is under off state, for the output voltage of B phase load just in upper pass-through state;

When under the condition in the first diode shutoff and second diode current flow the second DC power supply, in a switch periods, the 9th switching tube, the tenth switching tube and the 11 switching tube are that conducting state and twelvemo are closed pipe under off state, for the output voltage of C phase load just in upper pass-through state;

When under the condition in the first diode shutoff and second diode current flow the second DC power supply, in a switch periods, also just meet as the condition in formula (3) group like this:

$\left\{\begin{array}{c}{U}_{C1}=U_{C2}=U_C\\ U_{L1}=U_{L2}=U_{L3}=U_{L4}=U_L\\ U_C=U_L\\ U_i=U_C-{2U}_L\\ U_u=-U_i\end{array}\right.---\left(3\right)$

Wherein U _lrepresent equal U _l1, U _l2, U _l3and U _l4value, U _crepresent equal U _c1and U _c2value, U _land U _cbe real number value, U _l1be the first inductance inductive drop value, U _l2be the inductive drop value of the second inductance, U _l3be the inductive drop value of the 3rd inductance, U _l4be the inductive drop value of the 4th inductance, U _c1be the capacitance voltage value of the first electric capacity, U _c2be the capacitance voltage value of the second electric capacity, U _ifor the direct-current chain crest voltage value of the Z source three level neutral-point-clamped formula inverters in the device of the output voltage of described raising Z source three level neutral-point-clamped formula inverters, U _ufor when turn-off at the first diode and the condition of second diode current flow the second DC power supply under on pass-through state for the output voltage values of A phase load, on pass-through state for the output voltage values of B phase load or on the output voltage values for C phase load of pass-through state;

When under the condition in the second diode shutoff and first diode current flow the first DC power supply, in a switch periods, the first switching tube is off state and second switch pipe, the 3rd switching tube and the 4th switching tube are under conducting state, for the output voltage of A phase load just in lower pass-through state;

When under the condition in the second diode shutoff and first diode current flow the first DC power supply, in a switch periods, the 5th switching tube is off state and the 6th switching tube, the 7th switching tube and the 8th switching tube are under conducting state, for the output voltage of B phase load just in lower pass-through state;

When under the condition in the second diode shutoff and first diode current flow the first DC power supply, in a switch periods, the 9th switching tube is that off state and the tenth switching tube, the 11 switching tube and twelvemo are closed pipe under conducting state, for the output voltage of C phase load just in lower pass-through state;

Under the condition of such the second diode shutoff and first diode current flow the first DC power supply, in a switch periods, also just meet as the condition in formula (4) group:

$\left\{\begin{array}{c}{U}_{C1}^{\′}=U_{C2}^{\′}=U_C^{\′}\\ U_{L1}^{\′}=U_{L2}^{\′}=U_{L3}^{\′}=U_{L4}^{\′}=U_L^{\′}\\ U_C=U_L\\ U_i=U_C-{2U}_L\\ U_d=U_i\end{array}\right.---\left(4\right)$

Wherein U' _l1be the 5th inductance L ' ₁inductive drop value, U' _l2be the inductive drop value of the 6th inductance, U' _l3be the inductive drop value of the 7th inductance, U' _l4be the inductive drop value of the 8th inductance, U' _c1be the capacitance voltage value of the 3rd electric capacity, U' _c2be the capacitance voltage value of the 4th electric capacity, U' _l1, U' _l2, U' _l3and U' _l4equate and be U' _l, U' _c1and U' _c2equate and be U' _c, U _l, U' _l, U _cand U' _cbe real number value, U _ifor the direct-current chain crest voltage value of the Z source three level neutral-point-clamped formula inverters in the device of the output voltage of described raising Z source three level neutral-point-clamped formula inverters, U _dturn-off and first diode current flow the second DC power supply U for working as at the second diode _dc2condition under in lower pass-through state for the output voltage values of A phase load, in lower pass-through state for the output voltage values of B phase load or the output voltage values for C phase load in lower pass-through state;

In addition in a switch periods, according to inductance weber equilibrium relation system meet formula (5):

$U_{C}D+\frac{1}{2}(U_{\mathrm{dc}}-U_C)(1-D)=0---\left(5\right)$

Can release formula (6) by formula (5)

$U_C=\frac{1-D}{1-3D}{U}_{\mathrm{dc}}---\left(6\right)$

Wherein D is straight-through duty ratio;

According to formula (2), formula (3), formula (4), formula (5) and formula (6), the finally U under non-straight-through-1 state, non-straight-through 0 state and non-straight-through+1 state _ivalue is u under upper pass-through state or lower pass-through state _ivalue is so just realize and improved the DC-link voltage of Z source three level neutral-point-clamped formula inverters, and then improved the output voltage of system.