CN104035897B - A kind of storage control - Google Patents
A kind of storage control Download PDFInfo
- Publication number
- CN104035897B CN104035897B CN201410261435.1A CN201410261435A CN104035897B CN 104035897 B CN104035897 B CN 104035897B CN 201410261435 A CN201410261435 A CN 201410261435A CN 104035897 B CN104035897 B CN 104035897B
- Authority
- CN
- China
- Prior art keywords
- data
- module
- storage
- nand
- single layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Read Only Memory (AREA)
- Dram (AREA)
Abstract
The present invention provides a kind of storage control, by the way that single layer cell storage array is integrated into storage control, and substitute some or all of data buffer, therefore integrated single layer cell NAND storage arrays provided by the present invention have that memory cell size is small, cost is low, the advantage such as low in energy consumption, non-volatile, thus this new NAND storage controls structure of the present invention is suitable for power consumption, cost or the higher application field of capacity requirement.At the same time, if certain application environment is also very high to rate request, so single layer cell NAND array can be used as second level data buffer, a hybrid data buffer is formed with first order SRAM or DRAM cache device, high-speed read-write is achieveed the purpose that, and has met that unit size is small, cost is low, the advantage such as low in energy consumption, non-volatile.
Description
Technical field
The present invention relates to semiconductor applications, and in particular to a kind of storage control, height can be realized using the storage control
Fast data buffer storage.
Background technology
NAND type solid state hard disc has become the non-volatile storage technologies of current mainstream, is widely used in data center, a
The every field such as people's computer, mobile phone, intelligent terminal, consumer electronics, and the ever-increasing situation of demand is still presented.NAND type
The manufacturing process of solid state hard disc has also had evolved to 16nm, is converted from the manufacturing process of two dimension to three-dimensional manufacturing process.Three
Star company has announced commercially producing for the three dimensional NAND chip of 128Gb24 unit (bit) stacking.Company of Micron Technology then declares
The cloth New Two Dimensional NAND chip of 16nm128Gb, uses new two-dimensional cell structure to break through conventional two-dimensional structure size and contracts
Small limitation.
The manufacturing process of traditional NAND solid state hard discs storage chip and storage control chip is generally different, Samsung,
The big factory of the NAND solid state hard discs such as Micron Technology, Toshiba, Hynix uses special production line, incompatible with CMOS logic technique.With
Each wafer foundry based on CMOS technology can not realize the production of NAND solid state hard discs.Traditional two-dimentional NAND solid state hard discs
Although to more than ten nanometers of technique, this is only to be stored for NAND for technique and three dimensional NAND solid state hard disc technique
For array, its logic control circuit and artificial circuit part are still using very backward CMOS technology, such as only have
180nm、130nm.On the one hand it is the consideration of chip cost, advanced CMOS processing procedures can increase the manufacture cost of chip；On the other hand
It is that the write-in of NAND solid state hard disc units needs the voltage of 20V or so, high-voltage CMOS pipe is realized in advanced CMOS technology
Technology difficulty and cost are also bigger.The New Two Dimensional NAND solid state hard discs technique of Micron Technology in memory cell areas although employ height
The Advanced CMOS Process of dielectric constant metal gate (HKMG), but the logic control circuit of its chip and artificial circuit part are still adopted
It is very backward CMOS technology, and the HKMG techniques of its NAND solid state hard disc unit are using the work of Gate First
Technique integration method, it is incompatible with the Advanced CMOS Process of current mainstream.
General nand memory can be divided into single layer cell NAND (SLC, single-level cell) and multilevel-cell
NAND (MLC, multi-level cell).SLC is exactly a storage unit storage 1bit data, its main feature is that of high cost, appearance
Measure that small, speed is fast, erasable number (Endurance) is up to 100,000 times, 10 times higher than MLC solid state hard disc, data holding ability
(Retention) it is 10 years.MLC is exactly that a storage unit can store multiple bit data, can realize every list at present
Member storage 2bit and 3bit data, its maximum feature is exactly that the big cost of capacity is low, but speed is slow, and endurance life is relatively low, number
It can also decline according to holding capacity.Since the data stored in each MLC memory cell are more, structure is relative complex, error it is several
Rate can increase, it is necessary to carry out more error corrections, the poor multilevel-cell NAND of some data holding abilities even need into
So as to ensureing data reliability, these actions can all cause its performance significantly to lag behind SLC simple in structure to consolidate row periodic refresh
State hard disk.
The overall structure of General N AND solid state hard discs is as shown in Figure 1.Storage control is connected to system by front end interface
Bus.Storage control is connected by back side bus with NAND chip.The control core of storage control is in storage control
Status it is most important, and the important indicator influenced on the performance of storage control is exactly interior data buffer
(buffer).Data buffer optimizes the data transfer between system and NAND chip.System reads data from solid state hard disc
Order be generally：Page data is read from NAND chip by back side bus；Page data is saved in data buffer；System
System reads I/O data by Front Side Bus from data buffer.The order of system to solid state disk write data is firm with reading data
It is good opposite.As it can be seen that data buffer plays the role of stepping-stone (stepping Stone), system and NAND chip are alleviated
The unmatched problem of reading speed, while be additionally beneficial to raising the resistance to of NAND chip and write the service life.With solid state hard disc memory capacity
More come it is also big, it is also increasing to the capacity requirement of buffer.The capacity of increase data buffer makes storage control chip face
Product increase, cost constantly rise, and power consumption is also continuously increased.And another solution method is exactly by the way of external pad
To reduce storage control chip area and cost, structure is as shown in Figure 2.External data buffer be generally SRAM structures or
Person's dram chip, although capacity increases, power consumption is still very big, especially DRAM, it is also necessary to be periodically flushed to keep number
According to complete, additionally due to making reading speed to decrease using external mode rather than integration mode.
The content of the invention
A kind of storage control, data processing is carried out suitable for operating system to External memory equipment, wherein, the storage
Controller includes core controller module and data buffer module；
The operating system sends operational order to the core controller module, and the core controller module is according to connecing
The operational order of receipts, optimizes the data between the operating system and the External memory equipment by the data buffering module
Interaction；
Wherein, the data buffering module include one by single layer cell NAND storage arrays, NOR FLASH arrays, PCM,
The storage unit that one or more combinations in ReRAM, FeRAM, SRAM, DRAM are formed, for data cached.
Above-mentioned storage control, wherein, the storage unit includes first order memory and second level memory, described
The buffer memory capacity of first order memory is less than the buffer memory capacity of the second level memory；
Wherein, the first order memory includes SRAM or DRAM memory, and the second level memory is single layer cell
NAND storage arrays.
Above-mentioned storage control, wherein, the control gate of the single layer cell NAND storage arrays is based on Gate Last high
Prepared by karat gold category grid (gate last HKMG, high dielectric metal gate) technique.
Above-mentioned storage control, wherein, the storage control further includes a front end interface and a back end interface；
The data buffering module is connected with the front end interface and back end interface；And
The core controller module is connected with the front end interface and back end interface.
Single layer cell NAND storage arrays are integrated into storage control by the present invention, and substitute some or all of data
Buffer module, all possesses obvious advantage in reading and erasable speed, endurance life and power consumption.If certain application at the same time
Environment is also very high to rate request, then single layer cell NAND array can be used as second level data buffer, with the first order
Other memories such as SRAM or DRAM cache device form a hybrid data buffer, that is, have reached the mesh of high-speed read-write
, and meet that unit size is small, cost is low, the advantage such as low in energy consumption, non-volatile.
Brief description of the drawings
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, the present invention and its feature, outer
Shape and advantage will become more apparent upon.Identical mark indicates identical part in whole attached drawings.Not deliberately proportionally
Draw attached drawing, it is preferred that emphasis is the purport of the present invention is shown.
Attached drawing 1 is traditional NAND solid state hard disc overall structure diagrams；
Attached drawing 2 is the NAND solid state hard disc structure diagrams of conventional art external data buffer；
Attached drawing 3 is a kind of new NAND storage control schematic diagrames of the present invention；
Attached drawing 4 is a kind of specific embodiment schematic diagram of the present invention.
Embodiment
In the following description, a large amount of concrete details are given in order to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention may not need one or more of these details and be able to
Implement.In other examples, in order to avoid with the present invention obscure, for some technical characteristics well known in the art not into
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or component, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, component and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Explain technical scheme.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these detailed descriptions, this
Invention can also have other embodiment.
Embodiment one
The invention discloses a kind of storage control, the place suitable for operating system to External memory equipment progress data
Reason.With reference to shown in Fig. 3, it includes data buffering module (buffer), data register module (register) and core control
Device module (MCU) processed, data buffering module and data registration module are connected with core controller module.Operating system sends behaviour
Instruct to controller core core module, instruction of the core controller module according to received by it and NAND chip group is carried out
Read-write, erasing and/or the address of cache of data, and loss equalizing control and DMA controls are carried out to the External memory equipment
System operation, further, controller core core module optimize operation system according to the operational order received by data buffering module
Data interaction between system and the external memory storage.
The storage control is additionally provided with front end interface and back end interface, and data buffering module and core controller module are equal
It is connected with front end interface and back end interface, and an error correction module is provided between data buffering module and back end interface
(Error Correction Code, ECC), for carrying out real-time data correction.
Above-mentioned front end interface is other interfaces such as PCI, IDE or SATA, and back end interface is Toggle DDR or ONFI etc.
Other interfaces.ONFI (Open NAND Flash Interface) interface is by Intel, magnesium light, Hynix, Taiwan group's connection
Electronics, SanDisk, Sony, flies to announce that one kind of unified the connection nand flash memory formulated and control chip connects headed by rope semiconductor
Mouth standard；And Toggle ddr interfaces standard is jointly customized by Samsung and Toshiba.Due to storage control provided by the present invention
Device processed employs the interface standard of current mainstream, therefore application is also than wide.Meanwhile the back end interface connects some NAND cores
Piece group.In certain embodiments, which can be single layer cell NAND chip group, multilevel-cell NAND chip group, 3D
Stack one or more combinations in NAND chip group, i.e. the NAND chip group can be the NAND chip group of single type, example
As single layer cell NAND chip group or multilevel-cell NAND chip group or 3D stack NAND chip group or mixing
NAND chip group, such as not only include single layer cell NAND chip, but also comprising multilevel-cell NAND chip, 3D heaps can also be included
Folded NAND chip etc., it will not go into details for related embodiment.
Further, data buffering module include one by single layer cell NAND storage arrays, NOR FLASH arrays, PCM,
The storage unit that one or more combinations in ReRAM, FeRAM, SRAM, DRAM are formed, for data cached.It is further excellent
Choosing, which is single layer cell NAND storage arrays, and the control gate included by single layer cell NAND storage arrays
It is based on prepared by Gate Last high dielectrics metal gate (high-k metal gate) technique, is realized with metal gate process
The control gate of NAND cell, rather than traditional polysilicon is around control gate, it is possible to achieve it is advanced with high-dielectric constant metal grid
Integrating for CMOS technology, it is compatible with the Gate Last CMOS technologies of current mainstream, overcome current NAND solid state hard discs technique
Can not be compatible with advanced standard logic process the problem of, so that logic control circuit and artificial circuit part speed are faster,
And then greatly improve the readwrite performance of NAND chip.It can realize that realizing for high speed is various multiple using Gate Last CMOS technologies
Miscellaneous logic function, and larger NAND memory spaces can be obtained.Meanwhile the device prepared by based on Gate Last techniques,
Can also there is good performance in terms of high-performance ＆ low-power consumption.
In other embodiment of the present invention, single layer cell NAND storage arrays can also be NOR FLASH arrays, can be real
Now faster reading speed, but it is erasable slower；At the same time also can be using novel memory devices come instead of single layer cell NAND storage battle arrays
The memories such as row, PCM, ReRAM, FeRAM as escribed above, its main feature is that reading speed is more accelerated, erasable speed greatly improves,
And area can continue to zoom out, it is most important that leakage current smaller, being introduced into data buffer module can play
Lift the effect of device performance.
Fig. 3 is illustrated that in data cache module, at the same be provided with single layer cell NAND storage arrays and SRAM or
DRAM memory.If certain application environment is also very high to rate request, then single layer cell NAND storage arrays can conduct
Second level data buffer, forms a hybrid data cache module with first order SRAM or DRAM cache device, both reached
The purpose of read-write is improved, and meets that unit size is small, cost is low, the advantage such as low in energy consumption, non-volatile.And for hybrid
For data buffer, the capacity of first order data buffer storage can be far smaller than the capacity of second level caching, so that two-stage is each
While all being brought into play significantly from the advantages of buffer, the shortcomings that respective is also desalinated well.It should be noted that
If SRAM or DRAM cache device are provided with data cache module, then must also include it in data cache module
His storage unit of any one or more.
This integrated single layer cell NAND storage arrays of the present invention are contrasted with traditional SRAM or DRAM data buffer
As shown in table 1：
Table 1
Can be learnt according to form, although erasable speed and it is resistance to write the service life in terms of single layer cell NAND storage arrays and SRAM
Or DRAM memory cell is compared and do not have advantage, but the single layer cell NAND storage arrays that the present invention integrates possess memory cell size
It is small, cost is low, the advantage such as low in energy consumption, non-volatile, thus this new NAND storage control structures of the present invention are suitable for
To power consumption, cost or the higher application field of capacity requirement.
When computer system needs to carry out read operation to External memory equipment, controller core core module is received according to it
The computer system send read operation instruction, the corresponding data stored in External memory equipment is transferred by back end interface
Into data buffering module, computer system is read by front end interface and is stored in data buffering mould data in the block；
When computer system needs to carry out write operation to External memory equipment, controller core core module is received according to it
Computer system send write operation instruction, the data that the computer system writes are kept in data by front end interface
Buffer module, and stored by the data that back end interface tune goes in data buffering module to store into portion's storage device.
Embodiment two
A specific embodiment is named to be further elaborated.
Can be with assuming that for one per unit 2bit multilevel-cell NAND solid state hard discs, in its storage inside controller chip
Integrated single layer cell NAND storage arrays are so as to substitute whole traditional data buffers, structure such as Fig. 4 of whole solid state hard disc
It is shown.When system reads data from solid state hard disc, sequentially it is：(1) storage control take orders and by back side bus from
Page data is read in per unit 2bit multilevel-cell NAND chips；(2) page data is saved in single layer cell NAND data bufferings
In device；(3) system reads I/O data by Front Side Bus from single layer cell NAND data buffers.When system is hard to solid-state
When data are write in disk, sequentially it is：(1) data that system needs to write by Front Side Bus transmission；(2) I/O for writing needs
Data are saved in single layer cell NAND data buffers；(3) storage control takes orders I/O data by back side bus
Write in units of page in the specified address in every unit 2bit multilevel-cell NAND chips.As it can be seen that the present invention is this new
NAND storage controls structure can realize traditional data buffer function with single layer cell NAND storage arrays, can play
The effect of stepping-stone (stepping stone), and possess the characteristics such as leakage small power consumption, cost be low and non-volatile.
The present invention proposes a kind of new NAND controller structure, single layer cell based on Gate Last high-K metal gates technique
NAND storage arrays are integrated into storage control, and substitute some or all of data buffer.Using single layer cell NAND
Storage array rather than multilevel-cell NAND array or 3D stack NAND array be because single layer cell NAND array reading and
All possesses obvious advantage in erasable speed, endurance life and power consumption.The present invention is this to be integrated into NAND storage controls
Single layer cell NAND storage arrays why can substitute traditional data buffer, firstly because its energy in read or write speed
Enough read or write speeds close to even up to traditional data buffer, this mainly has benefited from：(1) Gate Last CMOS technologies are used
Allow the logic circuit of storage control and analog circuit uses more advanced CMOS technology, speed faster, thus can be with
Faster speed realizes various complicated logic functions so that storage control greatly improves in performance；(2) since storage is controlled
Device processed is integrated into same SoC chip with single layer cell NAND storage arrays, thus can use speed faster therebetween
The broader parallel port data transfer of bandwidth, thus storage control can more quickly access single layer cell NAND storage arrays,
Thus the read or write speed of NAND storage arrays is further improved；(3) since Gate Last CMOS metal grid techniques to deposit
Storage controller performance greatly improves, thus further improves the readwrite performance to single layer cell NAND storage arrays.It is above-mentioned
Reason enables the read or write speed of integrated single layer cell NAND storage arrays close to even up to traditional data buffer
Read or write speed, compared with external data buffer chip, read or write speed possibly even faster, thus the replacement portion that has the ability completely
Point or whole traditional data buffers.
In conclusion due to present invention employs as above technical solution, being deposited by the way that single layer cell storage array is integrated into
Store up in controller, and substitute some or all of data buffer, therefore integrated single layer cell NAND provided by the present invention
Storage array has that memory cell size is small, cost is low, the advantage such as low in energy consumption, non-volatile, thus the present invention is this new
NAND storage controls structure is suitable for power consumption, cost or the higher application field of capacity requirement.Meanwhile if certain is applied
Environment is also very high to rate request, then single layer cell NAND array can be used as second level data buffer, with the first order
SRAM or DRAM cache device form a hybrid data buffer, that is, have achieveed the purpose that high-speed read-write, and meet list
Elemental size is small, cost is low, the advantage such as low in energy consumption, non-volatile.And for the hybrid data buffer, the first series
According to the capacity of caching can be far smaller than the second level caching capacity, so two-stage each buffer the advantages of all play significantly
While out, also desalinate well the shortcomings that respective, and then device performance is improved in global level, and effectively controlled into
This.
Presently preferred embodiments of the present invention is described above.It is to be appreciated that the invention is not limited in above-mentioned
Particular implementation, wherein the equipment and structure be not described in detail to the greatest extent are construed as giving reality with the common mode in this area
Apply；Any those skilled in the art, without departing from the scope of the technical proposal of the invention, all using the disclosure above
Methods and technical content many possible changes and modifications are made to technical solution of the present invention, or be revised as equivalent variations etc.
Embodiment is imitated, this has no effect on the substantive content of the present invention.Therefore, every content without departing from technical solution of the present invention, foundation
The technical spirit of the present invention still falls within the present invention to any simple modifications, equivalents, and modifications made for any of the above embodiments
In the range of technical solution protection.
Claims (2)
1. a kind of storage control, carries out data processing, it is characterised in that described suitable for operating system to External memory equipment
Storage control includes core controller module and data buffer module；
The operating system sends operational order to the core controller module, and the core controller module is according to reception
Operational order, the data optimized by the data buffering module between the operating system and the External memory equipment are handed over
Mutually；
The data buffering module include by single layer cell NAND storage arrays, NOR FLASH arrays, PCM, ReRAM, FeRAM,
The storage unit that one or more combinations in SRAM, DRAM are formed, for data cached；
The storage unit includes first order memory and second level memory, and the buffer memory capacity of the first order memory is less than
The buffer memory capacity of the second level memory；
Wherein, the first order memory is SRAM or DRAM memory, and the second level memory is deposited for single layer cell NAND
Store up array；The storage control further includes data register module, a front end interface and a back end interface；
The data register module is connected with the core controller module, the data buffering module respectively with the core control
Device module processed, the front end interface are connected with the back end interface, the core controller module also respectively with the preceding termination
Mouth is connected with the back end interface；
And an error correction module is provided between the data buffering module and the back end interface, for being counted in real time
According to amendment.
2. storage control as claimed in claim 1, it is characterised in that the control gate of the single layer cell NAND storage arrays
Based on prepared by Gate-last high-K metal gate techniques.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410261435.1A CN104035897B (en) | 2014-06-12 | 2014-06-12 | A kind of storage control |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410261435.1A CN104035897B (en) | 2014-06-12 | 2014-06-12 | A kind of storage control |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104035897A CN104035897A (en) | 2014-09-10 |
| CN104035897B true CN104035897B (en) | 2018-04-24 |
Family
ID=51466668
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410261435.1A Active CN104035897B (en) | 2014-06-12 | 2014-06-12 | A kind of storage control |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104035897B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104811495B (en) * | 2015-04-27 | 2018-06-08 | 北京交通大学 | A kind of networking component content storage method and module for wisdom contract network |
| CN109379075B (en) * | 2018-11-21 | 2023-08-29 | 灿芯半导体(上海)股份有限公司 | Multi-mode ONFI training circuit |
| CN110413233A (en) * | 2019-07-26 | 2019-11-05 | 杭州电子科技大学 | A kind of solid-state hard disk controller |
| CN110413234B (en) * | 2019-07-26 | 2024-04-26 | 杭州电子科技大学 | Solid state disk |
| CN114093874A (en) * | 2020-05-20 | 2022-02-25 | 长江存储科技有限责任公司 | 3D NAND flash memory device and integration method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101656104A (en) * | 2008-08-22 | 2010-02-24 | 群联电子股份有限公司 | Flash memory storage system and data writing method thereof |
| CN101866678A (en) * | 2009-04-17 | 2010-10-20 | 常州南基天盛科技有限公司 | Flash disk |
| CN103136118A (en) * | 2011-11-21 | 2013-06-05 | 西部数据技术公司 | Disk drive data caching using a multi-tiered memory |
| CN103500076A (en) * | 2013-10-13 | 2014-01-08 | 张维加 | Novel USB protocol computer accelerating device based on multi-channel SLC NAND and DRAM cache memory |
| CN103593324A (en) * | 2013-11-12 | 2014-02-19 | 上海新储集成电路有限公司 | Quick-start and low-power-consumption computer system-on-chip with self-learning function |
| CN103677654A (en) * | 2012-09-24 | 2014-03-26 | 联想(北京)有限公司 | Method and electronic equipment for storing data |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7953931B2 (en) * | 1999-08-04 | 2011-05-31 | Super Talent Electronics, Inc. | High endurance non-volatile memory devices |
| US8078794B2 (en) * | 2000-01-06 | 2011-12-13 | Super Talent Electronics, Inc. | Hybrid SSD using a combination of SLC and MLC flash memory arrays |
| CN101162449B (en) * | 2007-10-08 | 2010-06-02 | 福州瑞芯微电子有限公司 | NAND FLASH controller and data interactive method with NAND FLASH chip |
-
2014
- 2014-06-12 CN CN201410261435.1A patent/CN104035897B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101656104A (en) * | 2008-08-22 | 2010-02-24 | 群联电子股份有限公司 | Flash memory storage system and data writing method thereof |
| CN101866678A (en) * | 2009-04-17 | 2010-10-20 | 常州南基天盛科技有限公司 | Flash disk |
| CN103136118A (en) * | 2011-11-21 | 2013-06-05 | 西部数据技术公司 | Disk drive data caching using a multi-tiered memory |
| CN103677654A (en) * | 2012-09-24 | 2014-03-26 | 联想(北京)有限公司 | Method and electronic equipment for storing data |
| CN103500076A (en) * | 2013-10-13 | 2014-01-08 | 张维加 | Novel USB protocol computer accelerating device based on multi-channel SLC NAND and DRAM cache memory |
| CN103593324A (en) * | 2013-11-12 | 2014-02-19 | 上海新储集成电路有限公司 | Quick-start and low-power-consumption computer system-on-chip with self-learning function |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104035897A (en) | 2014-09-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11237765B2 (en) | Data writing method and storage device | |
| US9818707B2 (en) | Stacked memory chip having reduced input-output load, memory module and memory system including the same | |
| CN109791519B (en) | Optimized use of non-volatile storage system and local flash memory with integrated compute engine | |
| CN103984509B (en) | Isomery NAND type solid state hard disk and the method for improving its performance | |
| CN104035897B (en) | A kind of storage control | |
| DE102009037984B4 (en) | Memory unit for a hierarchical memory architecture | |
| US8619490B2 (en) | Semiconductor memory devices | |
| CN109840223A (en) | Memory device, including its electronic device and electronic device operating method | |
| TW201248406A (en) | Integrated circuit memory device | |
| CN104866246A (en) | Solid state hybrid drive | |
| JP2015536521A (en) | Partial page memory operation | |
| TW201310454A (en) | Flash memory controller | |
| US20170351449A1 (en) | Memory system | |
| US20200019508A1 (en) | Memory device | |
| US20140068144A1 (en) | Heterogeneous data paths for systems having tiered memories | |
| JP2010198209A (en) | Semiconductor memory device | |
| US9552874B2 (en) | Combined memory block and data processing system having the same | |
| WO2018063614A1 (en) | Using compression to increase capacity of a memory-side cache with large block size | |
| CN104409099A (en) | FPGA (field programmable gate array) based high-speed eMMC (embedded multimedia card) array controller | |
| CN101930407B (en) | Flash memory control circuit and memory system and data transmission method thereof | |
| US10892021B2 (en) | On-die capacitor for a memory device | |
| TWI687811B (en) | Data storage apparatus and system information programming mehtod | |
| CN108133728A (en) | A kind of non-volatile RAM | |
| CN109426453A (en) | Data storage device and its operating method | |
| EP3751423A2 (en) | Technologies for adding computational ability to memory devices without changing media layers |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |