CN104022863B - A kind of integer field chaos circuit - Google Patents

Abstract

The invention discloses a kind of integer field chaos circuit, including Uniform noise signal generating circuit（N1）, sampling hold circuit（N2）, decoding circuit（N3）, iterative circuit（N4）, D/A change-over circuits（N5）Five parts are constituted, Uniform noise signal generating circuit（N1）Output terminals A and sampling hold circuit（N2）Input B be connected；Sampling hold circuit（N2）Output end C respectively with decoding circuit（N3）Four inputs D0, D1, D2, D3 be connected；Decoding circuit（N3）Output end E0 and iterative circuit（N4）Middle XOR0 input is connected, and output end E1 is connected with XOR1 input, and output end E2 is connected with XOR2 input, and output end E3 is connected with XOR3 input；XOR0, XOR1, XOR2, XOR3 output end are connected with the input of DAC1 in D/A change-over circuits N5 in iterative circuit N4, and XOR0, XOR1, XOR2, XOR3 input are connected with the input of DAC2 in D/A change-over circuits N5 in iterative circuit N4.The present invention inherently solves the dynamics degenerate problem that finite precision effect is brought.

Description

A kind of integer field chaos circuit

Technical field

The present invention relates to circuit, more particularly to chaos circuit, a kind of integer field chaos circuit is specifically referred to, is translated by regulation Code circuit N₃In four comparators Comparator0, Comparator1, Comparator2, Comparator3 comparison it is electric Pressure, when meeting 0V, 1V, 2V, 3V respectively, circuit generation 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 totally 16 The integer field chaotic signal of numerical chracter.It can be not only used for the encryption and decryption of vision signal and digital watermarking, but also as one Planting independent chaos signal generator, there is provided a kind of new integer field chaos signal source.

Background technology

In chaos encryption, whether the chaos system that information security depends primarily on generation has good statistical test special Property.However, current chaos system is based on real number domain operation, belong to real number field chaos system.Since all computings（Iteration）All Carried out in real number field, when being realized with computer or digital device, the limitation of word length necessarily causes finite precision effect, this Outside, continuous chaos also needs to just become chaos sequence by conversion, and this conversion can also introduce rounding error.

In order to solve this problem, we are being recently proposed integer field chaos system, refer specifically on integer field A class chaos system of computing is carried out, compared with existing real number field chaos system, it is mainly characterized by inherently having solved The dynamics degenerate problem that limit precision effect is brought.

The content of the invention

A kind of integer field chaos circuit is provided it is an object of the invention to overcome of the prior art not enough.

The present invention solves the technical scheme that is used of prior art problem：A kind of integer field chaos circuit, including it is uniform Circuit occurs for noise signal（N1）, sampling hold circuit（N2）, decoding circuit（N3）, iterative circuit（N4）, D/A change-over circuits （N5）Five parts, produce the integer field of 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 totally 16 numerical chracters Chaotic signal, its annexation is：

（1）The Uniform noise signal generating circuit（N1）Output terminals A and sampling hold circuit（N2）Input B phases Even；

（2）The sampling hold circuit（N2）Output end C respectively with decoding circuit（N3）Four input D0, D1, D2, D3 are connected；

（3）The decoding circuit（N3）Output end E0 and iterative circuit（N4）In the first NOR gate circuit（XOR0）It is defeated Enter end to be connected, output end E1 and the second NOR gate circuit（XOR1）Input be connected, output end E2 and the 3rd NOR gate circuit （XOR2）Input be connected, output end E3 and the 4th NOR gate circuit（XOR3）Input be connected；

（4）The iterative circuit（N4）In the first NOR gate circuit（XOR0）, the second NOR gate circuit（XOR1）, it is the 3rd different OR circuit（XOR2）, the 4th NOR gate circuit（XOR3）Output end and D/A change-over circuits（N5）Middle DAC1 input phase Even, iterative circuit（N4）In first, second, third, fourth NOR gate circuit（XOR0、XOR1、XOR2、XOR3）Input with D/A change-over circuits（N5）Middle DAC2 input is connected.

By adjusting decoding circuit（N3）In four comparators（Comparator0、Comparator1、Comparator2、 Comparator3）Comparison voltage, when meeting 0V, 1V, 2V, 3V respectively, circuit produce 0,1,2,3,4,5,6,7,8,9,10, 11st, the integer field chaotic signal of 12,13,14,15 totally 16 numerical chracters.

Compared with existing real number field chaos circuit, the present invention inherently solves the power that finite precision effect is brought Learn degenerate problem.

Brief description of the drawings

Fig. 1 is a kind of circuit diagram of integer field chaos circuit of the invention；

Fig. 2 is Uniform noise signal generating circuit in the embodiment of the present invention；

Fig. 3 is sampling hold circuit in the embodiment of the present invention；

Fig. 4 is decoding circuit in the embodiment of the present invention；

Fig. 5 is comparison circuit in the embodiment of the present invention；

Fig. 6 is iterative circuit in the embodiment of the present invention；

Fig. 7 is D/A change-over circuits in the embodiment of the present invention；

Fig. 8 is circuit realiration result figure of the embodiment of the present invention.

The realization, functional characteristics and advantage of the object of the invention will be described further referring to the drawings in conjunction with the embodiments.

Embodiment

Technical scheme is described in detail below with reference to drawings and the specific embodiments, to become apparent from, intuitively Understand the invention essence of the present invention.

As shown in figure 1, occurring electricity the embodiments of the invention provide a kind of integer field chaos circuit, including Uniform noise signal Road（N1）, sampling hold circuit（N2）, decoding circuit（N3）, iterative circuit（N4）, D/A change-over circuits（N5）Five parts, production The integer field chaotic signal of raw 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 totally 16 numerical chracters, it is connected Relation is：

（1）The Uniform noise signal generating circuit（N1）Output terminals A and sampling hold circuit（N2）Input B phases Even；

（2）The sampling hold circuit（N2）Output end C respectively with decoding circuit（N3）Four input D0, D1, D2, D3 are connected；

（3）The decoding circuit（N3）Output end E0 and iterative circuit（N4）In the first NOR gate circuit（XOR0）It is defeated Enter end to be connected, output end E1 and the second NOR gate circuit（XOR1）Input be connected, output end E2 and the 3rd NOR gate circuit （XOR2）Input be connected, output end E3 and the 4th NOR gate circuit（XOR3）Input be connected；

（4）The iterative circuit（N4）In the first NOR gate circuit（XOR0）, the second NOR gate circuit（XOR1）, it is the 3rd different OR circuit（XOR2）, the 4th NOR gate circuit（XOR3）Output end and D/A change-over circuits（N5）Middle DAC1 input phase Even, iterative circuit（N4）In first, second, third, fourth NOR gate circuit（XOR0、XOR1、XOR2、XOR3）Input with D/A change-over circuits（N5）Middle DAC2 input is connected.

By adjusting decoding circuit（N3）In four comparators（Comparator0、Comparator1、Comparator2、 Comparator3）Comparison voltage, when meeting 0V, 1V, 2V, 3V respectively, circuit produce 0,1,2,3,4,5,6,7,8,9,10, 11st, the integer field chaotic signal of 12,13,14,15 totally 16 numerical chracters.

As shown in Fig. 2 Fig. 2 is Uniform noise signal generating circuit N1；Chip MM5837 occurs for broadband white noise signal Device, by 10Hz to 40Hz every octave 3dB wave filters, produces white noise signal.Noise whole frequency from 20Hz to 20kHz There is flat be uniformly distributed in section.Output is superimposed upon in 8.5V DC levelsNoise.Component parameters are in Fig. 1：Electric capacity,,,,.Resistance,,,。

Due to the N1 of Uniform noise signal generating circuit shown in Fig. 2 outputTo be superimposed upon in 8.5V DC levelsNoise, therefore need to carry out level conversion, by being exported after conversionForUniform noise signal.Level turns Each resistance value changed in circuit is,。

As shown in figure 3, Fig. 3 is sampling hold circuit N2, chip model is LF398.Supply voltage is,.3 pin in figure input for analog signal, and 5 pin are output, electric capacity, select in this experiment TakeLeft and right.For square-wave signal, frequency is, the amplitude of output is, in this experiment It is middle choose square wave frequency be。

NoticeIt is bigger,Frequency then can be lower, at this moment iteration speed is slower.If conversely,It is smaller, Frequency it is then higher, at this moment iteration speed is faster, due to the limitation of device speed itself, and iteration speed has a higher limit. When generally testing,There should be the value of a suitable size,Also there should be an appropriate frequency, circuit could normal work.

As shown in Fig. 4 to Fig. 5, Fig. 4 is decoding circuit N3, and Fig. 5 is the comparator circuit in decoding circuit N3, each resistance Parameter value be,,,,, displacement The size of level is.According to Fig. 5, the logical relation for obtaining comparator input and output is：

Further according to Fig. 4, obtaining decoding circuit N3 input/output relations is：

（1）WhenWhen,, obtain

（1）

（2）WhenWhen,, obtain

（2）

（3）WhenWhen,, obtain

（3）

（4）WhenWhen,, obtain

（4）

Notice that the noise of Fig. 1 outputs is met, andIt is that a grade is generally distributed（I.e. uniform point Cloth）Between random signal.In other words, 、、、This Value in four intervals is equally distributed, andSize and four interval corresponding relations be

（5）

Pass through above-mentioned comparison, it is known thatWithAll it is to wait the random signal being generally distributed, relation between the two is met：

（6）

If, the iterative equation for obtaining basic IDCS is

（7）

In formula。

By comparing (1)~(7) formula, another mathematic(al) representation of equal value for further obtaining (7) formula is as follows：

According to (8) formula, the circuit design drawing that must correspond to iterative equation is as shown in Figure 6.

As shown in fig. 7, Fig. 7 is D/A change-over circuit N5, wherein,,,

.D/A change-over circuits N5 chip is DAC0832, should be designed into as a straight-through mould Formula, that is, simply enter a tetrad, corresponding integer letter can be just converted at once Number.Logic corresponding relation is：When input isWhen, correspondence D/A converter is output as, when defeated Enter forWhen, it is corresponding to be output as, when input isWhen, it is corresponding to be output as... ..., when input isWhen, it is corresponding to be output as, adjust resistanceBig I Realize this corresponding relation.

Complex chart 2 ~ 7, the result for obtaining IDCS way circuit design drawings is as shown in Figure 8.According to Fig. 8, by adjusting decoding circuit Four comparators Comparator0, Comparator1, Comparator2, Comparator3 comparison voltage in N3, respectively When meeting 0V, 1V, 2V, 3V, circuit produces 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 totally 16 numerical chracters Integer field chaotic signal.Circuit realiration result is as shown in Figure 8.

The preferred embodiments of the present invention are the foregoing is only, are not intended to limit the scope of the invention, it is every to utilize Equivalent structure or equivalent flow conversion that description of the invention and accompanying drawing content are made, or directly or indirectly it is used in other correlations Technical field, be included within the scope of the present invention.

Claims (1)

1. a kind of integer field chaos circuit, it is characterised in that：Including Uniform noise signal generating circuit (N1), sampling hold circuit (N2), decoding circuit (N3), iterative circuit (N4), five parts of D/A change-over circuits (N5), produce 0,1,2,3,4,5,6,7,8, 9th, the integer field chaotic signal of 10,11,12,13,14,15 totally 16 numerical chracters, its annexation is：

(1) output terminals A of the Uniform noise signal generating circuit (N1) is connected with the input B of sampling hold circuit (N2)；

(2) four inputs D0, D1, D2, the D3 of the output end C of the sampling hold circuit (N2) respectively with decoding circuit (N3) It is connected；

(3) the output end E0 of the decoding circuit (N3) and the first NOR gate circuit (XOR0) in iterative circuit (N4) input It is connected, output end E1 is connected with the input of the second NOR gate circuit (XOR1), output end E2 and the 3rd NOR gate circuit (XOR2) input is connected, and output end E3 is connected with the input of the 4th NOR gate circuit (XOR3)；

(4) the first NOR gate circuit (XOR0), the second NOR gate circuit (XOR1), the 3rd XOR gate in the iterative circuit (N4) Circuit (XOR2), the output end of the 4th NOR gate circuit (XOR3) are connected with the input of DAC1 in D/A change-over circuits (N5), repeatedly For the first NOR gate circuit (XOR0), the second NOR gate circuit (XOR1), the 3rd NOR gate circuit (XOR2), in circuit (N4) The input of four NOR gate circuits (XOR3) is connected with the input of DAC2 in D/A change-over circuits (N5)；

By adjust in the decoding circuit (N3) four comparator Comparator0, Comparator1, Comparator2, Comparator3 comparison voltage, when meeting 0V, 1V, 2V, 3V respectively, the integer field chaos circuit produces 0,1,2,3,4, 5th, the integer field chaotic signal of 6,7,8,9,10,11,12,13,14,15 totally 16 numerical chracters；

The Uniform noise signal generating circuit (N1), chip MM5837 is broadband white noise signal generator, is arrived by 10Hz 40Hz every octave 3dB wave filters, produce white noise signal ξ (t)；Noise has flat from 20Hz to 20kHz in whole frequency range Smooth is uniformly distributed；Output is superimposed upon the 1V in 8.5V DC levels_P-PNoise；

The output ξ (t) of the Uniform noise signal generating circuit (N1) is the 1V being superimposed upon in 8.5V DC levels_P-PNoise, therefore Need to carry out level conversion, by exporting Uniform noise signals of the η (t) into 0~4V after changing；It is each in level shifting circuit Individual resistance value is R₅=R₆=R₈=R₉=10k Ω, R₇=40k Ω；

The sampling hold circuit (N2), chip model is LF398；Supply voltage is V₊=+15V, V_-=-15V；3 pin are simulation Signal is inputted, and 5 pin are output, electric capacity C_F=0.01~0.1 μ F；

Comparator circuit in the decoding circuit (N3), decoding circuit (N3), the parameter value of each resistance is R₁₀=13.5k Ω, R₁₁=1k Ω, R₁₂=10k Ω, R₁₃=40k Ω, R₁₄=R₁₅=R₁₆=10k Ω, the size of shift levels is E=4V；Than Logical relation compared with device input and output is：

$\left\{\begin{array}{cccc}if& \mathrm{\&eta;}\left(n\right)>U_1,& then& {\mathrm{\&eta;}}_1=1\\ if& \mathrm{\&eta;}\left(n\right)<U_i,& then& {\mathrm{\&eta;}}_i=0\end{array}\right.$

Further obtaining decoding circuit (N3) input/output relation is：

(1) 3V is worked as<During η (t)≤4V, η₃=η₂=η₁=η₀=1, obtain

$\left\{\begin{array}{c}{s}_3^n={\mathrm{\&eta;}}_3=1\\ s_2^n={\mathrm{\&eta;}}_3\&CirclePlus;{\mathrm{\&eta;}}_2=1\&CirclePlus;1=0\\ s_1^n={\mathrm{\&eta;}}_2\&CirclePlus;{\mathrm{\&eta;}}_1=1\&CirclePlus;1=0\\ s_0^n={\mathrm{\&eta;}}_1\&CirclePlus;{\mathrm{\&eta;}}_0=1\&CirclePlus;1=0\end{array}\right.---\left(1\right)$

(2) 2V is worked as<During η (t)≤3V, η₃=0, η₂=η₁=η₀=1, obtain

$\left\{\begin{array}{c}{s}_3^n={\mathrm{\&eta;}}_3=0\\ s_2^n={\mathrm{\&eta;}}_3\&CirclePlus;{\mathrm{\&eta;}}_2=0\&CirclePlus;1=1\\ s_1^n={\mathrm{\&eta;}}_2\&CirclePlus;{\mathrm{\&eta;}}_1=1\&CirclePlus;1=0\\ s_0^n={\mathrm{\&eta;}}_1\&CirclePlus;{\mathrm{\&eta;}}_0=1\&CirclePlus;1=0\end{array}\right.---\left(2\right)$

(3) 1V is worked as<During η (t)≤2V, η₃=η₂=0, η₁=η₀=1, obtain

$\left\{\begin{array}{c}{s}_3^n={\mathrm{\&eta;}}_3=0\\ s_2^n={\mathrm{\&eta;}}_3\&CirclePlus;{\mathrm{\&eta;}}_2=0\&CirclePlus;0=0\\ s_1^n={\mathrm{\&eta;}}_2\&CirclePlus;{\mathrm{\&eta;}}_1=0\&CirclePlus;1=1\\ s_0^n={\mathrm{\&eta;}}_1\&CirclePlus;{\mathrm{\&eta;}}_0=1\&CirclePlus;1=0\end{array}\right.---\left(3\right)$

(4) as 0V≤η (t)≤1V, η₃=η₂=η₁=0, η₀=1, obtain

$\left\{\begin{array}{c}{s}_3^n={\mathrm{\&eta;}}_3=0\\ s_2^n={\mathrm{\&eta;}}_3\&CirclePlus;{\mathrm{\&eta;}}_2=0\&CirclePlus;0=0\\ s_1^n={\mathrm{\&eta;}}_2\&CirclePlus;{\mathrm{\&eta;}}_1=0\&CirclePlus;0=0\\ s_0^n={\mathrm{\&eta;}}_1\&CirclePlus;{\mathrm{\&eta;}}_0=0\&CirclePlus;1=1\end{array}\right.---\left(4\right)$

When the noise of output meets 0V≤η (t)≤4V, and η (t) is the random letter that a grade is generally distributed between [0V, 4V] Number, and sⁿSize and four interval corresponding relations be

$\left\{\begin{array}{cccc}if& \mathrm{\&eta;}\left(t\right)\&Element;\&lsqb;0V,1V),& then& s^n=0\\ if& \mathrm{\&eta;}\left(t\right)\&Element;\&lsqb;1V,2V),& then& s^n=1\\ if& \mathrm{\&eta;}\left(t\right)\&Element;\&lsqb;2V,3V),& then& s^n=2\\ if& \mathrm{\&eta;}\left(t\right)\&Element;\&lsqb;3V,4V\&rsqb;,& then& s^n=3\end{array}\right.---\left(5\right)$

Pass through above-mentioned comparison, it is known that s_nWithAll it is to wait the random signal being generally distributed, relation between the two is met：

$\left\{\begin{array}{cccc}if& \mathrm{\&eta;}\left(t\right)\&Element;\&lsqb;0V,1V),& then& s^n=0\&DoubleLeftRightArrow;s_3^n{s}_2^n{s}_1^n{s}_0^n=0001\\ if& \mathrm{\&eta;}\left(t\right)\&Element;\&lsqb;1V,2V),& then& s^n=1\&DoubleLeftRightArrow;s_3^n{s}_2^n{s}_1^n{s}_0^n=0010\\ if& \mathrm{\&eta;}\left(t\right)\&Element;\&lsqb;2V,3V),& then& s^n=2\&DoubleLeftRightArrow;s_3^n{s}_2^n{s}_1^n{s}_0^n=0100\\ if& \mathrm{\&eta;}\left(t\right)\&Element;\&lsqb;3V,4V\&rsqb;,& then& s^n=3\&DoubleLeftRightArrow;s_3^n{s}_2^n{s}_1^n{s}_0^n=1000\end{array}\right.---\left(6\right)$

If N=4, the iterative equation for obtaining basic IDCS is

$\left\{\begin{array}{c}{x}_i^n=\left\{\begin{array}{ccc}{x}_i^{n-1}& if& i\&NotEqual;s^n\\ {\left(f\right(x^{n-1}\left)\right)}_i=\stackrel{\&OverBar;}{x_i^{n-1}}& if& i=s^n\end{array}\right.\\ i=0,1,2,3\end{array}\right.---\left(7\right)$

S in formulaⁿ∈ { 0,1,2, LN-1 }={ 0,1,2,3 }；

By comparing (1)~(7) formula, another mathematic(al) representation of equal value for further obtaining (7) formula is as follows：

$\left\{\begin{array}{c}{s}^n=0\&DoubleLeftRightArrow;s_3^n{s}_2^n{s}_1^n{s}_0^n=0001\\ s^n=1\&DoubleLeftRightArrow;s_3^n{s}_2^n{s}_1^n{s}_0^n=0010\\ s^n=2\&DoubleLeftRightArrow;s_3^n{s}_2^n{s}_1^n{s}_0^n=0100\\ s^n=3\&DoubleLeftRightArrow;s_3^n{s}_2^n{s}_1^n{s}_0^n=1000\end{array}\right.\&DoubleRightArrow;\left\{\begin{array}{c}{x}_i^n=\left\{\begin{array}{ccc}{x}_i^{n-1}& if& i\&NotEqual;s^n\\ {\left(f\right(x^{n-1}\left)\right)}_i=\stackrel{\&OverBar;}{x_i^{n-1}}& if& i=s^n\end{array}\right.\\ i=0,1,2,3\end{array}\right.\&DoubleLeftRightArrow;\left\{\begin{array}{c}{x}_3^n=x_3^{n-1}\&CirclePlus;s_3^n\\ x_2^n=x_2^{n-1}\&CirclePlus;s_2^n\\ x_1^n=x_1^{n-1}\&CirclePlus;s_1^n\\ x_0^n=x_0^{n-1}\&CirclePlus;s_0^n\end{array}\right.---\left(8\right)$

According to (8) formula, the circuit design drawing of iterative equation must be corresponded to；

The D/A change-over circuits (N5), wherein R₁₇=10k Ω, R₁₈=2k Ω, R₁₉=60k Ω, R₂₀=R₂₁=10k Ω；D/A turns The chip for changing circuit (N5) is DAC0832, is designed into for a direct mode operation, that is, simply entering a tetradCorresponding integer signal x can be just converted at onceⁿ；Logic corresponding relation is：When input isWhen, correspondence D/A converter is output as xⁿ=0V, when input isWhen, it is corresponding defeated Go out for xⁿ=1V, when input isWhen, it is corresponding to be output as xⁿ=2V ... ..., when input isWhen, it is corresponding to be output as xⁿ=15V, regulation resistance R₁₉Size realize this corresponding relation；

The IDCS way circuits design drawing by adjust in decoding circuit (N3) four comparator Comparator0, Comparator1, Comparator2, Comparator3 comparison voltage, when meeting 0V, 1V, 2V, 3V respectively, the integer Domain chaos circuit produces the integer field chaos of 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 totally 16 numerical chracters Signal.