CN104022863B - A Chaotic Circuit in Integer Domain - Google Patents

Abstract

The invention discloses a kind of integer field chaos circuit, including Uniform noise signal generating circuit（N1）, sampling hold circuit（N2）, decoding circuit（N3）, iterative circuit（N4）, D/A change-over circuits（N5）Five parts are constituted, Uniform noise signal generating circuit（N1）Output terminals A and sampling hold circuit（N2）Input B be connected；Sampling hold circuit（N2）Output end C respectively with decoding circuit（N3）Four inputs D0, D1, D2, D3 be connected；Decoding circuit（N3）Output end E0 and iterative circuit（N4）Middle XOR0 input is connected, and output end E1 is connected with XOR1 input, and output end E2 is connected with XOR2 input, and output end E3 is connected with XOR3 input；XOR0, XOR1, XOR2, XOR3 output end are connected with the input of DAC1 in D/A change-over circuits N5 in iterative circuit N4, and XOR0, XOR1, XOR2, XOR3 input are connected with the input of DAC2 in D/A change-over circuits N5 in iterative circuit N4.The present invention inherently solves the dynamics degenerate problem that finite precision effect is brought.

Description

A Chaotic Circuit in Integer Domain

technical field

The present invention relates to a circuit, in particular to a chaotic circuit, specifically to a chaotic circuit in the integer domain, by adjusting the comparison voltages _of the four comparators Comparator0, Comparator1, Comparator2, and Comparator3 in the decoding circuit N3, respectively satisfying 0V, 1V, and 2V , 3V, the circuit generates 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, a total of 16 digital symbols of chaotic signals in the integer domain. It can be used not only for encryption and decryption of video signals and digital watermarks, but also as an independent chaotic signal generator, providing a new integer domain chaotic signal source.

Background technique

In chaotic encryption, information security mainly depends on whether the generated chaotic system has good statistical test properties. However, the current chaotic system is based on the real number field operation, which belongs to the real number field chaotic system. Since all operations (iterations) are carried out on the real number field, when implemented by computers or digital devices, the limitation of word length will inevitably lead to finite precision effects. In addition, continuous chaos needs to be transformed into a chaotic sequence. This transformation is also Rounding errors will be introduced.

In order to solve this problem, we recently proposed an integer domain chaotic system, which specifically refers to a class of chaotic systems that operate on the integer domain. Compared with the existing real number domain chaotic system, its main feature is that it is essentially Solve the problem of dynamic degradation caused by finite precision effects.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies in the prior art and provide an integer domain chaotic circuit.

The technical solution adopted by the present invention to solve the existing technical problems is: an integer domain chaotic circuit, including a uniform noise signal generating circuit (N1), a sample and hold circuit (N2), a decoding circuit (N3), and an iterative circuit (N4) , D/A conversion circuit (N5) five parts, generate 16 digital symbols of 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 Integer domain chaotic signal of , its connection relationship is:

(1) The output terminal A of the uniform noise signal generating circuit (N1) is connected to the input terminal B of the sample and hold circuit (N2);

(2) The output terminal C of the sample-and-hold circuit (N2) is respectively connected to the four input terminals D0, D1, D2, and D3 of the decoding circuit (N3);

(3) The output terminal E0 of the decoding circuit (N3) is connected to the input terminal of the first exclusive OR gate circuit (XOR0) in the iterative circuit (N4), and the output terminal E1 is connected to the input terminal of the second exclusive OR gate circuit (XOR1). The input terminals are connected, the output terminal E2 is connected to the input terminal of the third exclusive OR gate circuit (XOR2), and the output terminal E3 is connected to the input terminal of the fourth exclusive OR gate circuit (XOR3);

(4) The first exclusive OR gate circuit (XOR0), the second exclusive OR gate circuit (XOR1), the third exclusive OR gate circuit (XOR2), and the fourth exclusive OR gate circuit (XOR3) in the iterative circuit (N4) The output end of the D/A conversion circuit (N5) is connected to the input end of DAC1, and the first, second, third, and fourth exclusive OR gate circuits (XOR0, XOR1, XOR2, XOR3) in the iterative circuit (N4) The input end is connected with the input end of DAC2 in the D/A conversion circuit (N5).

By adjusting the comparison voltages of the four comparators (Comparator0, Comparator1, Comparator2, Comparator3) in the decoding circuit (N3) to satisfy 0V, 1V, 2V, and 3V respectively, the circuit generates 0, 1, 2, 3, 4, 5 , 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, a chaotic signal in the integer domain with a total of 16 digital symbols.

Compared with the existing chaotic circuit in the real number field, the invention essentially solves the problem of dynamic degradation caused by the limited precision effect.

Description of drawings

Fig. 1 is the circuit diagram of a kind of integer field chaotic circuit of the present invention;

Fig. 2 is the uniform noise signal generation circuit in the embodiment of the present invention;

Fig. 3 is sample and hold circuit in the embodiment of the present invention;

Fig. 4 is the decoding circuit in the embodiment of the present invention;

Fig. 5 is comparison circuit in the embodiment of the present invention;

Fig. 6 is an iterative circuit in an embodiment of the present invention;

Fig. 7 is the D/A conversion circuit in the embodiment of the present invention;

Fig. 8 is a diagram showing the circuit realization result of the embodiment of the present invention.

The realization of the purpose of the present invention, functional characteristics and advantages will be further described in conjunction with the embodiments and with reference to the accompanying drawings.

detailed description

The technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, so as to understand the essence of the present invention more clearly and intuitively.

As shown in Figure 1, the embodiment of the present invention provides an integer domain chaotic circuit, including a uniform noise signal generation circuit (N1), a sample and hold circuit (N2), a decoding circuit (N3), an iterative circuit (N4), D The /A conversion circuit (N5) has five parts to generate integers with 16 digital symbols of 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, and 15 domain chaotic signal, its connection relation is:

(1) The output terminal A of the uniform noise signal generating circuit (N1) is connected to the input terminal B of the sample and hold circuit (N2);

(2) The output terminal C of the sample-and-hold circuit (N2) is respectively connected to the four input terminals D0, D1, D2, and D3 of the decoding circuit (N3);

(3) The output terminal E0 of the decoding circuit (N3) is connected to the input terminal of the first exclusive OR gate circuit (XOR0) in the iterative circuit (N4), and the output terminal E1 is connected to the input terminal of the second exclusive OR gate circuit (XOR1). The input terminals are connected, the output terminal E2 is connected to the input terminal of the third exclusive OR gate circuit (XOR2), and the output terminal E3 is connected to the input terminal of the fourth exclusive OR gate circuit (XOR3);

(4) The first exclusive OR gate circuit (XOR0), the second exclusive OR gate circuit (XOR1), the third exclusive OR gate circuit (XOR2), and the fourth exclusive OR gate circuit (XOR3) in the iterative circuit (N4) The output end of the D/A conversion circuit (N5) is connected to the input end of DAC1, and the first, second, third, and fourth exclusive OR gate circuits (XOR0, XOR1, XOR2, XOR3) in the iterative circuit (N4) The input end is connected with the input end of DAC2 in the D/A conversion circuit (N5).

By adjusting the comparison voltages of the four comparators (Comparator0, Comparator1, Comparator2, Comparator3) in the decoding circuit (N3) to satisfy 0V, 1V, 2V, and 3V respectively, the circuit generates 0, 1, 2, 3, 4, 5 , 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, a chaotic signal in the integer domain with a total of 16 digital symbols.

As shown in Figure 2, Figure 2 is the uniform noise signal generating circuit N1; the chip MM5837 is a broadband white noise signal generator, which generates white noise signals through a 3dB filter per octave from 10Hz to 40Hz . Noise has a flat uniform distribution across the frequency band from 20Hz to 20kHz. The output is superimposed on the 8.5V DC level of the noise. The component parameters in Figure 1 are: capacitance , , , , . resistance , , , .

Since the output of the uniform noise signal generation circuit N1 shown in Figure 2 is superimposed on the 8.5V DC level Noise, so level conversion is required, and output after conversion for uniform noise signal. Each resistance value in the level shifting circuit is , .

As shown in Figure 3, Figure 3 is a sample and hold circuit N2, the chip model is LF398. The supply voltage is , . Pin 3 in the figure is the analog signal input, pin 5 is the output, and the capacitor , selected in this experiment about. is a square wave signal with a frequency of , the magnitude of the output is , in this experiment the frequency of the square wave is chosen as .

noticed bigger, The lower the frequency can be, the slower the iteration speed will be. Conversely, if smaller, The higher the frequency, the faster the iteration speed. Due to the speed limitation of the device itself, the iteration speed has an upper limit. When doing experiments usually, should have a value of appropriate size, There should also be an appropriate frequency for the circuit to work properly.

As shown in Figure 4 to Figure 5, Figure 4 is the decoding circuit N3, Figure 5 is the comparator circuit in the decoding circuit N3, the parameter value of each resistor is , , , , , the magnitude of the shift level is . According to Figure 5, the logical relationship between the input and output of the comparator is:

Further according to Fig. 4, the input-output relationship of the decoding circuit N3 is:

(1) when hour, ,have to

(1)

(2) when hour, ,have to

(2)

(3) when hour, ,have to

(3)

(4) when hour, ,have to

(4)

Note that the noise at the output of Figure 1 satisfies ,and is an equiprobable distribution (i.e. uniform distribution) in Random signals between. In other words, exist , , , The values in these four intervals are uniformly distributed, and The corresponding relationship between the size of and the four intervals is

(5)

From the above comparison, it can be seen that with Both are random signals with equal probability distribution, and the relationship between them satisfies:

(6)

Assume , the iterative equation of the basic IDCS is

(7)

In the formula .

By comparing formulas (1) to (7), another equivalent mathematical expression of formula (7) is obtained as follows:

According to (8), the circuit design diagram corresponding to the iterative equation is shown in Figure 6.

As shown in Figure 7, Figure 7 is a D/A conversion circuit N5, wherein , , ,

. The chip of D/A conversion circuit N5 is DAC0832, which should be designed as a direct mode, that is, as long as a four-digit binary number is input , which can be immediately converted into the corresponding integer signal . The logical correspondence is: when the input is When , the corresponding D/A converter output is , when the input is , the corresponding output is , when the input is , the corresponding output is ,..., when the input is , the corresponding output is , adjust the resistance The size of can achieve this correspondence.

Combining Figures 2 to 7, the result of the overall circuit design of IDCS is shown in Figure 8. According to Figure 8, by adjusting the comparison voltages of the four comparators Comparator0, Comparator1, Comparator2, and Comparator3 in the decoding circuit N3 to meet 0V, 1V, 2V, and 3V respectively, the circuit generates 0, 1, 2, 3, 4, 5 , 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, a chaotic signal in the integer domain with a total of 16 digital symbols. The circuit realization result is shown in Fig. 8 .

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the description of the present invention and the contents of the accompanying drawings, or directly or indirectly used in other related All technical fields are equally included in the scope of patent protection of the present invention.

Claims (1)

1. a kind of integer field chaos circuit, it is characterised in that：Including Uniform noise signal generating circuit (N1), sampling hold circuit (N2), decoding circuit (N3), iterative circuit (N4), five parts of D/A change-over circuits (N5), produce 0,1,2,3,4,5,6,7,8, 9th, the integer field chaotic signal of 10,11,12,13,14,15 totally 16 numerical chracters, its annexation is：

(1) output terminals A of the Uniform noise signal generating circuit (N1) is connected with the input B of sampling hold circuit (N2)；

(2) four inputs D0, D1, D2, the D3 of the output end C of the sampling hold circuit (N2) respectively with decoding circuit (N3) It is connected；

(3) the output end E0 of the decoding circuit (N3) and the first NOR gate circuit (XOR0) in iterative circuit (N4) input It is connected, output end E1 is connected with the input of the second NOR gate circuit (XOR1), output end E2 and the 3rd NOR gate circuit (XOR2) input is connected, and output end E3 is connected with the input of the 4th NOR gate circuit (XOR3)；

(4) the first NOR gate circuit (XOR0), the second NOR gate circuit (XOR1), the 3rd XOR gate in the iterative circuit (N4) Circuit (XOR2), the output end of the 4th NOR gate circuit (XOR3) are connected with the input of DAC1 in D/A change-over circuits (N5), repeatedly For the first NOR gate circuit (XOR0), the second NOR gate circuit (XOR1), the 3rd NOR gate circuit (XOR2), in circuit (N4) The input of four NOR gate circuits (XOR3) is connected with the input of DAC2 in D/A change-over circuits (N5)；

By adjust in the decoding circuit (N3) four comparator Comparator0, Comparator1, Comparator2, Comparator3 comparison voltage, when meeting 0V, 1V, 2V, 3V respectively, the integer field chaos circuit produces 0,1,2,3,4, 5th, the integer field chaotic signal of 6,7,8,9,10,11,12,13,14,15 totally 16 numerical chracters；

The Uniform noise signal generating circuit (N1), chip MM5837 is broadband white noise signal generator, is arrived by 10Hz 40Hz every octave 3dB wave filters, produce white noise signal ξ (t)；Noise has flat from 20Hz to 20kHz in whole frequency range Smooth is uniformly distributed；Output is superimposed upon the 1V in 8.5V DC levels_P-PNoise；

The output ξ (t) of the Uniform noise signal generating circuit (N1) is the 1V being superimposed upon in 8.5V DC levels_P-PNoise, therefore Need to carry out level conversion, by exporting Uniform noise signals of the η (t) into 0~4V after changing；It is each in level shifting circuit Individual resistance value is R₅=R₆=R₈=R₉=10k Ω, R₇=40k Ω；

The sampling hold circuit (N2), chip model is LF398；Supply voltage is V₊=+15V, V_-=-15V；3 pin are simulation Signal is inputted, and 5 pin are output, electric capacity C_F=0.01~0.1 μ F；

Comparator circuit in the decoding circuit (N3), decoding circuit (N3), the parameter value of each resistance is R₁₀=13.5k Ω, R₁₁=1k Ω, R₁₂=10k Ω, R₁₃=40k Ω, R₁₄=R₁₅=R₁₆=10k Ω, the size of shift levels is E=4V；Than Logical relation compared with device input and output is：

$\left\{\begin{array}{cccc}if& \mathrm{\&eta;}\left(n\right)>U_1,& then& {\mathrm{\&eta;}}_1=1\\ if& \mathrm{\&eta;}\left(n\right)<U_i,& then& {\mathrm{\&eta;}}_i=0\end{array}\right.$

Further obtaining decoding circuit (N3) input/output relation is：

(1) 3V is worked as<During η (t)≤4V, η₃=η₂=η₁=η₀=1, obtain

$\left\{\begin{array}{c}{s}_3^n={\mathrm{\&eta;}}_3=1\\ s_2^n={\mathrm{\&eta;}}_3\&CirclePlus;{\mathrm{\&eta;}}_2=1\&CirclePlus;1=0\\ s_1^n={\mathrm{\&eta;}}_2\&CirclePlus;{\mathrm{\&eta;}}_1=1\&CirclePlus;1=0\\ s_0^n={\mathrm{\&eta;}}_1\&CirclePlus;{\mathrm{\&eta;}}_0=1\&CirclePlus;1=0\end{array}\right.---\left(1\right)$

(2) 2V is worked as<During η (t)≤3V, η₃=0, η₂=η₁=η₀=1, obtain

$\left\{\begin{array}{c}{s}_3^n={\mathrm{\&eta;}}_3=0\\ s_2^n={\mathrm{\&eta;}}_3\&CirclePlus;{\mathrm{\&eta;}}_2=0\&CirclePlus;1=1\\ s_1^n={\mathrm{\&eta;}}_2\&CirclePlus;{\mathrm{\&eta;}}_1=1\&CirclePlus;1=0\\ s_0^n={\mathrm{\&eta;}}_1\&CirclePlus;{\mathrm{\&eta;}}_0=1\&CirclePlus;1=0\end{array}\right.---\left(2\right)$

(3) 1V is worked as<During η (t)≤2V, η₃=η₂=0, η₁=η₀=1, obtain

$\left\{\begin{array}{c}{s}_3^n={\mathrm{\&eta;}}_3=0\\ s_2^n={\mathrm{\&eta;}}_3\&CirclePlus;{\mathrm{\&eta;}}_2=0\&CirclePlus;0=0\\ s_1^n={\mathrm{\&eta;}}_2\&CirclePlus;{\mathrm{\&eta;}}_1=0\&CirclePlus;1=1\\ s_0^n={\mathrm{\&eta;}}_1\&CirclePlus;{\mathrm{\&eta;}}_0=1\&CirclePlus;1=0\end{array}\right.---\left(3\right)$

(4) as 0V≤η (t)≤1V, η₃=η₂=η₁=0, η₀=1, obtain

$\left\{\begin{array}{c}{s}_3^n={\mathrm{\&eta;}}_3=0\\ s_2^n={\mathrm{\&eta;}}_3\&CirclePlus;{\mathrm{\&eta;}}_2=0\&CirclePlus;0=0\\ s_1^n={\mathrm{\&eta;}}_2\&CirclePlus;{\mathrm{\&eta;}}_1=0\&CirclePlus;0=0\\ s_0^n={\mathrm{\&eta;}}_1\&CirclePlus;{\mathrm{\&eta;}}_0=0\&CirclePlus;1=1\end{array}\right.---\left(4\right)$

When the noise of output meets 0V≤η (t)≤4V, and η (t) is the random letter that a grade is generally distributed between [0V, 4V] Number, and sⁿSize and four interval corresponding relations be

$\left\{\begin{array}{cccc}if& \mathrm{\&eta;}\left(t\right)\&Element;\&lsqb;0V,1V),& then& s^n=0\\ if& \mathrm{\&eta;}\left(t\right)\&Element;\&lsqb;1V,2V),& then& s^n=1\\ if& \mathrm{\&eta;}\left(t\right)\&Element;\&lsqb;2V,3V),& then& s^n=2\\ if& \mathrm{\&eta;}\left(t\right)\&Element;\&lsqb;3V,4V\&rsqb;,& then& s^n=3\end{array}\right.---\left(5\right)$

Pass through above-mentioned comparison, it is known that s_nWithAll it is to wait the random signal being generally distributed, relation between the two is met：

$\left\{\begin{array}{cccc}if& \mathrm{\&eta;}\left(t\right)\&Element;\&lsqb;0V,1V),& then& s^n=0\&DoubleLeftRightArrow;s_3^n{s}_2^n{s}_1^n{s}_0^n=0001\\ if& \mathrm{\&eta;}\left(t\right)\&Element;\&lsqb;1V,2V),& then& s^n=1\&DoubleLeftRightArrow;s_3^n{s}_2^n{s}_1^n{s}_0^n=0010\\ if& \mathrm{\&eta;}\left(t\right)\&Element;\&lsqb;2V,3V),& then& s^n=2\&DoubleLeftRightArrow;s_3^n{s}_2^n{s}_1^n{s}_0^n=0100\\ if& \mathrm{\&eta;}\left(t\right)\&Element;\&lsqb;3V,4V\&rsqb;,& then& s^n=3\&DoubleLeftRightArrow;s_3^n{s}_2^n{s}_1^n{s}_0^n=1000\end{array}\right.---\left(6\right)$

If N=4, the iterative equation for obtaining basic IDCS is

$\left\{\begin{array}{c}{x}_i^n=\left\{\begin{array}{ccc}{x}_i^{n-1}& if& i\&NotEqual;s^n\\ {\left(f\right(x^{n-1}\left)\right)}_i=\stackrel{\&OverBar;}{x_i^{n-1}}& if& i=s^n\end{array}\right.\\ i=0,1,2,3\end{array}\right.---\left(7\right)$

S in formulaⁿ∈ { 0,1,2, LN-1 }={ 0,1,2,3 }；

By comparing (1)~(7) formula, another mathematic(al) representation of equal value for further obtaining (7) formula is as follows：

$\left\{\begin{array}{c}{s}^n=0\&DoubleLeftRightArrow;s_3^n{s}_2^n{s}_1^n{s}_0^n=0001\\ s^n=1\&DoubleLeftRightArrow;s_3^n{s}_2^n{s}_1^n{s}_0^n=0010\\ s^n=2\&DoubleLeftRightArrow;s_3^n{s}_2^n{s}_1^n{s}_0^n=0100\\ s^n=3\&DoubleLeftRightArrow;s_3^n{s}_2^n{s}_1^n{s}_0^n=1000\end{array}\right.\&DoubleRightArrow;\left\{\begin{array}{c}{x}_i^n=\left\{\begin{array}{ccc}{x}_i^{n-1}& if& i\&NotEqual;s^n\\ {\left(f\right(x^{n-1}\left)\right)}_i=\stackrel{\&OverBar;}{x_i^{n-1}}& if& i=s^n\end{array}\right.\\ i=0,1,2,3\end{array}\right.\&DoubleLeftRightArrow;\left\{\begin{array}{c}{x}_3^n=x_3^{n-1}\&CirclePlus;s_3^n\\ x_2^n=x_2^{n-1}\&CirclePlus;s_2^n\\ x_1^n=x_1^{n-1}\&CirclePlus;s_1^n\\ x_0^n=x_0^{n-1}\&CirclePlus;s_0^n\end{array}\right.---\left(8\right)$

According to (8) formula, the circuit design drawing of iterative equation must be corresponded to；

The D/A change-over circuits (N5), wherein R₁₇=10k Ω, R₁₈=2k Ω, R₁₉=60k Ω, R₂₀=R₂₁=10k Ω；D/A turns The chip for changing circuit (N5) is DAC0832, is designed into for a direct mode operation, that is, simply entering a tetradCorresponding integer signal x can be just converted at onceⁿ；Logic corresponding relation is：When input isWhen, correspondence D/A converter is output as xⁿ=0V, when input isWhen, it is corresponding defeated Go out for xⁿ=1V, when input isWhen, it is corresponding to be output as xⁿ=2V ... ..., when input isWhen, it is corresponding to be output as xⁿ=15V, regulation resistance R₁₉Size realize this corresponding relation；

The IDCS way circuits design drawing by adjust in decoding circuit (N3) four comparator Comparator0, Comparator1, Comparator2, Comparator3 comparison voltage, when meeting 0V, 1V, 2V, 3V respectively, the integer Domain chaos circuit produces the integer field chaos of 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15 totally 16 numerical chracters Signal.