CN112953507A

CN112953507A - Physical unclonable function circuit based on level converter and control method thereof

Info

Publication number: CN112953507A
Application number: CN202110294320.2A
Authority: CN
Inventors: 曹元�; 韩丽娟; 李江海; 钱文卫; 钱文晶
Original assignee: Changzhou Walson Electronics Research Institute Co ltd
Current assignee: Changzhou Walson Electronics Research Institute Co ltd
Priority date: 2021-03-19
Filing date: 2021-03-19
Publication date: 2021-06-11

Abstract

The invention provides a physical unclonable function circuit based on a level shifter and a control method thereof, wherein the circuit comprises: the PUF output mode control module is used for outputting a PUF output mode control signal according to the control signal; and the mode switching module is connected with the mode control module, and is used for shifting and converting the input signal into a power supply level signal of a second voltage and outputting the power supply level signal from the output end when receiving the level conversion mode control signal and the input signal of the input end is a logic signal of a first voltage, and outputting a level signal of '0' or '1' from the output end to generate a physical unclonable random number when receiving the PUF output mode control signal, wherein the first voltage is less than the second voltage. The circuit allows the working mode to be switched between the level shifter and the PUF, can be improved on the basis of the level shifter circuit, and is simple in structure.

Description

Physical unclonable function circuit based on level converter and control method thereof

Technical Field

The invention relates to the technical field of electricity, in particular to a physical unclonable function circuit based on a level shifter and a control method of the physical unclonable function circuit based on the level shifter.

Background

In the era of the internet of things, security and privacy have attracted a great deal of attention. Challenges facing the implementation of security functions on internet of things devices with limited resources have prompted researchers to develop more advanced and lightweight solutions.

Physical Unclonable Functions (PUFs) are used as emerging lightweight hardware to protect management keys and verify device security, and are increasingly applied to devices in the internet of things beyond traditional cryptographic algorithms that store secret key information in a non-volatile memory (NVM).

In addition, in the design of an electronic circuit of a new generation of internet of things equipment, with the introduction of low-voltage logic, the problem of inconsistent input/output logic often occurs inside a system, so that the complexity of the system design is improved. For example, when a 1.8V digital circuit communicates with an analog circuit operating at 3.3V, the problem of two-level conversion needs to be solved first, and a level shifter is needed.

In the related art, a level shifter and a PUF circuit are generally used to implement a level shift function and a PUF function, respectively. This will undoubtedly increase the hardware and structural complexity of the internet of things devices.

Disclosure of Invention

The present invention has been made to solve the above-mentioned problems, and a first object of the present invention is to provide a level shifter-based physically unclonable function circuit, which allows an operation mode to be switched between a level shifter (differential mode input) and a PUF (common mode input), and can be improved on the basis of a level shifter circuit, and has a simple structure, that is, the level shifter and the PUF functions can be implemented by a simple circuit, thereby improving the integration of the related device.

A second object of the present invention is to provide a method for controlling a physically unclonable function circuit of a level shifter.

The technical scheme adopted by the invention is as follows:

an embodiment of the first aspect of the present invention provides a level shifter-based physically unclonable function circuit, including: the PUF output module is used for outputting a PUF output mode control signal according to the control signal; the mode switching module is connected with the mode control module and used for shifting and converting the input signal into a power supply level signal of a second voltage and outputting the power supply level signal from an output end when the input signal of an input end is a logic signal of a first voltage when the level conversion mode control signal is received, and outputting a level signal of '0' or '1' from the output end when the PUF output mode control signal is received so as to generate a random number which is physically unclonable, wherein the first voltage is less than the second voltage.

The level shifter-based physically unclonable function circuit proposed by the present invention as described above may further have the following additional technical features:

according to one embodiment of the invention, the mode control module comprises: the control electrode of the first NMOS tube is used for receiving the control signal, the first electrode of the first NMOS tube is connected with the input end, and the second electrode of the first NMOS tube is connected with the inverting input end.

According to an embodiment of the invention, the turn-on voltage of the first NMOS transistor is 0.3V to 0.4V.

According to one embodiment of the invention, the mode switching module comprises: the control electrode of the second NMOS tube is used as an input end, and the breakover voltage of the second NMOS tube is a first voltage; the control electrode of the third NMOS tube is used as the inverting input end; the input end of the first phase inverter is connected with the substrate lead of the second NMOS tube, the output end of the first phase inverter is connected with the substrate lead of the third NMOS tube, and the power supply end of the first phase inverter is connected with the power supply level signal of the first voltage; the cross-coupled PMOS pair comprises a first PMOS tube and a second PMOS tube, a first pole of the first PMOS tube is connected with a first pole of the second PMOS tube and then connected with a power supply level signal of a second voltage, a second pole of the first PMOS tube is connected with a control pole of the second PMOS tube and then connected with a first pole of a second NMOS tube, a second pole of the second NMOS tube is grounded, a second pole of the second PMOS tube is connected with a control pole of the first PMOS tube and then connected with a first pole of a third NMOS tube, and a second pole of the third NMOS tube is grounded; the input end of the second phase inverter is connected with the first pole of the second NMOS tube, the output end of the second phase inverter is used as the output end, and the power supply end of the second phase inverter is connected with a power supply level signal of the second voltage; and the input end of the third phase inverter is connected with the first pole of the third NMOS tube, the output end of the third phase inverter is used as the inverted output end, and the power supply end of the third phase inverter is connected with the power supply level signal of the second voltage.

According to an embodiment of the present invention, when the control signal received by the control electrode of the first NMOS transistor is a low level signal, the mode switching module shifts and converts the input signal into a power level signal of a second voltage and outputs the power level signal from the output terminal; when the control signal received by the control electrode of the first NMOS tube is a high level signal, the mode switching module outputs the level signal of '0' or '1' from the output end to generate the physical unclonable random number.

An embodiment of the second aspect of the present invention provides a control method for a level shifter-based physically unclonable function circuit, including the following steps: receiving a control signal and sending a mode control signal according to the control signal, wherein the mode control signal comprises a level conversion mode control signal and a PUF output mode control signal; when the level conversion mode control signal is received and an input signal of an input end is a logic signal of a first voltage, the input signal is shifted and converted into a power supply level signal of a second voltage and the power supply level signal is output from an output end; outputting a level signal of "0" or "1" from the output terminal to generate a physically unclonable random number upon receiving the PUF output pattern control signal, wherein the first voltage is smaller than the second voltage.

The invention has the beneficial effects that:

the invention allows the working mode to be switched between the level shifter (differential mode input) and the PUF (common mode input), can be improved on the basis of a level shifter circuit, has simple structure, namely, the level shifter and the PUF can be realized by a simple circuit, and the integration of related equipment is improved.

Drawings

FIG. 1 is a block schematic diagram of a level shifter based physically unclonable function circuit according to one embodiment of the invention;

FIG. 2 is a circuit topology diagram of a level shifter based physically unclonable function circuit according to one embodiment of the present invention;

FIG. 3 is a circuit schematic of a second inverter A2 and a third inverter A3 according to one embodiment of the invention;

FIG. 4 is a circuit schematic of a first inverter A1 according to one embodiment of the present invention;

FIG. 5 is a waveform diagram of the output of the circuit shown in FIG. 2;

FIG. 6 is a schematic diagram of simulated waveforms for a level shifter according to one specific example of the present invention;

FIG. 7 is a schematic illustration of an inter-chip Hamming distance distribution according to a specific example of the present invention;

FIG. 8 is a graph illustrating BER over a range of temperatures, according to one specific example of the present invention;

FIG. 9 is a graph of BER over a range of supply voltages, according to a specific example of the present invention;

FIG. 10 is a graphical illustration of autocorrelation test results in accordance with one particular example of the present invention; .

Fig. 11 is a graph of power consumption and energy consumption at different bit rates according to a specific example of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

FIG. 1 is a block schematic diagram of a level shifter based physically unclonable function circuit, according to one embodiment of the invention. As shown in fig. 1, the circuit includes: the device comprises a mode control module 1 and a mode switching module 2.

The mode control module 1 is configured to receive a control signal Vctr and send a mode control signal according to the control signal, where the mode control signal includes a level conversion mode control signal and a PUF output mode control signal; the mode switching module 2 is connected to the mode control module 1, and the mode switching module 2 is configured to shift and convert an input signal into a power level signal of a second voltage and output the power level signal from the output end out when the input signal at the input end in is a logic signal of a first voltage when receiving a level conversion mode control signal, and output a level signal of "0" or "1" from the output end when receiving a PUF output mode control signal to generate a physically unclonable random number, where the first voltage is smaller than the second voltage.

Specifically, the operating mode of the circuit can be switched by changing the control signal received by the mode control module 1 according to actual requirements. When the mode switching module 2 receives the level shift mode control signal, the mode switching module 2 may shift and convert the low input voltage logic signal into a higher power supply level signal. When the mode switching module 2 receives the PUF output mode control signal, it may output a level signal of "0" or "1" based on the random uncertainty that the circuit node metastable state causes the PMOS transistor pair to be turned on in sequence, thereby generating a physical unclonable random number. And the mode switching module 2 is improved on the basis of the level shifter. Therefore, the circuit allows the working mode to be switched between the level shifter (differential mode input) and the PUF (common mode input), can be improved on the basis of the level shifter circuit, has a simple structure, namely the level shifter and the PUF can be realized through a simple circuit, and improves the integration of related equipment.

According to an embodiment of the present invention, as shown in fig. 2, the mode control module 1 may include: a first NMOS transistor N1, a control electrode of the first NMOS transistor N1 being a signal receiving terminal, a control electrode of the first NMOS transistor N1 being configured to receive a control signal Vctr, a first electrode of the first NMOS transistor N1 being connected to the input terminal in, a second electrode of the first NMOS transistor N1 being connected to the inverting input terminal in

Are connected. The control signal Vctr may be a high level signal or a low level signal.

According to an embodiment of the invention, the turn-on voltage of the first NMOS transistor N1 may be 0.3V to 0.4V.

Specifically, the first NMOS transistor N1 may employ a low threshold device to attenuate the voltage drop formed by the transmission resistance of the first NMOS transistor N1, so that the input in and the inverting input terminal are connected

The signals are extremely symmetrical, and the output reliability of the PUF can be effectively improved.

According to an embodiment of the present invention, as shown in fig. 2, the mode switching module 2 may include: a second NMOS transistor N2, a third NMOS transistor N3, a first inverter A1, a cross-coupled PMOS pair, a second inverter A2 and a third inverter A3, wherein the cross-coupled PMOS pair comprises a first PMOS transistor P1 and a second PMOS transistor P2,

a control electrode of the second NMOS transistor N2 is used as an input terminal in, and the turn-on voltage of the second NMOS transistor N2 is a first voltage; the control electrode of the third NMOS transistor N3 is used as an inverting input end

The input end of the first phase inverter A1 is connected with the substrate lead of the second NMOS transistor, the output end of the first phase inverter A1 is connected with the substrate lead of the third NMOS transistor N3, and the first phase inversionThe power supply terminal of the device a1 is connected to a power supply level signal VDDL of a first voltage; the cross-coupled PMOS pair comprises a first PMOS pipe P1 and a second PMOS pipe P2, a first pole of the first PMOS pipe P1 is connected with a first pole of the second PMOS pipe P2 and then connected with a power supply level signal VDDH of a second voltage, a second pole of the first PMOS pipe P1 is connected with a control pole of the second PMOS pipe P2 and then connected with a first pole of a second NMOS pipe N2, a second pole of the second NMOS pipe N2 is grounded, a second pole of the second PMOS pipe P2 is connected with a control pole of the first PMOS pipe P1 and then connected with a first pole of a third NMOS pipe N3, and a second pole of the third NMOS pipe N3 is grounded; the input end of the second inverter a2 is connected to the first pole of the second NMOS transistor N2, the output end of the second inverter a2 serves as the output end out, and the power supply end of the second inverter a2 is connected to the power supply level signal VDDH of the second voltage; the input end of the third inverter A3 is connected with the first pole of the third NMOS transistor N3, and the output end of the third inverter A3 is used as the inverted output end

A power source terminal of the third inverter is connected to a power source level signal VDDH of the second voltage.

Specifically, as shown in fig. 2, a first node a exists between the second pole of P1, the input terminal of a2, and the first pole of N2, a second node B exists between the second pole of P2, the input terminal of A3, and the first pole of N3, and the second NMOS transistor N2 may be a low-threshold device. In the level conversion mode, the Vctr end is at a low level, when the input end "in" is at a high level, the N1 is turned off, the N2 and the P2 are turned on, and the N3 and the P1 are turned off, and due to the positive feedback effect of the cross-coupled PMOS on the P1 and the P2 transistors, the low input voltage "in" end (the logic high of which is V DDL) can output the high level of VDDH at the node B, so that the logic high level is shifted from VDDL to VDDH. Subsequently, if the low input voltage "in" terminal goes low, then N3 and P1 will be activated, thereby causing the output of node B to be pulled low. Thus, a level shifter with a differential common-source voltage logic gate may convert a low input voltage logic signal to a higher supply level signal.

In the PUF mode, the Vctr end is at high level, when the input end ' in ' is at low level, N1 is conducted, and the input end ' in ' is opposite to the input end ' inTo the input end

The same is low and N2 and N3 are off, which will place nodes A and B in a metastable state. Depending on the conduction current between N2 and N3, the level states of nodes a and B may latch the supply Voltage (VDDH) or Ground (GND), i.e., the levels of nodes a and B may be high or low. When the input terminal in is raised from a low level to a high level, N2 and N3 are theoretically turned on, and thus the voltages at the nodes a and B will fall simultaneously. However, due to the change of conduction of the N2 tube and the N3 tube, the current I flows due to conduction₁And I₂Slightly different, causing P1 or P2 to be activated faster than the other, which in turn causes positive feedback to promote the output response to settle to '0' or '1'.

In the present invention, the main entropy sources of the PUF are from the NMOS transistor pair (N2, N3). Optimizing the size of the NMOS transistor pair may reduce power consumption, area, and increase randomness due to process variations. In addition, to avoid the effect of imbalance on the PUF output, an inverter may be added at both nodes A, B as a buffer. Meanwhile, N1 employs low threshold devices to attenuate the voltage drop created by the transmission resistance of N1, making the input "in" and the inverting input

In the design of very large scale integrated circuit, a level shifter is used for connecting signals between different power domains, and since the power consumption of the circuit is proportional to the square of the current, the method for reducing the power consumption by optimizing the working current of the circuit unit under different voltages is very effective. As shown in fig. 2, the overhead unique to each response bit of the level shifter circuit is the overhead of turning on a single NMOS rectifier and allowing the operating mode of the circuit to be switched between the level shifter (differential mode input) and the PUF (common mode input).

In the present invention, the circuit schematic diagram of the second inverter a2 and the third inverter A3 (i.e. the inverter with logic high level VDDH) can be referred to fig. 3, where MP3 is PMOS, MN3 is PMOS; referring to fig. 4, a circuit diagram of the first inverter a1 (i.e., an inverter with logic high level VDDL) is shown, where MP4 is PMOS and MN4 is PMOS. The output waveform diagram of the circuit shown in fig. 2 can be referred to fig. 5.

And (3) experimental verification:

the performance of the above proposed level shifter-based physically unclonable function circuit of the present invention in terms of PUF uniqueness, reliability, randomness, speed, power consumption, etc. will be introduced and analyzed experimentally. The proposed PUF was simulated by Cadence Virtuoso Spectre under a commercial 65nm CMOS process. The collected data was further processed by MATLAB scripts.

The transfer characteristic of the level shifting function is first verified before testing the performance of the PUF. As shown in fig. 6, a simulated waveform diagram of converting an input signal of 20MHz and 0.6V into 1.2V shows that the present invention can well convert a sub-threshold voltage into a standard voltage, Vin represents an input signal, Vout represents an output signal, and tone represents time.

The uniqueness, reliability, randomness, speed and power consumption of the PUF function are verified below.

1. Uniqueness of

The uniqueness measure the degree of difference between CRP (excitation response pairs) produced by different PUF examples, estimated by the average inter-chip Hamming Distance (HD). The uniqueness U of the PUF is represented as follows:

where m is the total number of PUF devices, Ru and Rv are the random output bit streams of two different PUF devices with the same stimulus C, and n is the bit length, where n is 128.

Ideally, the uniqueness of a PUF should be 50%, which means that PUF instances can be completely distinguished and have the largest decorrelation. Under nominal conditions (1.2V, 27 ℃), 1000 iterations of MC simulations were performed to evaluate the uniqueness of the PUF. Fig. 7 shows the HD distribution of the proposed PUF, Count represents the number of PUFs at a certain hamming distance, Histogram represents and Fitted represents the fit value. A gaussian distribution curve with a mean value of 49.11% and a standard deviation of 4.42% fits well.

2. Reliability of

Another characteristic of PUFs is reliability, which evaluates whether a CRP generated by one PUF under the same stimulus is stable under different operating conditions (e.g., different supply voltages, temperatures, etc.), usually expressed in terms of Bit Error Rate (BER). BER refers to the percentage of the number of erroneous bits in the generated bit stream relative to the total number of bits. The reliability S is typically calculated as follows:

where Ri is the response of random excitation C under nominal conditions (1.2V, 27 ℃). Ri, j is the response at different operating conditions, the same stimulus C. k is the number of times the same stimulus C evaluates the same PUF. An ideal PUF must have 100% reliability.

The reliability of the PUF was evaluated by BER (temperature range-20 ℃ C. -100 ℃ C., power supply voltage range 1.0V-1.5V) under different conditions. 1000 CRPs were collected under each condition to calculate reliability. Fig. 8 and 9 plot the simulation results with the worst case reliability at 100 c and 1.0V. The normalized BER per 10 ℃ and 0.1V was 1.98% and 2.2%, respectively.

3. Randomness property

Randomness is estimated as the uncertainty or unpredictability of the CRP generated by the PUF. A good PUF has high randomness, which means that it is difficult for an attacker to predict successfully with a small number of CRPs collected. To assess randomness, the National Institute of Standards and Technology (NIST) randomness test and autocorrelation test were performed.

1) NIST randomness test: the NIST SP800 statistical test suite is an important test suite for randomness analysis. 10000 raw PUF response bits were collected in the experiment and table 1 shows the NIST test results. The P-values are used to measure the degree of randomness and all P-values should be greater than 0.01 to achieve 99% confidence in any random source. As can be seen from the table, the PUF passes all NIST tests (other items not shown are not performed due to the limited length of the bitstream), which means that the PUF generates a random bit sequence with high randomness.

2) And (3) self-correlation testing: autocorrelation is the cross-correlation of a signal with itself at different points in time. An autocorrelation function (ACF) may be used to compute the autocorrelation of a random bit sequence to determine whether it is independent and uniformly distributed. Figure 10 shows the results of the 50000CRP ACF test with a confidence interval of ± 0.0089 at a confidence level of 95%, with the lower limit demonstrating the vulnerability to correlation power analysis and the lang Length representing the hysteresis Length.

4. Speed and power

To further evaluate the performance of the new PUF designed, its power consumption and bit rate were measured. Fig. 11 shows the relationship between power consumption, power consumption per bit and bit rate at 27 c and 1.2V. In the design, the maximum bit rate for enabling both working modes to operate normally is 20Mbps, the power consumption is 14.39W, and the power consumption per bit is 0.72 pJ/b.

5. Performance comparison

The PUF performance proposed herein is compared to the latest weak PUF design in table 2. Compared to several PUFs based on existing hardware resources, we can conclude that the PUF proposed herein is significantly better than other PUFs in terms of reliability and uniqueness over the temperature and supply voltage range. Compared to the structure in ISCS' 19[6], the proposed PUF has a 1% reduction in energy consumption per bit (0.72pJ) and a higher operating frequency of 20 MHz. In addition to this, it is most important to note that this is the first time we have successfully used the idea of a level shifter to create a weak PUF pattern. In the designed PUF structure based on the cross-coupled level converter, the cost of each response bit is only a single NMOS transistor and can be ignored in the overall layout, so that the proposed design has the characteristics of low energy consumption and low cost of each response bit.

6. Conclusion

A high performance, low overhead weak PUF circuit structure is presented, which is the first time entropy is extracted from commercial level shifter designs. Based on the original level translator circuit, the NMOS switch transistor is the only overhead of each response bit when the PUF works, and the NMOS switch transistor enables the existing cross-coupling level translator circuit to be easily switched between a differential mode and a common mode. The proposed PUF cell extracts entropy by exploiting the intrinsic process variation of the two NMOS transistors controlled by the common-mode signal, resulting in a random response sequence, and performs MC simulation using a standard 65nm CMOS process with 49.11% uniqueness. In the worst case, the reliability is 95.31% and 96.09% in the temperature range of-20 ℃ to 100 ℃ and the power supply voltage range of 1.0V to 1.5V, respectively. The maximum bit rate and the optimal energy consumption per bit are 20Mbps and 0.72 pJ/b. The design can be improved on the original level converter circuit, and the low cost and low energy efficiency of only one additional NMOS transistor per bit make the design a promising hardware security primitive of the Internet of things equipment.

From the foregoing, it can be seen that the present invention extracts difference information from the process variations inherent in cross-coupled level shifters (CCLS) in existing integrated circuit chips. CCLS can convert voltages between different levels to allow different circuit blocks to operate in different power domains with optimized energy efficiency. In the circuit of the present invention, a single switching transistor is embedded in the level shifter, i.e., the only overhead for each response bit to change the operating mode of the CCLS from differential to common mode. By exploiting the uncertainty of the output voltage due to the different switching times of the two PMOS in the cross-coupled network, the serial number of the PUF can be extracted at common mode effects. The standard 65-nanometer CMOS simulation process is used, and experiments show that the PUF circuit can generate serial number uniqueness of 49.11%, reliability of 96.09%, power supply voltage of 1.0-1.5V, and temperature fluctuation of 95.31% between-20 ℃ and 100 ℃. At 20Mbps, 1.2V, high load of 27 ℃, the energy per bit is only 0.72 pJ/b.

In summary, according to the physically unclonable function circuit based on the level shifter in the embodiment of the present invention, the operation mode is allowed to be switched between the level shifter (differential mode input) and the PUF (common mode input), and the circuit can be improved on the basis of the level shifter circuit, the structure is simple, that is, the level shifter and the PUF function can be implemented by a simple circuit, the integration of the related device is improved, and experiments prove that when the circuit is operated in the level shifter mode, the subthreshold voltage can be well converted into the standard voltage, and when the circuit is operated in the PUF output mode, the circuit has better performances in terms of PUF uniqueness, reliability, randomness, speed, power consumption and the like.

Based on the physical unclonable function circuit based on the level shifter, the invention also provides a control method of the physical unclonable function circuit based on the level shifter. Since the control method of the present invention is based on the above circuit, details that are not disclosed in the method can refer to the above circuit embodiment, and are not described in detail in the present invention.

The control method of the physical unclonable function circuit based on the level converter, which is implemented according to the invention, comprises the following steps:

and S1, receiving the control signal and sending out a mode control signal according to the control signal, wherein the mode control signal comprises a level conversion mode control signal and a PUF output mode control signal.

S2, when the level shift mode control signal is received and the input signal at the input terminal is a logic signal of the first voltage, the level shift mode control signal shifts and converts the input signal into a power supply level signal of the second voltage and outputs the power supply level signal from the output terminal.

And S3, outputting a level signal of '0' or '1' from the output terminal to generate a physically unclonable random number when receiving the PUF output mode control signal, wherein the first voltage is less than the second voltage.

According to the control method of the physical unclonable function circuit based on the level converter, the working mode is allowed to be switched between the level converter (differential mode input) and the PUF (common mode input), improvement can be performed on the basis of the level converter circuit, the structure is simple, namely the level converter and the PUF function can be realized through a simple circuit, and the integration of related equipment is improved.

In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. The meaning of "plurality" is two or more unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the first feature "on" or "under" the second feature may be directly contacting the first and second features or indirectly contacting the first and second features through an intermediate. Also, a first feature "on," "over," and "above" a second feature may be directly or diagonally above the second feature, or may simply indicate that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lesser elevation than the second feature.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction. In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.

The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.

It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.

In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.

The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that changes, modifications, substitutions and alterations can be made in these embodiments without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.

Claims

1. A level shifter based physically unclonable function circuit, comprising:

the PUF output module is used for outputting a PUF output mode control signal according to the control signal;

the mode switching module is connected with the mode control module and used for shifting and converting the input signal into a power supply level signal of a second voltage and outputting the power supply level signal from an output end when the input signal of an input end is a logic signal of a first voltage when the level conversion mode control signal is received, and outputting a level signal of '0' or '1' from the output end when the PUF output mode control signal is received so as to generate a random number which is physically unclonable, wherein the first voltage is less than the second voltage.

2. The level-shifter based physically unclonable function circuit of claim 1, wherein the mode control module comprises:

the control electrode of the first NMOS tube is used for receiving the control signal, the first electrode of the first NMOS tube is connected with the input end, and the second electrode of the first NMOS tube is connected with the inverting input end.

3. The level shifter based physical unclonable function circuit of claim 1, wherein the first NMOS transistor has a turn-on voltage of 0.3V to 0.4V.

4. The level-shifter based physically unclonable function circuit of claim 2, wherein the mode switching module comprises:

the control electrode of the second NMOS tube is used as an input end, and the breakover voltage of the second NMOS tube is a first voltage;

a control electrode of the third NMOS tube is used as the inverting input end;

the input end of the first phase inverter is connected with the substrate lead of the second NMOS tube, the output end of the first phase inverter is connected with the substrate lead of the third NMOS tube, and the power supply end of the first phase inverter is connected with the power supply level signal of the first voltage;

the cross-coupled PMOS pair comprises a first PMOS tube and a second PMOS tube, a first pole of the first PMOS tube is connected with a second pole of the first PMOS tube and then connected with a power supply level signal of a second voltage, a second pole of the first PMOS tube is connected with a control pole of the second PMOS tube and then connected with a first pole of a second NMOS tube, a second pole of the second NMOS tube is grounded, a second pole of the second PMOS tube is connected with a control pole of the first PMOS tube and then connected with a first pole of a third NMOS tube, and a second pole of the third NMOS tube is grounded;

the input end of the second phase inverter is connected with the first pole of the second NMOS tube, the output end of the second phase inverter is used as the output end, and the power supply end of the second phase inverter is connected with a power supply level signal of the second voltage;

and the input end of the third phase inverter is connected with the first pole of the third NMOS tube, the output end of the third phase inverter is used as the inverted output end, and the power supply end of the third phase inverter is connected with the power supply level signal of the second voltage.

5. The level-shifter based physically unclonable function circuit of claim 4,

when the control signal received by the control electrode of the first NMOS tube is a low level signal, the mode switching module shifts and converts the input signal into a power supply level signal of a second voltage and outputs the power supply level signal from the output end;

when the control signal received by the control electrode of the first NMOS tube is a high level signal, the mode switching module outputs the level signal of '0' or '1' from the output end to generate the physical unclonable random number.

6. A method of controlling a level shifter based physically unclonable function circuit according to any of claims 1-5, comprising the steps of:

receiving a control signal and sending a mode control signal according to the control signal, wherein the mode control signal comprises a level conversion mode control signal and a PUF output mode control signal;

when the level conversion mode control signal is received and an input signal of an input end is a logic signal of a first voltage, the input signal is shifted and converted into a power supply level signal of a second voltage and the power supply level signal is output from an output end;

outputting a level signal of "0" or "1" from the output terminal to generate a physically unclonable random number upon receiving the PUF output pattern control signal, wherein the first voltage is smaller than the second voltage.