CN104022772A - Close-loop analog quantity output method and circuit capable of zero setting automatically - Google Patents
Close-loop analog quantity output method and circuit capable of zero setting automatically Download PDFInfo
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- CN104022772A CN104022772A CN201310647585.1A CN201310647585A CN104022772A CN 104022772 A CN104022772 A CN 104022772A CN 201310647585 A CN201310647585 A CN 201310647585A CN 104022772 A CN104022772 A CN 104022772A
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Abstract
The invention discloses a close-loop analog quantity output method and circuit capable of zero setting automatically. The circuit comprises a reference zeroing module, a filtering operation amplifier module, a constant current source module, an analog current/ voltage conversion module and a feedback module. The filtering operation amplifier module comprises a first input end, a second input end and an output end. A digital PWM wave output by a CPU is input to the first input end of the filtering operation amplifier module; the reference zeroing module is electrically connected with the second input end of the filtering operation amplifier module; and the output end of the filtering operation amplifier module is electrically connected with the constant current source module, and an analog current magnitude is generated on the constant current source module. After the analog current magnitude passes through the analog current/ voltage conversion module and the feedback module in sequence, a sampling voltage is generated. The generated sampling voltage is input into an analog quantity AD sampling port of the CPU. According to the method and circuit, pulse width adjustment can be carried out on the digital PWM signals, the pulse width is automatically adjusted to compensate a nominal analog voltage so as to eliminate steady state errors due to temperature drift and circuit parameters, and anti-disturbance performance of the circuit is improved.
Description
Technical field
The present invention relates to field of power electronics, relating in particular to one can be from zeroing closed loop analog output method and circuit.
Background technology
The PWM ripple that the input of analog output interface circuit circuit often adopts CPU to send, pulsewidth by program control PWM ripple, frequency, after interface circuit is made filtering amplifier and processed, can obtain 0-10V analog voltage or the 0-20mA of nominal, the current amplitude of 4-20mA.
This PWM control simulation amount output circuit has simplicity of design, resolution is high, the linearity is good feature, is widely used in Industry Control and electronics, electric product, is wherein also no lack of the classical model about this circuit.But this kind of circuit be in the comparatively severe occasion of some environment, as easily there is high temperature, strong jamming in some Industry Control time, this scheme performance is unsatisfactory, often has the problem such as amplifier null offset, output amplitude disturbance in application.
Consider to select low drift amplifier, add EMC components and parts and can improve this problem from device, but this scheme still can not meet some to the linearity and the stricter occasion of stability requirement, and increase product cost.
Summary of the invention
For the weak point existing in above-mentioned technology, the invention provides one can be from zeroing closed loop analog output method and circuit, this circuit adopts closed-loop control analog output mode, can improve circuit performance of noiseproof, eliminates the steady-state error that temperature drift and circuit parameter cause.
For achieving the above object, the invention provides one can, from zeroing closed loop analog output method, comprise the following steps:
Step 1, the digital PWM ripple that CPU is exported carry out RC filtering, amplifier integration reverse process;
Step 2, the zeroing voltage reversal producing through step 1 digital PWM ripple after treatment and benchmark zeroing module are added, and generate analog voltage amount;
Step 3, analog voltage amount generate simulation current flow after entering constant-current source resume module;
Step 4, detection simulation output mode select signal whether to control the break-make of metal-oxide-semiconductor, if turn-off, jump procedure 3, if open-minded, enters step 5;
The nominal analog voltage of step 5, simulation current flow conversion output 0-10V;
The nominal analog voltage input feedback module of step 6,0-10V, and simulation output feedback signal in this feedback module output sampled voltage;
After step 7, sampled voltage input CPU analog quantity AD sample port, form closed loop;
Whether step 8, detection analog quantity AD sample port up-sampling voltage exist temperature to float or disturbance, if do not exist, this jump procedure 10, if exist, enters step 9;
Step 9, in real time digital pwm signal is carried out to pulse-width regulated, until realize the closed-loop control of the nominal analog voltage to AD sample port 0-10V;
Step 10, execution finish.
Wherein, in described step 6 sampled voltage between 0-3V.
Wherein, in described step 3, simulation current flow is 0-20mA.
For achieving the above object, the present invention also provides one zeroing closed loop analogue quantity output circuit certainly, comprises the benchmark zeroing module, filtering amplifier module, constant-current source module, analog current voltage transformation module and the feedback module that produce zeroing voltage, described filtering amplifier module comprises first input end, the second input and output, the first input end of the digital PWM ripple input filter amplifier module that frequency is certain and pulsewidth is adjustable of CPU output, described benchmark zeroing module is electrically connected with the second input of filtering amplifier module, the output of described filtering amplifier module is electrically connected with constant-current source module, and generate simulation current flow in constant-current source module, this simulation current flow produces sampled voltage successively after analog current voltage transformation module and feedback module, after the sampled voltage input CPU analog quantity AD sample port of described generation, this circuit forms closed loop.
Wherein, described benchmark zeroing module comprises chip and the first electric capacity; Between the input of described chip and output, be electrically connected with the second electric capacity and the 3rd electric capacity of connecting, after the output of described chip is electrically connected with one end of the first electric capacity, produce zeroing voltage, the other end of described the first electric capacity is also connected electrically between the second electric capacity and the 3rd electric capacity.
Wherein, described filtering amplifier module comprises the first resistance, the second resistance, the 4th electric capacity, the first amplifier comparator and the second amplifier comparator, the digital PWM ripple of described CPU output is successively by transferring to the reverse input end of the first amplifier comparator after the first resistance and the second resistance, one end ground connection of described the 4th electric capacity, the other end is connected electrically between the first resistance and the second resistance, the in-phase input end of described the first amplifier comparator is by ground connection after the 3rd resistance, between the reverse input end of described the first amplifier comparator and output, be parallel with the 4th resistance and the 5th electric capacity, and the output of described the first amplifier comparator is by the reverse input end of the 5th resistance and the second amplifier comparator, the in-phase input end of described the second amplifier comparator is by ground connection after the 6th resistance, the output of described the second amplifier comparator is electrically connected with the 7th resistance, between the reverse input end of described the second amplifier comparator and the 7th resistance, be parallel with the 8th resistance and the 6th electric capacity, described the 6th electric capacity is also successively by being electrically connected to zeroing voltage after the 9th resistance and the tenth resistance, described the 9th resistance is also by ground connection after the 11 resistance in parallel and the 7th electric capacity, described the 7th resistance is also electrically connected constant-current source module.
Wherein, described constant-current source module comprises the 3rd amplifier comparator and the first triode, described the 7th resistance is also electrically connected with the in-phase input end of the 3rd amplifier comparator by the 12 resistance, the inverting input of described the 3rd amplifier comparator is by ground connection after the 13 resistance, the output of described the 3rd amplifier comparator is electrically connected with the base stage of the first triode by the 14 resistance, between the in-phase input end of described the 3rd amplifier comparator and inverting input, be electrically connected with the 15 resistance of connecting, the 16 resistance and the 17 resistance, and described the 15 resistance and the 16 resistance common port are also electrically connected analog current voltage transformation module, the in-phase input end of described the 3rd amplifier comparator is also by ground connection after the 8th electric capacity, the inverting input of described the 3rd amplifier comparator is also by ground connection after the 9th electric capacity, the emitter of described the first triode is connected electrically between the 16 resistance and the 17 resistance, and the collector electrode of described the first triode electrical connection 15V voltage.
Wherein, described analog current voltage transformation module comprises the second triode and metal-oxide-semiconductor, simulation output mode inputs to the base stage of the two or three utmost point after selecting signal by the 18 resistance, the equal ground connection of emitter of the source electrode of described metal-oxide-semiconductor and the two or three utmost point, and described the two or three base stage of the utmost point and the source electrode of metal-oxide-semiconductor are electrically connected with the 19 resistance, drain electrode electrical connection the 20 resistance and the 21 resistance in parallel of described metal-oxide-semiconductor, described the 20 resistance also connects the first diode and second diode of series connection, described the 21 resistance is also connected to the common port that the first diode and the second diode form, 15V supply voltage is connected to respectively the two or three collector electrode of the utmost point and the grid of metal-oxide-semiconductor by the 23 resistance, and the nominal analog voltage of the drain electrode of described metal-oxide-semiconductor output 0-10V, and the nominal analog voltage of this 0-10V inputs to feedback module.
Wherein, described feedback module comprises four high guaily unit comparator and the 24 resistance, the nominal analog voltage of described 0-10V inputs to the in-phase input end of four high guaily unit comparator by the 24 resistance, short circuit between the inverting input of described four high guaily unit comparator and output, and described four high guaily unit comparator output terminal is electrically connected to simulation output feedback signal after by the 25 resistance, described simulation output feedback signal output sampled voltage also inputs to CPU analog quantity AD sample port, between the in-phase input end of described four high guaily unit comparator and output, be also parallel with the tenth electric capacity, the 26 resistance and the 11 electric capacity.
Compared with prior art, provided by the invention can, from zeroing closed loop analog output method and circuit, have following beneficial effect:
1) method provided by the invention, by detecting analog quantity AD sample port up-sampling voltage, whether detect digital PWM ripple exists temperature to float or disturbance, if the digital PWM ripple that CPU sends occurs that temperature is floated or when disturbance, the present invention just carries out pulse-width regulated to digital pwm signal in real time, automatically adjusting pulsewidth compensates the steady-state error that nominal analog voltage causes to eliminate temperature drift and circuit parameter, improves circuit performance of noiseproof;
2) by the break-make of simulating output mode selection signal controlling metal-oxide-semiconductor, and realize the conversion of simulation current flow and voltage, the nominal analog voltage of final output 0-10V, this nominal analog voltage is through the simulation output feedback signal output sampled voltage of feedback module, this process makes digital PWM ripple form closed loop control, the circuit that this output intent is formed can regulate voluntarily and keep original state, reduces the impact of disturbing analog voltage;
3) circuit provided by the invention, by common amplifier stack benchmark zeroing module, and introduces closed-loop control system, to improve circuit performance of noiseproof, eliminates the steady-state error that temperature drift and circuit parameter cause;
4) the present invention also have reasonable in design, resolution is high, the linearity good, stability is strong and operating efficiency high.
Brief description of the drawings
Fig. 1 is the workflow diagram of the closed loop of zeroing certainly analog output method of the present invention;
Fig. 2 is the fundamental diagram of filtering amplifier module, constant-current source module and analog current voltage transformation module in the present invention;
Fig. 3 is the fundamental diagram of benchmark zeroing voltage module in the present invention;
Fig. 4 is the fundamental diagram of feedback module in the present invention;
Fig. 5-10 are the output waveform figure of closed-loop simulation output circuit;
Figure 11 is the oscillogram of the present invention's the first concrete application examples;
Figure 12 is the oscillogram of prior art the first concrete application examples;
Figure 13 is the oscillogram of the present invention's the second concrete application examples;
Figure 14 is the oscillogram of prior art the second concrete application examples.
Main element symbol description is as follows:
10, benchmark zeroing module 11, filtering amplifier module
12, constant-current source module 13, analog current voltage transformation module
14, feedback module
Embodiment
In order more clearly to explain the present invention, below in conjunction with accompanying drawing, the present invention is further described.
Refer to Fig. 1-4, of the present invention can, from zeroing closed loop analog output method, comprising the following steps:
Step S1, the digital PWM ripple AO-PWM that CPU is exported carry out RC filtering, amplifier integration reverse process; In this step, by RC capacitance resistance ware, it is carried out to filtering, and carry out amplifier integration reverse process by the first amplifier comparator.
Step S2, the zeroing voltage VREF producing through above-mentioned digital PWM ripple AO-PWM after treatment and benchmark zeroing module 10 are oppositely added, and generate analog voltage amount; The concrete steps that benchmark zeroing module 10 produces zeroing voltage in this step are; After supply voltage+5V input chip U, by chip U processings of return to zero, and the output voltage VREF that returns to zero, be using reference voltage as the voltage that returns to zero here, and be+3V.
Step S3, analog voltage amount enter after constant-current source module 12 is processed and generate simulation current flow.
Step S4, detection simulation output mode select signal AO-SELECT whether to control the break-make of metal-oxide-semiconductor, if turn-off, jump procedure S3, if open-minded, enters step S5.
The nominal analog voltage of step S5, simulation current flow conversion output 0-10V; In this step, can realize the conversion of 0-20mA simulation current flow to the nominal analog voltage AO of 0-10V.
The nominal analog voltage AO input feedback module 14 of step S6,0-10V, and simulation output feedback signal AO-BACK in this feedback module 14 output sampled voltage, sampled voltage is between 0-3V.
After step S7, sampled voltage input CPU analog quantity AD sample port, form closed loop; The input of simulating the defeated CPU of being back to of sampled voltage of the 0-3V of output feedback signal AO-BACK forms closed-loop control.
Whether step S8, detection analog quantity AD sample port up-sampling voltage exist temperature to float or disturbance, if do not exist, this jump procedure S10, if exist, enters step S9.
Step S9, in real time digital pwm signal is carried out to pulse-width regulated, until realize the closed-loop control of the nominal analog voltage to AD sample port 0-10V; In this step, carry out real-time pulse-width regulated by four high guaily unit comparator, after adjusting, make this imitated output quantity belong in a correct accurate scope.
Step S10, execution finish.
For realizing the above-mentioned closed loop of zeroing certainly analog output method, the present invention also provides the output circuit of realizing the method, now this circuit is further elaborated: this circuit comprises the benchmark zeroing module 10, filtering amplifier module 11, constant-current source module 12, analog current voltage transformation module 13 and the feedback module 14 that produce zeroing voltage VREF, filtering amplifier module 11 comprises first input end, the second input and output, the first input end of the digital PWM ripple AO-PWM input filter amplifier module 11 that frequency is certain and pulsewidth is adjustable of CPU output, benchmark zeroing module 10 is electrically connected with the second input of filtering amplifier module 11, the output of filtering amplifier module 11 is electrically connected with constant-current source module 12, and generate simulation current flow in constant-current source module 12, this simulation current flow produces sampled voltage successively after analog current voltage transformation module 13 and feedback module 14, after the sampled voltage input CPU analog quantity AD sample port producing, this circuit forms closed loop.
In the present embodiment, benchmark zeroing module 10 comprises chip U and the first capacitor C 1; Between the input of chip U and output, be electrically connected with the second capacitor C 2 and the 3rd capacitor C 3 of connecting, after the output of chip U is electrically connected with one end of the first capacitor C 1, produce zeroing voltage VREF, the other end of the first capacitor C 1 is also connected electrically between the second capacitor C 2 and the 3rd capacitor C 3.Pass through in this module+5V input generates 3V zeroing voltage VREF through U.Chip U in this module can, according to the offset voltage for disappearing in circuit, return to zero.
In the present embodiment, filtering amplifier module 11 comprises the first resistance R 1, the second resistance R 2, the 4th capacitor C 4, the first amplifier comparator U1 and the second amplifier comparator U2, the digital PWM ripple AO=PWM of CPU output is successively by transferring to the reverse input end of the first amplifier comparator U1 after the first resistance R 1 and the second resistance R 2, one end ground connection of the 4th capacitor C 1, the other end is connected electrically between the first resistance R 1 and the second resistance R 2, the in-phase input end of the first amplifier comparator U1 is by the rear ground connection of the 3rd resistance R 3, between the reverse input end of the first amplifier comparator U1 and output, be parallel with the 4th resistance R 4 and the 5th capacitor C 5, and the output of the first amplifier comparator U1 is by the reverse input end of the 5th resistance R 5 and the second amplifier comparator U2, the in-phase input end of the second amplifier comparator U2 is by the rear ground connection of the 6th resistance R 6, the output of the second amplifier comparator U2 is electrically connected with the 7th resistance R 7, between the reverse input end of the second amplifier comparator U2 and the 7th resistance R 7, be parallel with the 8th resistance R 8 and the 6th capacitor C 6, the 6th capacitor C 6 is also successively by being electrically connected to zeroing voltage VREF after the 9th resistance R 9 and the tenth resistance R 10, the 9th resistance R 9 is also by the 11 resistance R 11 and the rear ground connection of the 7th capacitor C 7 in parallel, the 7th resistance R 7 is also electrically connected constant-current source module 12.
In the present embodiment, constant-current source module 12 comprises the 3rd amplifier comparator U3 and the first triode Q1, the 7th resistance R 7 is also electrically connected with the in-phase input end of the 3rd amplifier comparator U3 by the 12 resistance R 12, the inverting input of the 3rd amplifier comparator U3 is by the rear ground connection of the 13 resistance R 13, the output of the 3rd amplifier comparator U3 is electrically connected with the base stage of the first triode Q1 by the 14 resistance R 14, between the in-phase input end of the 3rd amplifier comparator U3 and inverting input, be electrically connected with the 15 resistance R 15 of connecting, the 16 resistance R the 16 and the 17 resistance R 17, and the 15 resistance R the 15 and the 16 resistance R 16 common ports are also electrically connected analog current voltage transformation module 13, the in-phase input end of the 3rd amplifier comparator U3 is also by the rear ground connection of the 8th capacitor C 8, the inverting input of the 3rd amplifier comparator U3 is also by the rear ground connection of the 9th capacitor C 9, the emitter of the first triode Q1 is connected electrically between the 16 resistance R the 16 and the 17 resistance R 17, and the collector electrode of the first triode Q1 electrical connection 15V voltage.
In the present embodiment, analog current voltage transformation module 13 comprises the second triode Q2 and metal-oxide-semiconductor M, simulation output mode inputs to the base stage of the two or three utmost point Q2 after selecting signal AO-SELECT by the 18 resistance R 18, the equal ground connection of emitter of the source electrode of metal-oxide-semiconductor M and the two or three utmost point Q2, and the source electrode of the base stage of the two or three utmost point Q2 and metal-oxide-semiconductor M is electrically connected with the 19 resistance R 19, drain electrode electrical connection the 20 resistance R the 20 and the 21 resistance R 21 in parallel of metal-oxide-semiconductor M, the 20 resistance R 20 also connects the first diode D1 and the second diode D2 of series connection, the 21 resistance R 21 is also connected to the common port that the first diode D1 and the second diode D2 form, 15V supply voltage is connected to respectively the collector electrode of the two or three utmost point Q2 and the grid of metal-oxide-semiconductor M by the 23 resistance R 23, and the nominal analog voltage AO of the drain electrode of metal-oxide-semiconductor M output 0-10V, and the nominal analog voltage AO of this 0-10V inputs to feedback module 14.
In the present embodiment, feedback module 14 comprises four high guaily unit comparator U4 and the 24 resistance R 24, the nominal analog voltage AO of 0-10V inputs to the in-phase input end of four high guaily unit comparator U4 by the 24 resistance R 24, short circuit between the inverting input of four high guaily unit comparator U4 and output, and four high guaily unit comparator U4 output is electrically connected to simulation output feedback signal AO-BACK after by the 25 resistance R 25, simulation output feedback signal AO-BACK output sampled voltage also inputs to CPU analog quantity AD sample port, between the in-phase input end of four high guaily unit comparator U and output, be also parallel with the tenth capacitor C 10, the 26 resistance R the 26 and the 11 capacitor C 11.In this circuit, in real time digital PWM ripple AO-PWM signal is carried out to pulse-width regulated by four high guaily unit comparator U4, realize the closed-loop control of the 0-10V to AD mouth.
Please further consult Fig. 5-10, amplitude Y1=5V, the fixed frequency of establishing the digital PWM ripple signal AO-PWM of CPU output are that 2KHZ, duty are the adjustable square wave of △ X, when metal-oxide-semiconductor M opens, and Y2=V
aO, record waveform as, CH1=AO-PWM, CH2=AO, the test condition in these Fig. 5-8: 25 ° of normal temperature, zero load; If Fig. 5 is input pwm pulse f
aO-PWM=2KHZ, Y1=5V, Fig. 6 is when controlling pulsewidth duty and being 100uS, V
aO=0V, Fig. 7 is when controlling pulsewidth duty and being 74uS, V
aO=-1V, Fig. 8 is when controlling pulsewidth duty and being 412uS, V
aO=10V.Fig. 9-10th, limit test condition: 85 ° of insulating boxs, load current 5mA, Fig. 9 is when automatically controlling pulsewidth duty and being 112uS, V
aO=-18mV, Figure 10 is when automatically controlling pulsewidth duty and being 432 uS, V
aO=9.99V.
From Fig. 5-10, can obtain drawing a conclusion: the digital PWM ripple AO-PWM pulsewidth that 1) Fig. 5-8 show to control CPU output can make this circuit output 0-10V nominal analog voltage AO, and can be closed-loop control and provide lower than 0V and be greater than the voltage margin of 10V; 2), when temperature rises to 85 °, because of the temperature characterisitic of each device, make output voltage V
aOcan reduce, comparison diagram 2 knows, Fig. 9 shows, digital PWM ripple AO-PWM is by increasing pulsewidth 12uS with compensation drift; 3) at AO mouth and while meeting load R=2K Ω, while comparing zero load, voltage stress slightly declines, and comparison diagram 8 knows, Figure 10 shows, digital PWM ripple AO-PWM by increase pulsewidth 20uS with the load of compensation AO mouth because of the voltage fluctuation changing or disturbance causes.
Frequency converter is conventionally with analog output function, and analog output interface circuit is widely used in instrument and shows or control slave industrial control equipment, but the analog quantity of output is subject to environment or the load variations of different use occasion appearance or the impact of disturbance.This circuit application, on AC80 Series Frequency Converter control board, is improved to system performance of noiseproof and stability, used steadily reliable in actual job site.As Figure 11-13rd, the contrast of AC80 series analog amount output circuit and other serial traditional analog amount output circuit oscillogram; Analog output Y2=-12.5mV when Figure 11 is AC80 series 0HZ, analog output Y2=-225mV when Figure 12 is other serial 0HZ, analog output Y2=9.99V when Figure 13 is AC80 series 50HZ, analog output Y2=-9.825V when Figure 14 is other serial 50HZ.Can obtain drawing a conclusion from above-mentioned contrast: the corresponding 0V output of frequency converter 0HZ, under on-the-spot hot environment, show to adopt this invention drift can be controlled in 0.1HZ by 11, Figure 12 deposits the corresponding 10V output of large 1.1HZ drift frequency converter 50HZ, while adopting slave pattern, exporting 9.99V by Figure 13 shows to adopt this invention can be by slave synchronous operation 50HZ, Figure 14 can only make slave move at 49HZ, if the internal resistance of slave simulated measurement input circuit more hour, to drag down AD sample port voltage, this problem is more obvious.
Provided by the invention can, from zeroing closed loop analog output method and circuit, have following advantage:
1) method provided by the invention, by detecting analog quantity AD sample port up-sampling voltage, whether detect digital PWM ripple exists temperature to float or disturbance, if the PWM ripple that CPU sends occurs that temperature is floated or when disturbance, the present invention just carries out pulse-width regulated to digital pwm signal in real time, automatically adjusting pulsewidth compensates the steady-state error that nominal analog voltage causes to eliminate temperature drift and circuit parameter, improves circuit performance of noiseproof.
2) by the break-make of simulating output mode selection signal controlling metal-oxide-semiconductor, and realize the conversion of simulation current flow and voltage, the nominal analog voltage of final output 0-10V, this nominal analog voltage is through the simulation output feedback signal output sampled voltage of feedback module, this process makes digital PWM ripple form closed loop control, the circuit that this output intent is formed can regulate voluntarily and keep original state, reduces the impact of disturbing analog voltage.
3) analog output method provided by the invention, analog voltage amount is first to transfer the nominal analog voltage that again transfers 0-10V after simulation current flow to, because analog voltage signal is poorer than analog current signal interference free performance, therefore in work transmission, transferring simulation current flow to transmits, reduce the transmission time of analog voltage amount, effectively improve the interference free performance of analog quantity.
4) circuit provided by the invention, by common amplifier stack benchmark zeroing module, and introduces closed-loop control system, to improve circuit performance of noiseproof, eliminates the steady-state error that temperature drift and circuit parameter cause.
5) the present invention also have reasonable in design, resolution is high, the linearity good, stability is strong and operating efficiency high.
Disclosed is above only several specific embodiment of the present invention, but the present invention is not limited thereto, and the changes that any person skilled in the art can think of all should fall into protection scope of the present invention.
Claims (9)
1. can, from a zeroing closed loop analog output method, it is characterized in that, comprise the following steps:
Step 1, the digital PWM ripple that CPU is exported carry out RC filtering, amplifier integration reverse process;
Step 2, the zeroing voltage reversal producing through step 1 digital PWM ripple after treatment and benchmark zeroing module are added, and generate analog voltage amount;
Step 3, analog voltage amount generate simulation current flow after entering constant-current source resume module;
Step 4, detection simulation output mode select signal whether to control the break-make of metal-oxide-semiconductor, if turn-off, jump procedure 3, if open-minded, enters step 5;
The nominal analog voltage of step 5, simulation current flow conversion output 0-10V;
The nominal analog voltage input feedback module of step 6,0-10V, and simulation output feedback signal in this feedback module output sampled voltage;
After step 7, sampled voltage input CPU analog quantity AD sample port, form closed loop;
Whether step 8, detection analog quantity AD sample port up-sampling voltage exist temperature to float or disturbance, if do not exist, this jump procedure 10, if exist, enters step 9;
Step 9, in real time digital pwm signal is carried out to pulse-width regulated, until realize the closed-loop control of the nominal analog voltage to AD sample port 0-10V;
Step 10, execution finish.
2. can, from zeroing closed loop analog output method, it is characterized in that according to claim 1, in described step 6, sampled voltage is between 0-3V.
3. can, from zeroing closed loop analog output method, it is characterized in that according to claim 1, in described step 3, simulation current flow is 0-20mA.
4. realize can, from a zeroing closed loop analogue quantity output circuit, it is characterized in that of method described in claim 1, comprise the benchmark zeroing module, filtering amplifier module, constant-current source module, analog current voltage transformation module and the feedback module that produce zeroing voltage, described filtering amplifier module comprises first input end, the second input and output, the first input end of the digital PWM ripple input filter amplifier module that frequency is certain and pulsewidth is adjustable of CPU output, described benchmark zeroing module is electrically connected with the second input of filtering amplifier module, the output of described filtering amplifier module is electrically connected with constant-current source module, and generate simulation current flow in constant-current source module, this simulation current flow produces sampled voltage successively after analog current voltage transformation module and feedback module, after the sampled voltage input CPU analog quantity AD sample port of described generation, this circuit forms closed loop.
5. can, from zeroing closed loop analogue quantity output circuit, it is characterized in that according to claim 4, described benchmark zeroing module comprises chip and the first electric capacity; Between the input of described chip and output, be electrically connected with the second electric capacity and the 3rd electric capacity of connecting, after the output of described chip is electrically connected with one end of the first electric capacity, produce zeroing voltage, the other end of described the first electric capacity is also connected electrically between the second electric capacity and the 3rd electric capacity.
6. can, from zeroing closed loop analogue quantity output circuit, it is characterized in that according to claim 4, described filtering amplifier module comprises the first resistance, the second resistance, the 4th electric capacity, the first amplifier comparator and the second amplifier comparator, the digital PWM ripple of described CPU output is successively by transferring to the reverse input end of the first amplifier comparator after the first resistance and the second resistance, one end ground connection of described the 4th electric capacity, the other end is connected electrically between the first resistance and the second resistance, the in-phase input end of described the first amplifier comparator is by ground connection after the 3rd resistance, between the reverse input end of described the first amplifier comparator and output, be parallel with the 4th resistance and the 5th electric capacity, and the output of described the first amplifier comparator is by the reverse input end of the 5th resistance and the second amplifier comparator, the in-phase input end of described the second amplifier comparator is by ground connection after the 6th resistance, the output of described the second amplifier comparator is electrically connected with the 7th resistance, between the reverse input end of described the second amplifier comparator and the 7th resistance, be parallel with the 8th resistance and the 6th electric capacity, described the 6th electric capacity is also successively by being electrically connected to zeroing voltage after the 9th resistance and the tenth resistance, described the 9th resistance is also by ground connection after the 11 resistance in parallel and the 7th electric capacity, described the 7th resistance is also electrically connected constant-current source module.
7. according to the closed loop analogue quantity output circuit that can certainly return to zero described in claim 4 or 6, it is characterized in that, described constant-current source module comprises the 3rd amplifier comparator and the first triode, described the 7th resistance is also electrically connected with the in-phase input end of the 3rd amplifier comparator by the 12 resistance, the inverting input of described the 3rd amplifier comparator is by ground connection after the 13 resistance, the output of described the 3rd amplifier comparator is electrically connected with the base stage of the first triode by the 14 resistance, between the in-phase input end of described the 3rd amplifier comparator and inverting input, be electrically connected with the 15 resistance of connecting, the 16 resistance and the 17 resistance, and described the 15 resistance and the 16 resistance common port are also electrically connected analog current voltage transformation module, the in-phase input end of described the 3rd amplifier comparator is also by ground connection after the 8th electric capacity, the inverting input of described the 3rd amplifier comparator is also by ground connection after the 9th electric capacity, the emitter of described the first triode is connected electrically between the 16 resistance and the 17 resistance, and the collector electrode of described the first triode electrical connection 15V voltage.
8. can, from zeroing closed loop analogue quantity output circuit, it is characterized in that according to claim 7, described analog current voltage transformation module comprises the second triode and metal-oxide-semiconductor, simulation output mode inputs to the base stage of the two or three utmost point after selecting signal by the 18 resistance, the equal ground connection of emitter of the source electrode of described metal-oxide-semiconductor and the two or three utmost point, and described the two or three base stage of the utmost point and the source electrode of metal-oxide-semiconductor are electrically connected with the 19 resistance, drain electrode electrical connection the 20 resistance and the 21 resistance in parallel of described metal-oxide-semiconductor, described the 20 resistance also connects the first diode and second diode of series connection, described the 21 resistance is also connected to the common port that the first diode and the second diode form, 15V supply voltage is connected to respectively the two or three collector electrode of the utmost point and the grid of metal-oxide-semiconductor by the 23 resistance, and the nominal analog voltage of the drain electrode of described metal-oxide-semiconductor output 0-10V, and the nominal analog voltage of this 0-10V inputs to feedback module.
9. according to claim 8 can be from zeroing closed loop analogue quantity output circuit, it is characterized in that, described feedback module comprises four high guaily unit comparator and the 24 resistance, the nominal analog voltage of described 0-10V inputs to the in-phase input end of four high guaily unit comparator by the 24 resistance, short circuit between the inverting input of described four high guaily unit comparator and output, and described four high guaily unit comparator output terminal is electrically connected to simulation output feedback signal after by the 25 resistance, described simulation output feedback signal output sampled voltage also inputs to CPU analog quantity AD sample port, between the in-phase input end of described four high guaily unit comparator and output, be also parallel with the tenth electric capacity, the 26 resistance and the 11 electric capacity.
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| CN201310647585.1A CN104022772B (en) | 2013-12-06 | 2013-12-06 | Can be from zeroing closed loop analog output method and circuit |
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| CN104539245A (en) * | 2014-11-11 | 2015-04-22 | 深圳市华星光电技术有限公司 | Self-zeroing circuit of operational amplifier |
| CN104731153A (en) * | 2015-01-27 | 2015-06-24 | 北京利德曼生化股份有限公司 | Closed-loop regulation drive circuit for high-power semiconductor chilling plate |
| CN107168284A (en) * | 2017-05-23 | 2017-09-15 | 深圳市汇辰自动化技术有限公司 | A kind of apparatus and method of automatic calibration PLC analog output modules |
| CN108957187A (en) * | 2018-07-17 | 2018-12-07 | 国网辽宁省电力有限公司电力科学研究院 | A kind of test device of ac analog channel hardware |
| CN110531744A (en) * | 2019-10-17 | 2019-12-03 | 北京和利时智能技术有限公司 | A kind of analog signals output circuit |
| CN114641112A (en) * | 2022-05-17 | 2022-06-17 | 西蒙电气（中国）有限公司 | Circuit structure, method and device for realizing smooth dimming of output pulse width feedback based on power supply chopping, processor and storage medium thereof |
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| CN110531744A (en) * | 2019-10-17 | 2019-12-03 | 北京和利时智能技术有限公司 | A kind of analog signals output circuit |
| CN114641112A (en) * | 2022-05-17 | 2022-06-17 | 西蒙电气（中国）有限公司 | Circuit structure, method and device for realizing smooth dimming of output pulse width feedback based on power supply chopping, processor and storage medium thereof |
| CN114641112B (en) * | 2022-05-17 | 2022-11-25 | 西蒙电气（中国）有限公司 | Circuit structure, method and device for realizing smooth dimming of output pulse width feedback based on power supply chopping, processor and storage medium thereof |
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