CN104022147A - Semiconductor device with function of restraining transient voltage - Google Patents
Semiconductor device with function of restraining transient voltage Download PDFInfo
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- CN104022147A CN104022147A CN201410252278.8A CN201410252278A CN104022147A CN 104022147 A CN104022147 A CN 104022147A CN 201410252278 A CN201410252278 A CN 201410252278A CN 104022147 A CN104022147 A CN 104022147A
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- 230000001052 transient effect Effects 0.000 title claims abstract description 21
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 230000000452 restraining effect Effects 0.000 title abstract 3
- 230000002093 peripheral effect Effects 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 8
- 238000002161 passivation Methods 0.000 claims description 8
- 230000005684 electric field Effects 0.000 abstract description 4
- 230000015556 catabolic process Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/8613—Mesa PN junction diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
Abstract
The invention discloses a semiconductor device with the function of restraining the transient voltage, the semiconductor device with the function of restraining the transient voltage comprises an upper stand body, a middle stand body and a lower stand body, wherein the middle stand body makes contact with the bottom face of the upper stand body, and the lower stand body makes contact with the bottom face of the middle stand body. The outer side face of the upper stand body and the outer side face of the lower stand body are inclined faces respectively. The upper stand body comprises a first N-type light doping region and a first N-type heavy doping region. The middle stand body is sequentially provided with a first P-type light doping region, a P-type heavy doping region and a second P-type light doping region from top to bottom. The lower stand body comprises a second N-type light doping region and a second N-type heavy doping region. The central region of a first PN junction contact face is provided with an upwards convex face, the edge region of the first PN junction contact face is provided with edge downwards concave faces, and the edge downwards concave faces are located on the two sides of the upwards convex face located in the center. The leakage current from the surface in the total leakage current is reduced, and the reverse leakage current of the whole device is reduced greatly, the high temperature resistance of the device is improved, the electric field intensity gradient at the edge is reduced, and voltage resistance of the device is improved.
Description
Technical field
The present invention relates to a kind of semiconductor device, be specifically related to a kind of transient voltage and suppress semiconductor device.
Background technology
Transient voltage suppresses semiconductor device TVS can guarantee that circuit and electronic devices and components are avoided static, surge pulse damages, and even loses efficacy.General TVS is parallel to protected circuit two ends, in holding state.When circuit two ends are subject to transient pulse or surge current, impact, and pulse amplitude is while surpassing the puncture voltage of TVS, TVS can become Low ESR the impedance at two ends from high impedance at a terrific speed and realize conducting, and absorbs transient pulse.Under this state, the voltage at its two ends substantially changes with current value, thus the voltage clamp at its two ends at a predetermined numerical value, this value is about 1.3～1.6 times of puncture voltage, with and protection circuit element below is not subject to the impact of transient pulse.
summary of the invention
Technical problem for above-mentioned existence, the object of the invention is: proposed a kind of transient voltage and suppressed semiconductor device, this transient voltage suppresses semiconductor device to be reduced in leakage current from surperficial leakage current, greatly reduce the reverse leakage current of whole device, and improved device resistance to elevated temperatures, reduce Liao edge electric field intensity gradient, thereby improved device withstand voltage performance.
Technical solution of the present invention is achieved in that a kind of transient voltage suppresses semiconductor device, comprise upper platform body, with the middle stage body of plane-plane contact at the bottom of upper platform body and with the lower platform body of plane-plane contact at the bottom of middle stage body, described upper platform body and be inclined-plane with lower platform body lateral surface separately, this upper platform body comprises the first light dope N-type district, the first heavy doping N-type district, described middle stage body is followed successively by the first doped with P type district, heavy doping p type island region and the second doped with P type district from top to bottom, and this lower platform body comprises the second light dope N-type district, the second heavy doping N-type district; Described the first heavy doping N-type district, the first light dope N-type district contact and are positioned at directly over it, and described the second heavy doping N-type district, the second light dope N-type district contact and be positioned under it;
In described middle stage body, the first doped with P type district contacts with the first light dope N-type district of upper platform body and forms the first PN junction contact-making surface, and in described middle stage body, the second doped with P type district contacts with the second light dope N-type district of lower platform body and forms the second PN junction contact-making surface;
One first passivation protection floor is covered in first fringe region of heavy doping N-type district upper surface and the side surface in the first heavy doping N-type district, one second passivation protection floor is covered in second fringe region of heavy doping N-type district lower surface and the side surface in the second heavy doping N-type district, upper metal level is covered in the middle section in the first heavy doping N-type district, and lower metal layer is covered in the middle section in the second heavy doping N-type district;
The upper area that described the first light dope N-type district contacts with the first heavy doping N-type district and the peripheral regions that is arranged in the first light dope N-type area edge have the first doped N-type district, this in first the upper surface in doped N-type district contact with the lower surface in the first heavy doping N-type district, this in first the lateral surface in doped N-type district extend to upper platform body lateral surface, the lower area that described the first doped with P type district contacts with heavy doping p type island region and the peripheral regions that is arranged in the first doped with P type area edge have first p type island region of adulterating, this lower surface that adulterates p type island region in first contacts with the upper surface of heavy doping p type island region, this lateral surface that adulterates p type island region in first extends to middle stage body lateral surface,
The lower area that described the second light dope N-type district contacts with the second heavy doping N-type district and the peripheral regions that is arranged in the second light dope N-type area edge have the second doped N-type district, this in second the lower surface in doped N-type district contact with the upper surface in the second heavy doping N-type district, this in second the lateral surface in doped N-type district extend to lower platform body lateral surface, the upper area that described the second doped with P type district contacts with heavy doping p type island region and the peripheral regions that is arranged in the second doped with P type area edge have second p type island region of adulterating, this upper surface that adulterates p type island region in second contacts with the lower surface of heavy doping p type island region, this lateral surface that adulterates p type island region in second extends to middle stage body lateral surface,
The middle section of described the first PN junction contact-making surface has convex surface on center, and the fringe region of described the first PN junction contact-making surface has edge concave surface, and this edge concave surface is positioned at convex surface both sides on center; The middle section of described the second PN junction contact-making surface has central dip face, and the fringe region of described the second PN junction contact-making surface has convex surface on edge, and on this edge, convex surface is positioned at central dip face both sides.
Related content in technique scheme is explained as follows:
In such scheme, the lateral surface of described upper platform body and with middle stage body in the angle of lateral surface in the first doped with P type district be 135 ° ~ 155 °, the lateral surface of described lower platform body and with middle stage body in the angle of lateral surface in the second doped with P type district be 135 ° ~ 155 °.
Because technique scheme is used, the present invention compared with prior art has following advantages and effect:
1. transient voltage of the present invention suppresses semiconductor device, it comprise upper platform body and with the lower platform body of plane-plane contact at the bottom of upper platform body, this upper platform body comprises light dope N-type district, heavy doping N-type district, this lower platform body comprises heavy doping p type island region, doped with P type district, the upper area that light dope N-type district contacts with heavy doping N-type district and the peripheral regions that is arranged in the first light dope N-type area edge have doped N-type district, the upper surface in Ci Zhong doped N-type district contacts with the lower surface in heavy doping N-type district, the lateral surface in Ci Zhong doped N-type district extends to upper platform body lateral surface, the lower area that doped with P type district contacts with heavy doping p type island region and the peripheral regions that is arranged in doped with P type area edge have doping p type island region, the lower surface of p type island region of adulterating in this contacts with the upper surface of heavy doping p type island region, the lateral surface of p type island region of adulterating in this extends to lower platform body lateral surface, at low pressure (below 10V) TVS under tunnel breakdown pattern, reduce in leakage current from surperficial leakage current, greatly reduce the reverse leakage current of whole device, thereby further reduced power consumption, avoided the local temperature rise of device, circuit stability and reliability have been improved.
2. transient voltage of the present invention suppresses semiconductor device, its upper platform body and with the lower platform body of plane-plane contact at the bottom of upper platform body, upper platform body and be inclined-plane with upper platform body lateral surface separately, the lateral surface of upper platform body and with the angle of the lateral surface of lower platform body be 135 ° ~ 155 °, improved device resistance to elevated temperatures, reduce Liao edge electric field intensity gradient, thereby improved device withstand voltage performance.
3. transient voltage of the present invention suppresses semiconductor device, the upper area that its light dope N-type district contacts with heavy doping N-type district and the peripheral regions that is arranged in the first light dope N-type area edge have doped N-type district, the lower area that doped with P type district contacts with heavy doping p type island region and the peripheral regions that is arranged in doped with P type area edge have doping p type island region, the middle section of PN junction contact-making surface has upper convex surface, the fringe region of PN junction contact-making surface has concave surface, this concave surface is positioned at convex surface both sides, improved effective-current area, peak electric field is moved to the reverse leakage current that also reduces whole device when having improved current density to center, guaranteed at high temperature, can face upward reverse current processed raises fast.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, technical solution of the present invention is described further:
Accompanying drawing 1 is transient voltage inhibition semiconductor device structure schematic diagram of the present invention;
In above accompanying drawing: 1, upper platform body; 2, middle stage body; 3, the first light dope N-type district; 4, the first heavy doping N-type district; 5, the second light dope N-type district; 6, the second heavy doping N-type district; 7, the first passivation protection layer; 8, the second passivation protection layer; 9, upper metal level; 10, lower metal layer; 11, doped N-type district in first; 12, the p type island region of adulterating in first; 13, lower platform body; 14, the first doped with P type district; 15, heavy doping p type island region; 16, the second doped with P type district; 17, doped N-type district in second; 18, the p type island region of adulterating in second; 19, convex surface on center; 20, edge concave surface; 21, central dip face; 22, convex surface on edge.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described.
A kind of transient voltage as shown in Figure 1 suppresses semiconductor device, comprise upper platform body 1, with the middle stage body 2 of 1 end of upper platform body plane-plane contact and with the lower platform body 13 of middle stage body 2 end plane-plane contact, described upper platform body 1 and be inclined-plane with lower platform body 13 lateral surface separately, this upper platform body 1 comprises the first light dope N-type district 3, the first heavy doping N-type district 4, described middle stage body 2 is followed successively by the first doped with P type district 14, heavy doping p type island region 15 and the second doped with P type district 16 from top to bottom, and this lower platform body 2 comprises the second light dope N-type district 5, the second heavy doping N-type district 6; Described the first heavy doping N-type district 4, the first light dope N-type district 3 contact and are positioned at directly over it, and described the second heavy doping N-type district 6, the second light dope N-type district 5 contact and be positioned under it;
In described middle stage body 2, the first doped with P type district 14 contacts with the first light dope N-type district 3 of upper platform body 1 and forms the first PN junction contact-making surface, and in described middle stage body 2, the second doped with P type district 16 contacts with the second light dope N-type district 5 of lower platform body 13 and forms the second PN junction contact-making surface;
One first passivation protection floor 7 is covered in first fringe region of heavy doping N-type district 4 upper surfaces and the side surface in the first heavy doping N-type district 4, one second passivation protection floor 8 is covered in second fringe region of heavy doping N-type district 6 lower surfaces and the side surface in the second heavy doping N-type district 6, upper metal level 9 is covered in the middle section in the first heavy doping N-type district 4, and lower metal layer 10 is covered in the middle section in the second heavy doping N-type district 6;
The upper area that described the first light dope N-type district 3 contacts with the first heavy doping N-type district 4 and the peripheral regions that is arranged in 3 edges, the first light dope N-type district have the first doped N-type district 11, this in first the upper surface in doped N-type district 11 contact with the lower surface in the first heavy doping N-type district 4, this in first the lateral surface in doped N-type district 11 extend to upper platform body 1 lateral surface, the lower area that described the first doped with P type district 14 contacts with heavy doping p type island region 15 and the peripheral regions that is arranged in 14 edges, the first doped with P type district have first p type island region 12 of adulterating, this lower surface that adulterates p type island region 12 in first contacts with the upper surface of heavy doping p type island region 15, this lateral surface that adulterates p type island region 12 in first extends to middle stage body 2 lateral surfaces,
The lower area that described the second light dope N-type district 5 contacts with the second heavy doping N-type district 6 and the peripheral regions that is arranged in 5 edges, the second light dope N-type district have the second doped N-type district 17, this in second the lower surface in doped N-type district 17 contact with the upper surface in the second heavy doping N-type district 6, this in second the lateral surface in doped N-type district 17 extend to lower platform body 13 lateral surfaces, the upper area that described the second doped with P type district 16 contacts with heavy doping p type island region 15 and the peripheral regions that is arranged in 16 edges, the second doped with P type district have second p type island region 18 of adulterating, this upper surface that adulterates p type island region 18 in second contacts with the lower surface of heavy doping p type island region 15, this lateral surface that adulterates p type island region 18 in second extends to middle stage body 2 lateral surfaces,
The middle section of described the first PN junction contact-making surface has convex surface 19 on center, and the fringe region of described the first PN junction contact-making surface has edge concave surface 20, and this edge concave surface 20 is positioned at convex surface 19 both sides on center; The middle section of described the second PN junction contact-making surface has central dip face 21, and the fringe region of described the second PN junction contact-making surface has convex surface 22 on edge, and on this edge, convex surface 22 is positioned at central dip face 21 both sides.
The lateral surface of above-mentioned upper platform body 1 and with middle stage body 2 in the angle of lateral surface in the first doped with P type district 14 be 135 ° ~ 155 °, the lateral surface of described lower platform body 13 and with middle stage body 2 in the angle of lateral surface in the second doped with P type district 16 be 135 ° ~ 155 °.
While adopting above-mentioned transient voltage to suppress semiconductor device, its at low pressure (below 10V) TVS under tunnel breakdown pattern, reduce in leakage current from surperficial leakage current, greatly reduce the reverse leakage current of whole device, thereby further reduced power consumption, avoid the local temperature rise of device, improved circuit stability and reliability; Again, its upper platform body and with the lower platform body of plane-plane contact at the bottom of upper platform body, upper platform body and be inclined-plane with upper platform body lateral surface separately, the lateral surface of upper platform body and with the angle of the lateral surface of lower platform body be 135 ° ~ 155 °, improved device resistance to elevated temperatures, guaranteed at high temperature, can face upward reverse current processed and raise fast.
Above-described embodiment is only explanation technical conceive of the present invention and feature; its object is to allow person skilled in the art can understand content of the present invention and be implemented; can not limit the scope of the invention with this; all equivalences that Spirit Essence is done according to the present invention change or modify, and all should be encompassed in protection scope of the present invention.
Claims (3)
1. a transient voltage suppresses semiconductor device, it is characterized in that: comprise upper platform body (1), with the middle stage body (2) of upper platform body (1) end plane-plane contact and with the lower platform body (13) of middle stage body (2) end plane-plane contact, described upper platform body (1) and be inclined-plane with lower platform body (13) lateral surface separately, this upper platform body (1) comprises the first light dope N-type district (3), the first heavy doping N-type district (4), described middle stage body (2) is followed successively by the first doped with P type district (14) from top to bottom, heavy doping p type island region (15) and the second doped with P type district (16), this lower platform body (2) comprises the second light dope N-type district (5), the second heavy doping N-type district (6), described the first heavy doping N-type district (4), the first light dope N-type district (3) contact and are positioned at directly over it, and described the second heavy doping N-type district (6), the second light dope N-type district (5) contact and be positioned under it,
In described middle stage body (2), the first doped with P type district (14) contacts with the first light dope N-type district (3) of upper platform body (1) and forms the first PN junction contact-making surface, and in described middle stage body (2), the second doped with P type district (16) contacts with the second light dope N-type district (5) of lower platform body (13) and forms the second PN junction contact-making surface;
One first passivation protection floor (7) is covered in first fringe region of heavy doping N-type district (4) upper surface and the side surface in the first heavy doping N-type district (4), one second passivation protection floor (8) is covered in second fringe region of heavy doping N-type district (6) lower surface and the side surface in the second heavy doping N-type district (6), upper metal level (9) is covered in the middle section in the first heavy doping N-type district (4), and lower metal layer (10) is covered in the middle section in the second heavy doping N-type district (6);
The upper area that described the first light dope N-type district (3) contacts with the first heavy doping N-type district (4) and the peripheral regions that is arranged in the first edge, light dope N-type district (3) have the first doped N-type district (11), this in first the upper surface in doped N-type district (11) contact with the lower surface in the first heavy doping N-type district (4), this in first the lateral surface in doped N-type district (11) extend to upper platform body (1) lateral surface, the lower area that described the first doped with P type district (14) contacts with heavy doping p type island region (15) and the peripheral regions that is arranged in the first edge, doped with P type district (14) have first p type island region (12) of adulterating, this lower surface that adulterates p type island region (12) in first contacts with the upper surface of heavy doping p type island region (15), this lateral surface that adulterates p type island region (12) in first extends to middle stage body (2) lateral surface,
The lower area that described the second light dope N-type district (5) contacts with the second heavy doping N-type district (6) and the peripheral regions that is arranged in the second edge, light dope N-type district (5) have the second doped N-type district (17), this in second the lower surface in doped N-type district (17) contact with the upper surface in the second heavy doping N-type district (6), this in second the lateral surface in doped N-type district (17) extend to lower platform body (13) lateral surface, the upper area that described the second doped with P type district (16) contacts with heavy doping p type island region (15) and the peripheral regions that is arranged in the second edge, doped with P type district (16) have second p type island region (18) of adulterating, this upper surface that adulterates p type island region (18) in second contacts with the lower surface of heavy doping p type island region (15), this lateral surface that adulterates p type island region (18) in second extends to middle stage body (2) lateral surface,
The middle section of described the first PN junction contact-making surface has convex surface on center (19), and the fringe region of described the first PN junction contact-making surface has edge concave surface (20), and this edge concave surface (20) is positioned at convex surface on center (19) both sides; The middle section of described the second PN junction contact-making surface has central dip face (21), and the fringe region of described the second PN junction contact-making surface has convex surface on edge (22), and convex surface on this edge (22) is positioned at central dip face (21) both sides.
2. transient voltage according to claim 1 suppresses semiconductor device, it is characterized in that: in described first, the contact-making surface in doped N-type district (11) and the first light dope N-type district (3) is arcwall face, the p type island region (12) of adulterating in described first is arcwall face with the contact-making surface in the first doped with P type district (14).
3. transient voltage according to claim 1 suppresses semiconductor device, it is characterized in that: in described second, the contact-making surface in doped N-type district (17) and the second light dope N-type district (5) is arcwall face, the p type island region (18) of adulterating in described second is arcwall face with the contact-making surface in the second doped with P type district (16).
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| CN201410252278.8A CN104022147B (en) | 2014-06-09 | 2014-06-09 | Semiconductor device with function of restraining transient voltage |
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| CN104022147B (en) * | 2014-06-09 | 2017-05-24 | 苏州市职业大学 | Semiconductor device with function of restraining transient voltage |
| CN113421930A (en) * | 2021-08-23 | 2021-09-21 | 江苏应能微电子有限公司 | Structure of bidirectional high-voltage transient voltage suppressor and manufacturing method thereof |
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| US20120329238A1 (en) * | 2009-04-30 | 2012-12-27 | Alpha & Omega Semiconductor, Inc. | Method For Forming A Transient Voltage Suppressor Having Symmetrical Breakdown Voltages |
| CN201985106U (en) * | 2010-10-19 | 2011-09-21 | 上海美高森美半导体有限公司 | Composite inner passivation layer structure of transient voltage suppression diode |
| CN201877435U (en) * | 2010-12-07 | 2011-06-22 | 中国振华集团永光电子有限公司 | Silicon bilateral transient voltage suppression diode |
| CN203941903U (en) * | 2014-06-09 | 2014-11-12 | 苏州市职业大学 | A kind of transient voltage suppresses semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104022147B (en) * | 2014-06-09 | 2017-05-24 | 苏州市职业大学 | Semiconductor device with function of restraining transient voltage |
| CN113421930A (en) * | 2021-08-23 | 2021-09-21 | 江苏应能微电子有限公司 | Structure of bidirectional high-voltage transient voltage suppressor and manufacturing method thereof |
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