CN104022074A - 一种含纳米孔隙的低介电常数复合薄膜的制备方法 - Google Patents

一种含纳米孔隙的低介电常数复合薄膜的制备方法 Download PDF

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CN104022074A
CN104022074A CN201410240798.7A CN201410240798A CN104022074A CN 104022074 A CN104022074 A CN 104022074A CN 201410240798 A CN201410240798 A CN 201410240798A CN 104022074 A CN104022074 A CN 104022074A
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丁士进
谭再上
范仲勇
张卫
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Fudan University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
    • C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
    • C23C16/513—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using plasma jets
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/1042—Formation and after-treatment of dielectrics the dielectric comprising air gaps
    • H01L2221/1047—Formation and after-treatment of dielectrics the dielectric comprising air gaps the air gaps being formed by pores in the dielectric

Abstract

本发明属于集成电路制造技术领域，具体为一种含纳米孔隙的低介电常数复合薄膜的制备方法。本发明以四乙氧基硅烷和双戊烯为前驱体，采用等离子体增强化学气相沉积工艺，通过控制沉积过程中的衬底温度、射频功率、反应腔中工作压强、前驱体配比等工艺参数，沉积得到无机-有机复合薄膜；然后对该薄膜进行适当的热退火处理，使得部分有机组分发生热分解，由此获得含纳米孔隙的低介电常数复合薄膜。该薄膜介电常数为2.5~2.9，在1MV/cm场强下的漏电流密度处于10-8~10-9A/cm2数量级范围内，击穿场强大于2MV/cm，且具有优异的力学性能。该方法操控简单，与现有集成电路后端互连工艺完全兼容，是互连介质的理想候选者。

Description

一种含纳米孔隙的低介电常数复合薄膜的制备方法
技术领域
本发明属于集成电路制造技术领域，具体涉及一种含纳米孔隙的低介电常数复合薄膜的制备方法，应用于铜互连中的层间介质。
背景技术
随着集成电路技术的发展，具有高速度、高器件密度、低功耗以及低成本的芯片越来越成为超大规模集成电路的主要产品。此时，芯片中的导线密度不断增加，导线宽度和间距不断减小，这导致芯片后端互连中的电阻（R）和电容（C）所产生的寄生效应越来越明显。目前，工业上已经普遍采用铜（Cu）代替铝（Al）进行布线，以降低电阻；以及采用低介电常数（low-k）材料取代传统的二氧化硅（SiO2）作为层内和层间电介质，以降低寄生电容。
工业上采用的low-k材料主要是通过向SiO2中掺入甲基等有机基团以及引入孔隙等方法，来实现降低介电常数的目的。然而，过多的有机基团和微孔的引入会导致薄膜的热稳定性变差，力学性能发生退化，从而限制了low-k薄膜在后端互连工艺中的应用。为了解决这一问题，需要对孔隙大小以及有机基团的引入进行严格的设计，采用适宜的前驱体和理想的工艺条件，来实现含有纳米孔隙的无机-有机复合薄膜的制备。因此，本发明以四乙氧基硅烷（TEOS）为前驱体，以双戊烯（LIMO）为成孔剂，采用与现有集成电路制造工艺相兼容的等离子体增强化学气相沉积（PECVD）技术，并结合薄膜沉积后的热处理，制备出了含纳米孔隙的低介电常数SiOCH无机-有机复合薄膜。该低介电常数复合薄膜具有优异的力学性能，能够满足集成电路后端互连的性能要求。
发明内容
本发明的目的在于针对现有技术存在的问题，提供一种力学性能优异的含纳米孔隙的低介电常数复合薄膜的制备方法。
本发明提出的含纳米孔隙的低介电常数复合薄膜，是以四乙氧基硅烷（TEOS）和双戊烯（LIMO）为前驱体，采用PECVD工艺，获得无机-有机复合薄膜。然后，对该复合薄膜进行热处理，使得部分有机组分发生热分解，从而得到含纳米孔隙的低介电常数无机-有机复合薄膜。
本发明提出的含纳米孔隙的低介电常数复合薄膜的制备方法，具体步骤如下：
（1）对反应腔体抽真空，使腔体压力小于0.02 Torr，然后通过加热系统将衬底加热至预设的温度，并维持稳定；
（2）向反应腔体中通入前驱体TEOS和LIMO，各自的流量分别为0.1~2 g/min；首先采用汽化器使TEOS和LIMO汽化，其中TEOS的汽化温度为120~160 ℃，LIMO的汽化温度为60~100 ℃；然后使用载气（例如氦气）将TEOS和LIMO蒸汽从不同气路输送到反应腔中，其中输送TEOS蒸汽的载气流量为500~5000 sccm，输送LIMO蒸汽的载气流量为1000~8000 sccm；
（3）等离子体增强化学气相沉积过程中，工艺参数分别为：功率50~800 W，衬底温度100~350 ℃，反应腔中工作压强1~8 Torr；上下极板间距10~20 mm；由此得到无机─有机复合薄膜，其中无机成分主要为Si-O-Si结构，有机成分主要为CHx（x=1, 2, 3）基团；
（4）将PECVD薄膜置于管式炉、箱式炉或其它腔体中，进行热退火处理；退火温度为400~600℃，退火时间为0.5~4小时，退火气氛可以为氩气、氦气、氮气等，压力为0.1~ 800 Torr。由于在退火过程中，部分有机组分发生热分解，获得含纳米孔隙的复合薄膜。
对上述薄膜进行电学和力学测量，性能如下：介电常数为2.5~2.9，在1 MV/cm场强下的漏电流密度处于10-8~10-9A/cm2数量级范围内，击穿场强大于2 MV/cm，杨氏模量为8~12 GPa，硬度为0.5~1.2 GPa。
本发明具有如下优点：
由本发明所提供的方法制备的薄膜具有低介电常数、良好的绝缘性能和优异的力学性能。这与本方法能向薄膜中引入纳米尺度的孔隙有关。
本发明提供的方法与现有集成电路加工工艺相兼容，所制备的薄膜可直接用作芯片后端互连中的层间介质。工艺操控简单容易，通过调整工艺参数，可以有效地控制薄膜的组分、化学结构、孔隙率等，达到调控low-k薄膜的电学、力学等性能的目的。
附图说明
图1是沉积薄膜以及经过热退火处理后薄膜的红外光谱图。
图2是热退火处理后薄膜的剖面透射电子显微镜照片。
具体实施方式
实施例1
设定衬底温度为200℃，反应腔中工作压强为3 Torr，沉积功率为300 W；TEOS和LIMO质量比为1:1，汽化温度分别为160 ℃和100 ℃；用氦气做载气，流量分别为2000 sccm和5000 sccm，沉积得到无机-有机复合薄膜。沉积薄膜在氩气（Ar）氛围不同温度下进行热退火处理，气压小于0.3 Torr，退火时间为1小时。
薄膜性能测量：薄膜厚度和折射率通过椭偏仪来测量，测量波长范围为250 nm~800 nm，并用柯西（Cauthy）模型拟合。为了测量上述薄膜的电学性能，本发明以低电阻率硅片（电阻率为0.001~0.005 Ω·cm）为衬底，以电子束蒸发的铝作为顶电极和底电极，顶电极为直径400 μm的圆形电极。在室温或高于室温（小于150 ℃）条件下，通过对铝/low-k薄膜/硅/铝结构的电容-电压（C-V）曲线的测量来提取介电常数，并通过多点测试来获得可靠的平均介电常数值。通过对电流-电压（I-V）曲线的测量获得薄膜的漏电特性。采用纳米压痕测试来得到薄膜的力学性能（杨氏模量和硬度），用于纳米压痕测试的薄膜厚度为600 nm左右，压入深度为薄膜厚度的10%。
由图1可以看出，热处理后的薄膜的红外光谱中在1140 cm-1附近存在一个明显的肩峰，这揭示了笼型Si-O-Si结构的存在。此外，热处理后对应于CHx的吸收峰强度显著减小，这表明PECVD沉积薄膜中含有较多的CHx有机基团，热处理导致大部分有机基团的分解去除。从图2可以看出，热处理后的薄膜中含有大量的纳米孔隙，与热处理后有机基团的分解相关。表1列出了PECVD沉积薄膜在不同温度退火后的各项性能参数，随着退火温度从400 ℃升高到500 ℃，所得薄膜的折射率从1.411减小到1.345，室温下介电常数从2.93减小到2.52。在1 MV/cm电场强度下它们的漏电流密度处于1.05×10-9 A/cm2~1.64×10-9 A/cm2的极低范围。薄膜的杨氏模量为7.81 GPa~10.60 GPa，硬度为0.74 GPa~1.10 GPa。
表1 
实施例2
设定衬底温度为200 ℃，反应腔中工作压强为3 Torr，沉积功率为300 W；采用不同的TOES和LIMO质量比，以洁净的低电阻率硅片（电阻率为0.001-0.005 Ω·cm）作为衬底，沉积得到一系列无机-有机复合薄膜，并在氮气（N2）氛围下进行热退火处理，气压约为一个大气压，退火温度为450 ℃，退火时间为1.5小时。如表2所示，所得薄膜的折射率为1.364-1.369，杨氏模量为6.65 GPa ~ 8.79 GPa，硬度为0.59 GPa ~ 0.92 GPa。所得薄膜在100 ℃下进行电性能测试，k值为2.60~2.75，1 MV/cm下的漏电流密度均处于10-9 A/cm2数量级。
表2 
实施例3
设定衬底温度为200 ℃，反应腔中工作压强为3 Torr，TEOS和LIMO质量比为1:1，以洁净的低电阻率硅片（电阻率为0.001-0.005 Ω·cm）作为衬底，改变沉积功率（分别为350  W、450 W、550 W），沉积得到一系列的薄膜。然后，将所得薄膜置于Ar气氛中进行热退火处理，气压小于0.3 Torr，退火温度为425 ℃，退火时间为4小时。经过热处理后的薄膜的电学性能如表3所示，测试温度为室温。随着PECVD射频功率从350 W增加到550 W，所得薄膜的介电常数从2.71上升到2.90，在1 MV/cm场强下的漏电流密度位于8.06×10-9 A/cm2 ~ 1.23×10-8 A/cm2范围内。
表3 
在此将本发明的材料描述为薄膜材料，但本发明不局限于此，本发明的材料可以多种形式存在，如粉末，块体，片材，涂层和薄膜等以及无需用于集成电路中的介质材料。任何本领域普通技术人员，在不脱离本发明的精神范围内，可做等效变化，均属于本发明的保护范围。

Claims (3)

1.一种含纳米孔隙的低介电常数复合薄膜的制备方法，其特征在于具体步骤如下：
（1）对反应腔体抽真空，使腔体压力小于0.02 Torr，然后通过加热系统将衬底加热至预设的温度，并维持稳定；
（2）向反应腔体中通入前驱体TEOS和LIMO，各自的流量分别为0.1~2 g/min；首先采用汽化器使TEOS和LIMO汽化，其中TEOS的汽化温度为120~160 ℃，LIMO的汽化温度为60~100 ℃；然后使用载气将TEOS和LIMO蒸汽从不同气路输送到反应腔中，其中输送TEOS蒸汽的载气流量为500~5000 sccm，输送LIMO蒸汽的载气流量为1000~8000 sccm；
（3）等离子体增强化学气相沉积过程中，工艺参数分别为：功率50~800 W，衬底温度100~350 ℃，反应腔中工作压强1~8 Torr；上下极板间距10~20 mm；由此得到无机-有机复合薄膜，其中无机成分主要为Si-O-Si结构，有机成分主要为CHx（x=1, 2, 3）基团；
（4）将复合薄膜置于管式炉、箱式炉或其它腔体中，进行热退火处理；退火温度为400~600℃，退火时间为0.5~4小时，退火气氛为氩气、氦气或氮气，压力为0.1~ 800 Torr；在退火过程中，部分有机组分发生热分解，从而获得含纳米孔隙的复合薄膜。
2.根据权利要求1所述的含纳米孔隙的低介电常数复合薄膜的制备方法，其特征在于：TEOS和LIMO蒸汽是通过汽化器获得，其中TEOS的汽化温度为120~160 ℃，LIMO的汽化温度为60~100℃。
3.一种由权利要求1所述制备方法制备得到的含纳米孔隙的低介电常数复合薄膜，其电学和力学性能如下：介电常数为2.5~2.9，在1 MV/cm场强下的漏电流密度处于10-8~10-9A/cm2数量级范围内，击穿场强大于2 MV/cm，杨氏模量为8~12 GPa，硬度为0.5~1.2 GPa。
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CN113981415A (zh) * 2021-10-25 2022-01-28 晶澳太阳能有限公司 管式pecvd系统的流量计异常工作的确定方法及装置

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