CN104009093A - Method for manufacturing high-k dielectric layer water-based indium oxide thin film transistors - Google Patents

Method for manufacturing high-k dielectric layer water-based indium oxide thin film transistors Download PDF

Info

Publication number
CN104009093A
CN104009093A CN201410264881.8A CN201410264881A CN104009093A CN 104009093 A CN104009093 A CN 104009093A CN 201410264881 A CN201410264881 A CN 201410264881A CN 104009093 A CN104009093 A CN 104009093A
Authority
CN
China
Prior art keywords
sample
preparation
spin coating
thin film
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201410264881.8A
Other languages
Chinese (zh)
Other versions
CN104009093B (en
Inventor
单福凯
刘奥
刘国侠
孟优
谭惠月
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qingdao University
Original Assignee
Qingdao University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qingdao University filed Critical Qingdao University
Priority to CN201410264881.8A priority Critical patent/CN104009093B/en
Publication of CN104009093A publication Critical patent/CN104009093A/en
Application granted granted Critical
Publication of CN104009093B publication Critical patent/CN104009093B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66969Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00Nanotechnology for materials or surface science, e.g. nanocomposites
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B82NANOTECHNOLOGY
    • B82YSPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00Manufacture or treatment of nanostructures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02301Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment in-situ cleaning
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02299Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
    • H01L21/02312Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
    • H01L21/02315Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/02623Liquid deposition
    • H01L21/02628Liquid deposition using solutions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02658Pretreatments
    • H01L21/02661In-situ cleaning
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/34Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
    • H01L21/46Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
    • H01L21/477Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/517Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate

Abstract

The invention belongs to the technical field of manufacturing of semiconductor thin film transistors and relates to a method for manufacturing high-k dielectric layer water-based indium oxide thin film transistors. The method includes the steps that zirconium acetylacetonate is dissolved in dimethylformamide, and ethanol amine of the same molar weight as the zirconium acetylacetonate is added as a stabilizer, so that a precursor solution is formed; a sample is obtained by coating a cleaned low-resistance silicon substrate with the precursor solution in a spinning mode, and a sample obtained after light annealing is obtained by placing the sample below a high-pressure mercury lamp for ultraviolet light treatment; a thin film sample is obtained through annealing of the sample obtained after light annealing; an In2O3 channel layer is obtained by coating the surface of the obtained thin film sample with an In2O3 aqueous solution; finally, a source electrode and a drain electrode are manufactured on the In2O3 channel layer, and then the thin film transistors can be obtained. According to the overall implementation scheme, cost is low, processes are simple, the principle is reliable, product performance is good, the manufacturing process is environmentally friendly, application prospects are wide, and a feasible plan is provided for manufacturing the high-performance thin film transistors on a large scale.

Description

The transistorized preparation method of a kind of high k dielectric layer water-based indium oxide film
Technical field:
The invention belongs to semiconductor thin-film transistor preparing technical field, relate to the transistorized preparation method of a kind of high k dielectric layer water-based indium oxide film, particularly a kind of with water-based indium oxide (In 2o 3) be channel layer and with ultra-thin zirconia (ZrO x, 1<x<2) be the preparation method of the thin-film transistor of high k dielectric layer.
Background technology:
In recent years, thin-film transistor (Thin Film Transistor, TFT) has been brought into play important function in driven with active matrix liquid crystal display device (Active Matrix Liquid Crystal Display, AMLCD).From low temperature amorphous silicon TFT to high temperature polysilicon TFT, technology is more and more ripe, application also from can only drive LCD (Liquid Crystal Display) to develop into not only can to drive LCD but also can driving OLED (Organic Light Emitting Display), Electronic Paper even.Along with semiconductor process technology improves constantly, Pixel Dimensions constantly reduces, the resolution of display screen is also more and more higher, TFT is as driving the switch application of pixel in the display devices such as liquid crystal display (TFT-LCD), wherein the size of grid dielectric material energy gap determines the size of leakage current, and its relative dielectric constant determines the size (being energy consumption size) of device subthreshold swing.Along with the development of large scale integrated circuit, as the characteristic size of the metal oxide semiconductor transistor of si-substrate integrated circuit core devices, constantly reduce always, it reduces rule and follows Moore's Law.The current lithographic dimensioned 28nm that reached, CMOS grid equivalent oxide thickness drops to below 1nm, the thickness of gate oxide approaches atomic distance (IEEE Electron Device Lett.2004,25 (6): 408-410), along with reducing of equivalent oxide thickness, cause tunnel effect, research shows silicon dioxide (SiO 2) thickness while reducing to 1.5nm by 3.5nm grid leakage current by 10 -12a/cm 2increase to 10A/cm 2(IEEE Electron Device Lett.1997,18 (5): 209-211).Larger leakage current can cause high power consumption and corresponding heat dissipation problem, and this all causes adverse influence for device integrated level, reliability and life-span, is therefore badly in need of the high dielectric material replacement traditional Si O that research and development make new advances 2.At present, extensively adopt high-k (high k) grid dielectric to increase capacitance density and reduce grid leakage current in MOS integrated circuit technology, high k material is because of its large dielectric constant, with SiO 2there is in the situation of same equivalent gate oxide thickness (EOT) its actual Thickness Ratio SiO 2large is many, thereby has solved SiO 2the quantum tunneling effect producing because approaching the physical thickness limit.
The novel high-k dielectric material that becomes at present study hotspot comprises ATO (Advanced Material, 24,2945,2012), Al 2o 3(Nature, 489,128,2012), ZrO 2(Advanced Material, 23,971,2011), WO 3(Applied Physics Letters, 102,052905,2013) and Ta 2o 5(Applied Physics Letters, 101,261112,2012) etc.TFT device is film-type structure, and the dielectric constant of its gate dielectric layer, compactness and thickness are very large to transistorized performance impact, at numerous SiO 2in grid dielectric substitute, zirconia (ZrO x) as high-k dielectric material, there is good reliability, it has larger dielectric constant (20-30), wider band gap (5.8eV) (Advanced Material, 23,971,2011), electronics and hole are had to proper passage barrier height (being greater than 1eV), there is good Lattice Matching with Si surface, can be compatible mutually with traditional CMOS technique.Therefore, ZrO xbe supposed to substitute traditional grid dielectric material, become the strong candidate of the high k grid of TFT of new generation dielectric material.And, consider new direction-printing electronic device of microelectronic component development in the future, utilizing sol-gel technique to prepare film will be a well selection, sol-gel technique is subject to extensive use in the preparation technology of superfines, film coating, fiber and other material, it has advantages of that it is unique: in its reaction each component be blended in intermolecular carrying out, thereby the particle diameter of product is little, uniformity is high; Course of reaction is easy to control, and can obtain the product that some are difficult to obtain with additive method, and reaction is carried out at low temperatures in addition, has avoided the appearance of high temperature dephasign, makes the purity of product high.Therefore adopt sol-gel technique to prepare ZrO xhigh k dielectric film, proposes the way that a kind of employing ultraviolet light decomposes and low temperature (300 ℃) thermal decomposition combines and decomposes ZrO xorganic principle in film, the principle that wherein ultraviolet light decomposes is: utilize ultraviolet UVC (200-275nm) and UVD wave band (100-200nm) and airborne oxygen reaction generation active oxygen, have the active oxygen of strong oxidizing property can be at room temperature with film in C, N element reaction generation Co x, NO xthereby gas departs from film; Simultaneously, ultraviolet light decomposition method can improve film sample surface state (Applied Physics Letters, 102,192101,2013), make sample surfaces finer and close, level and smooth, the less roughness in gate dielectric layer surface is conducive to charge carrier in surperficial migration, improves carrier mobility and the switching response speed of TFT device.In addition, following adopted low temperature thermal decomposition is processed ZrO xthe interlayer that film can effectively be avoided bringing in semiconductor channel layer process annealing (<300 ℃) the process phenomenon of dissolving each other; In the preparation process of channel layer, adopt distilled water to substitute traditional organic solution (EGME etc.) as solvent, form novel aqueous solution, aqueous solution has the advantages such as nontoxic, environmental protection, cheapness than conventional organic solution; In addition owing to being electrostatical binding between solute cation and hydrone in aqueous solution, than covalent bonds mode in organic solution, there is more weak combination energy, therefore adopt the film of aqueous solution method spin coating to there is lower decomposition temperature, utilize aqueous solution technology to prepare that reliability is high, reproducible, the semiconductive thin film of low-temperature decomposition is just becoming the technical field that industrial quarters and scientific research circle are being furtherd investigate.
At present, adopt amorphous oxides indium zinc oxygen (IZO), indium gallium zinc oxygen (IGZO), indium oxide (In 2o 3) material is as the preparation of thin film transistor channel layer and the existing open source literature of application technology, large quantity research has been done by the states such as Japan and Korea S..In 2o 3rely on its high mobility (>100cm 2/ Vs), high permeability (visible ray >80%) becomes the strong candidate (IEEE Electron Device Lett.31,567,2010) of semiconductor channel layer material.We consult by Patents, document, utilize aqueous solution method to prepare TFT channel layer and rarely have report, based on ultra-thin ZrO xthe water-based In of high k dielectric layer 2o 3nobody sets foot in TFT especially.Consider the requirement of future " flexible display device " to low temperature in thin film preparation process process, we guarantee in TFT preparation process that temperature is lower than 300 ℃.In prepared by above-mentioned technique 2o 3/ ZrO xthe TFT device of structure not only has higher carrier mobility, and thering is the feature (being greater than 80% in visible light wave range transmitance) of the high grade of transparency, its TFT, as the pixel switch of AMLCD, will improve the aperture opening ratio of active matrix greatly, improve brightness, reduce power consumption simultaneously; Its whole soln preparation technology does not rely on expensive vacuum coating equipment in addition, and cost of manufacture is further reduced, and these advantages make its transparent electron display device field in future have very wide potential market.
Summary of the invention:
The object of the invention is to overcome the shortcoming that prior art exists, seek design and provide a kind of with ultra-thin zirconia (ZrO x) be high k dielectric layer and with water-based indium oxide (In 2o 3) be the transistorized preparation method of high performance thin film of channel layer, first select low-resistance silicon as substrate and gate electrode, the mode that adopts sol-gel technique, photo-annealing and Low Temperature Thermal annealing to combine is prepared ultra-thin ZrO x(<10nm) gate dielectric layer; Adopt again aqueous solution method low temperature to prepare the In of high permeability, high mobility 2o 3semiconductor channel layer, thus be prepared into high performance thin-film transistor, and its electric property meets the requirement of display to thin-film transistor (TFT) completely.
To achieve these goals, the present invention specifically comprises following processing step:
(1), the preparation of precursor solution: by acetylacetone,2,4-pentanedione zirconium Zr (C 5h 7o 2) 4be dissolved in dimethyl formamide, add with the monoethanolamine of acetylacetone,2,4-pentanedione zirconium equimolar amounts as stabilizer the molar content [Zr of zirconium simultaneously 4+] be 0.01-0.9; The volume ratio of monoethanolamine and dimethyl formamide is 1:1-10; At 20-100 ℃ of lower magnetic force, stir the precursor solution that forms clear for 1-24 hour, wherein zirconia precursor solution concentration is 0.01-0.5M;
(2), the preparation of film sample: using plasma cleaning method cleans low-resistance surface of silicon, on low-resistance silicon substrate after cleaning, adopt the precursor solution of conventional sol-gel technique spin coating step (1) preparation to obtain sample, after spin coating finishes, sample is put into and under high-pressure mercury lamp, carries out ultraviolet lighting and process and obtain the sample after photo-annealing, make sample realize photodissociation and curing object; The sample after photo-annealing is carried out to 300 ℃ of process annealing 1-3 hour, the interlayer of avoiding semiconductor channel layer process annealing process the to bring phenomenon of dissolving each other, obtains film sample again;
(3), In 2o 3the preparation of channel layer: by indium nitrate In (NO 3) 3be dissolved in distilled water the In that the concentration that at room temperature stirs 1-24 hour formation clear is 0.1-0.3mol/L 2o 3aqueous solution; Then the film sample surface obtaining in step (2) utilizes sol-gel technique to adopt commercially available sol evenning machine spin coating In 2o 3aqueous solution, first even glue 4-8 second under 400-600 rev/min, then under 2000-4000 rev/min even glue 15-30 second, spin coating number of times is 1-3 time, at every turn spin coating thickness 5-10nm; Film sample after spin coating is put into 120-150 ℃ burned and is cured and puts into Muffle furnace after processing and carry out 200-300 ℃ of process annealing and process 1-3 hour, make In 2o 3thickness is the In of 5-30nm 2o 3film, prepares In 2o 3channel layer;
(4), the preparation of source, drain electrode: utilize conventional Vacuum sublimation to utilize stainless steel mask plate at In 2o 3preparation source, drain electrode above channel layer, obtain based on ultra-thin ZrO xthe water-based In of high k dielectric layer 2o 3thin-film transistor.
The plasma clean method relating in step of the present invention (2) adopts oxygen or argon gas as purge gas, and its power is 20-60Watt, and scavenging period is 20-200s, and the intake of working gas is 20-50 SCCM; When preparing film sample, use sol evenning machine spin coating, first even glue 4-8 second under 400-600 rev/min, then under 3000-6000 rev/min even glue 15-25 second; Spin coating number of times is 1-5 time, and the film thickness of each spin coating is 4-8nm; The power of high-pressure mercury lamp is 1-2KW, and the dominant wavelength of ultraviolet light is 365nm, and light application time is 20-40 minute, high-pressure mercury lamp light source distance sample surfaces 5-100cm.
The electrode raceway groove length-width ratio of thin-film transistor prepared by step of the present invention (4) is 1:4-20, and thermal evaporation electric current is 30-50A; The source making, leak electricity very metal A l or Au electrode, thickness of electrode is 50-200nm.
The present invention compared with prior art, there is following advantage: the one, the semiconductor channel layer in thin-film transistor and high k dielectric layer all utilize chemical solution method to prepare, and chemical solution system is very cheap, and its preparation process does not need high vacuum environment, in air, can carry out, reduce costs; Reaction can be carried out at low temperatures, avoids the appearance of high temperature dephasign when reducing costs; The 2nd, using plasma cleans substrate surface, and while increasing spin coating, precursor solution, with the adhesive force of substrate, makes film sample surface after spin coating homogeneous and smooth more; The 3rd, the mode that adopts ultraviolet light photo-annealing and Low Temperature Thermal annealing to combine obtains densification, novel novel grid dielectric material ZrO x, avoid traditional sol-gel film-forming process for the demand of high temperature (>500 ℃), make the ZrO of preparation xdielectric layer can be prepared in plastic, for important foundation is established in application flexible, transparent display part; The 4th, the ZrO making xthe physical thickness of high k gate dielectric layer is only 10nm, and the low-leakage current simultaneously having meets the integrated demand for device size of microelectronics well; ZrO xthe high permeability that film itself has (visible light wave range approaches 90%), meets the requirement of transparent electronics to material self; The ZrO making xfilm is amorphous state, can realize large area industry preparation; The 5th, in thin-film transistor, semiconductor channel layer utilizes the preparation of aqueous solution method.Utilize distilled water than conventional organic solvents, to there is the advantages such as nontoxic, environmental protection as solvent phase; Meanwhile, aqueous solution is less demanding to ambient humidity, therefore further reduces preparation cost; Finally, because distilled water does not have corrosivity, when dripping to ZrO xin the time of on gate dielectric layer, can not corrode ZrO xsurface, is therefore beneficial to formation interface more clearly, and this is most important for TFT device performance high-performance electricity performance; The 6th, utilize aqueous solution to prepare In 2o 3the high permeability that semiconductive thin film itself has (visible light wave range is greater than 80%), meets the requirement of transparent electronics; Its low temperature (<300 ℃) preparation condition is compatible mutually with the low temperature manufacturing technology that flat panel display requires simultaneously; Its General Implementing scheme cost is low, and technique is simple, and principle is reliable, good product performance, and preparation environmental friendliness, has a extensive future, and for large area, preparing high performance thin-film transistor provides feasible scheme.
Accompanying drawing explanation:
Fig. 1 be the present invention prepare based on ZrO xthe water-based In of high k dielectric layer 2o 3the structural principle schematic diagram of thin-film transistor.
Fig. 2 is that the thin-film transistor prepared of the present invention is at different I n 2o 3output characteristic curve figure during annealing temperature, wherein grid bias V gS=1.5V, the In of curve a 2o 3annealing temperature is 200 ℃; The In of curve b 2o 3annealing temperature is 230 ℃; The In of curve c 2o 3annealing temperature is In 2o 3-250 ℃; The In of curve d 2o 3annealing temperature is In 2o 3-270 ℃.
Fig. 3 is that the thin-film transistor prepared of the present invention is at different I n 2o 3transfer characteristic curve figure during annealing temperature, wherein source-drain voltage V dS=1.0V, the In of curve a 2o 3annealing temperature is 200 ℃; The In of curve b 2o 3annealing temperature is 230 ℃; The In of curve c 2o 3annealing temperature is In 2o 3-250 ℃; The In of curve d 2o 3annealing temperature is In 2o 3-270 ℃.
Embodiment:
Below by specific embodiment, also further illustrate by reference to the accompanying drawings the present invention.
Embodiment:
Acetylacetone,2,4-pentanedione zirconium in the present embodiment and indium nitrate powder, dimethyl formamide, monoethanolamine organic solvent are all purchased from Aladdin company, and purity is greater than 98%; Its bottom grating structure is with ultra-thin zirconia (ZrO x) be high k dielectric layer and with water-based indium oxide (In 2o 3) preparation process of the film thin-film transistor that is channel layer is:
(1) first adopt sol-gel technique to prepare ultra-thin ZrO xhigh k dielectric film:
Step 1: select the single-sided polishing low-resistance silicon of business purchase as substrate (ρ <0.0015 Ω cm) and gate electrode, low-resistance silicon substrate is used hydrofluoric acid, acetone, alcohol Ultrasonic Cleaning substrate respectively 10 minutes successively, after repeatedly rinsing with deionized water, high pure nitrogen dries up;
Step 2: dimethyl formamide and monoethanolamine are configured to mixed solution according to mol ratio 2:1, acetylacetone,2,4-pentanedione zirconium is dissolved in this mixed solution according to 0.1M, weigh mixed solution 10mL, taking acetylacetone,2,4-pentanedione zirconium is 0.48g, and after mixing, under the effect of magnetic agitation, 70 ℃ of water-baths are stirred and within 3 hours, formed clarification, transparent precursor liquid;
Step 3: clean low-resistance silicon substrate is put into plasma clean chamber, extract to 0.5Pa and pass into high-purity (99.99%) oxygen until chamber, controlling its power is 30Watt, and scavenging period is 120s, and during work, the intake of oxygen is 30SCCM;
Step 4: preparation ZrO xsample: the precursor solution of preparation in step 2 is spin-coated on the low-resistance silicon substrate cleaning, and spin coating number of times is 1~5 time, and during spin coating precursor solution, the parameter of sol evenning machine is set to: elder generation is in 500 revs/min of even glue 5 seconds, then in 5000 revs/min of even glue 25 seconds; After spin coating finishes, sample is put under high-pressure mercury lamp and carries out ultraviolet light polymerization processing, high-pressure mercury lamp power is 1KW, and dominant wavelength is UVC and UVD, and the uv-exposure time is 30 minutes, and mercury lamp light source is apart from sample surfaces 10cm, by the ZrO solidifying after processing xsample is put into Muffle furnace process annealing and is processed, and annealing temperature is 300 ℃, and annealing time 1 hour, obtains ZrO xsample;
(2) utilize In 2o 3in is prepared in aqueous solution spin coating 2o 3channel layer:
Step 1: indium nitrate powder is dissolved in distilled water, and indium ion concentration is 0.1M; In this experiment, weigh distilled water 10mL, taking indium nitrate is 0.3g, after mixing, under the effect of magnetic agitation, stirring at room forms the In of clear for 12 hours 2o 3aqueous solution;
Step 2: preparation In 2o 3channel layer: by the In of preparation in step 1 2o 3aqueous solution is spin-coated on the ZrO processing xon sample, during spin coating, the parameter of sol evenning machine is set to: first in 500 revs/min of even glue 5 seconds, then in 3000 revs/min of even glue 25 seconds, after spin coating finishes, sample is put into Muffle furnace process annealing and process, annealing temperature is for being respectively 200,230,250,270 ℃, annealing time 1 hour;
(3) adopt Vacuum sublimation to prepare source, leak metal electrode:
By the mode of thermal evaporation, at In 2o 3on channel layer, with the stainless steel mask plate that breadth length ratio is 1000/100 μ m, prepare metal A l that 100nm is thick as source, drain electrode, thermal evaporation electric current is 40A, prepares Al/In 2o 3/ ZrO xthe thin-film transistor of/Si structure;
(4) to the Al/In making 2o 3/ ZrO xthe thin-film transistor of/Si structure (Fig. 1) is tested; At different I n 2o 3thin-film transistor output characteristic curve under annealing temperature condition utilizes the test of Keithley 2634B semiconductor source table to obtain (Fig. 2); The transfer characteristic curve (Fig. 3) corresponding to thin-film transistor of preparation utilizes Keithley 2634B semiconductor source table test to obtain equally, wherein with the In of 200,230,250,270 ℃ of annealing in process 2o 3for a, b, c, d in the transfer characteristic curve difference corresponding diagram 3 of channel layer TFT.

Claims (3)

1. the transistorized preparation method of high k dielectric layer water-based indium oxide film, is characterized in that specifically comprising following processing step:
(1), the preparation of precursor solution: by acetylacetone,2,4-pentanedione zirconium Zr (C 5h 7o 2) 4be dissolved in dimethyl formamide, add with the monoethanolamine of acetylacetone,2,4-pentanedione zirconium equimolar amounts as stabilizer simultaneously, stir the precursor solution that forms clear for 1-24 hour at 20-100 ℃ of lower magnetic force, wherein zirconia precursor solution concentration is 0.01-0.5M, zirconium Zr 4+molar content be 0.01-0.9; The volume ratio of monoethanolamine and dimethyl formamide is 1:1-10;
(2), the preparation of film sample: using plasma cleaning method cleans low-resistance surface of silicon, on low-resistance silicon substrate after cleaning, adopt the precursor solution of conventional sol-gel technique spin coating step (1) preparation to obtain sample, after spin coating finishes, sample is put into and under high-pressure mercury lamp, carries out ultraviolet lighting and process and obtain the sample after photo-annealing, realize the photodissociation of sample and solidify; The sample after photo-annealing is carried out to 300 ℃ of process annealing 1-3 hour, the interlayer of avoiding semiconductor channel layer process annealing process the to bring phenomenon of dissolving each other, obtains film sample again;
(3), In 2o 3the preparation of channel layer: by indium nitrate In (NO 3) 3be dissolved in distilled water the In that the concentration that at room temperature stirs 1-24 hour formation clear is 0.1-0.3mol/L 2o 3aqueous solution; Then the film sample surface obtaining in step (2) utilizes sol-gel technique to adopt commercially available sol evenning machine spin coating In 2o 3aqueous solution, first even glue 4-8 second under 400-600 rev/min, then under 2000-4000 rev/min even glue 15-30 second, spin coating number of times is 1-3 time, at every turn spin coating thickness 5-10nm; Film sample after spin coating is put into 120-150 ℃ burned and is cured and puts into Muffle furnace after processing and carry out 200-300 ℃ of process annealing and process 1-3 hour, make In 2o 3thickness is the In of 5-30nm 2o 3film, prepares In 2o 3channel layer;
(4), the preparation of source, drain electrode: utilize conventional Vacuum sublimation to utilize stainless steel mask plate at In 2o 3preparation source, drain electrode above channel layer, obtain based on ultra-thin ZrO xthe water-based In of high k dielectric layer 2o 3thin-film transistor.
2. the transistorized preparation method of high k dielectric layer water-based indium oxide film according to claim 1, it is characterized in that the plasma clean method relating in step (2) adopts oxygen or argon gas as purge gas, its power is 20-60Watt, scavenging period is 20-200s, and the intake of working gas is 20-50SCCM; When preparing film sample, use sol evenning machine spin coating, first even glue 4-8 second under 400-600 rev/min, then under 3000-6000 rev/min even glue 15-25 second; Spin coating number of times is 1-5 time, and the film thickness of each spin coating is 4-8nm; The power of high-pressure mercury lamp is 1-2KW, and the dominant wavelength of ultraviolet light is 365nm, and light application time is 20-40 minute, high-pressure mercury lamp light source distance sample surfaces 5-100cm.
3. the transistorized preparation method of high k dielectric layer water-based indium oxide film according to claim 1, is characterized in that the electrode raceway groove length-width ratio of thin-film transistor prepared by step (4) is 1:4-20, and thermal evaporation electric current is 30-50A; The source making, leak electricity very metal A l or Au electrode, thickness of electrode is 50-200nm.
CN201410264881.8A 2014-06-13 2014-06-13 A kind of preparation method of high k dielectric layer aqueous indium oxide film transistor Expired - Fee Related CN104009093B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201410264881.8A CN104009093B (en) 2014-06-13 2014-06-13 A kind of preparation method of high k dielectric layer aqueous indium oxide film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410264881.8A CN104009093B (en) 2014-06-13 2014-06-13 A kind of preparation method of high k dielectric layer aqueous indium oxide film transistor

Publications (2)

Publication Number Publication Date
CN104009093A true CN104009093A (en) 2014-08-27
CN104009093B CN104009093B (en) 2016-08-31

Family

ID=51369675

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410264881.8A Expired - Fee Related CN104009093B (en) 2014-06-13 2014-06-13 A kind of preparation method of high k dielectric layer aqueous indium oxide film transistor

Country Status (1)

Country Link
CN (1) CN104009093B (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104201112A (en) * 2014-09-28 2014-12-10 青岛大学 Preparation method for water solution thin film transistor
CN104485283A (en) * 2014-09-10 2015-04-01 友达光电股份有限公司 Method of manufacturing thin film transistor and apparatus for manufacturing thin film transistor
CN104934327A (en) * 2015-05-20 2015-09-23 青岛大学 Method for preparing thin-film transistor based on scandia high-k dielectric layer
CN104945962A (en) * 2015-05-13 2015-09-30 上海交通大学 Metal oxide protective film and preparation method thereof
CN105428247A (en) * 2016-01-18 2016-03-23 青岛大学 Preparation method of thin film transistor based on water-based ultrathin ZrO2 high k dielectric layer
CN105489770A (en) * 2016-01-08 2016-04-13 武汉大学 Indium oxide electronic transmission layer planar perovskite photovoltaic battery and preparation method therefor
CN105489486A (en) * 2016-01-18 2016-04-13 青岛大学 Method for preparing thin-film transistor based on ultra-thin magnesium oxide high-k dielectric layer
CN105552130A (en) * 2016-01-18 2016-05-04 青岛大学 Preparation method for thin film transistor based on ultra-thin Li2O high-k dielectric layer
CN106431397A (en) * 2016-09-14 2017-02-22 齐鲁工业大学 Low-temperature solution preparation method of high-dielectric zirconium oxide thin film
CN106783564A (en) * 2016-09-14 2017-05-31 齐鲁工业大学 A kind of cryogenic fluid preparation method of indium oxide transparent semiconductor film
CN108232013A (en) * 2017-11-29 2018-06-29 华南师范大学 The method for preparing zirconia film and flexible transistor
CN108493098A (en) * 2018-04-17 2018-09-04 南京邮电大学 Preparation method based on low temperature solution polycondensation p-type metal iodine compound film transistor
CN110517958A (en) * 2019-08-09 2019-11-29 中山大学 A kind of preparation method of oxide thin film transistor

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050051770A1 (en) * 2003-09-04 2005-03-10 Hitachi, Ltd. Electrode substrate, thin film transistor, display device and their production
CN101290883A (en) * 2008-05-29 2008-10-22 南京大学 Soft chemistry method for preparing ultrathin HfO* or ZrO* gate dielectric membrane
JP2009267192A (en) * 2008-04-28 2009-11-12 Mitsubishi Electric Corp Manufacturing method for semiconductor device and semiconductor manufacturing device
EP2339638A1 (en) * 2009-12-24 2011-06-29 Samsung Electronics Co., Ltd. Transistor
CN103779427A (en) * 2014-02-26 2014-05-07 华南理工大学 Oxide thin film transistor and preparation method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050051770A1 (en) * 2003-09-04 2005-03-10 Hitachi, Ltd. Electrode substrate, thin film transistor, display device and their production
JP2009267192A (en) * 2008-04-28 2009-11-12 Mitsubishi Electric Corp Manufacturing method for semiconductor device and semiconductor manufacturing device
CN101290883A (en) * 2008-05-29 2008-10-22 南京大学 Soft chemistry method for preparing ultrathin HfO* or ZrO* gate dielectric membrane
EP2339638A1 (en) * 2009-12-24 2011-06-29 Samsung Electronics Co., Ltd. Transistor
CN103779427A (en) * 2014-02-26 2014-05-07 华南理工大学 Oxide thin film transistor and preparation method thereof

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104485283B (en) * 2014-09-10 2017-08-15 友达光电股份有限公司 Method of manufacturing thin film transistor and apparatus for manufacturing thin film transistor
CN104485283A (en) * 2014-09-10 2015-04-01 友达光电股份有限公司 Method of manufacturing thin film transistor and apparatus for manufacturing thin film transistor
CN104201112A (en) * 2014-09-28 2014-12-10 青岛大学 Preparation method for water solution thin film transistor
CN104945962A (en) * 2015-05-13 2015-09-30 上海交通大学 Metal oxide protective film and preparation method thereof
CN104934327A (en) * 2015-05-20 2015-09-23 青岛大学 Method for preparing thin-film transistor based on scandia high-k dielectric layer
CN105489770A (en) * 2016-01-08 2016-04-13 武汉大学 Indium oxide electronic transmission layer planar perovskite photovoltaic battery and preparation method therefor
CN105552130B (en) * 2016-01-18 2018-08-10 青岛大学 A kind of preparation method based on the high k dielectric layer thin film transistor (TFT) of ultra-thin lithia
CN105552130A (en) * 2016-01-18 2016-05-04 青岛大学 Preparation method for thin film transistor based on ultra-thin Li2O high-k dielectric layer
CN105489486A (en) * 2016-01-18 2016-04-13 青岛大学 Method for preparing thin-film transistor based on ultra-thin magnesium oxide high-k dielectric layer
CN105428247A (en) * 2016-01-18 2016-03-23 青岛大学 Preparation method of thin film transistor based on water-based ultrathin ZrO2 high k dielectric layer
CN105428247B (en) * 2016-01-18 2018-08-10 青岛大学 One kind being based on aqueous ultra-thin ZrO2The film crystal tube preparation method of high k dielectric layer
CN106431397A (en) * 2016-09-14 2017-02-22 齐鲁工业大学 Low-temperature solution preparation method of high-dielectric zirconium oxide thin film
CN106783564A (en) * 2016-09-14 2017-05-31 齐鲁工业大学 A kind of cryogenic fluid preparation method of indium oxide transparent semiconductor film
CN108232013A (en) * 2017-11-29 2018-06-29 华南师范大学 The method for preparing zirconia film and flexible transistor
CN108232013B (en) * 2017-11-29 2019-12-03 华南师范大学 The method for preparing zirconia film and flexible transistor
CN108493098A (en) * 2018-04-17 2018-09-04 南京邮电大学 Preparation method based on low temperature solution polycondensation p-type metal iodine compound film transistor
CN110517958A (en) * 2019-08-09 2019-11-29 中山大学 A kind of preparation method of oxide thin film transistor

Also Published As

Publication number Publication date
CN104009093B (en) 2016-08-31

Similar Documents

Publication Publication Date Title
CN104009093A (en) Method for manufacturing high-k dielectric layer water-based indium oxide thin film transistors
CN104201112A (en) Preparation method for water solution thin film transistor
CN105489486A (en) Method for preparing thin-film transistor based on ultra-thin magnesium oxide high-k dielectric layer
CN105428247B (en) One kind being based on aqueous ultra-thin ZrO2The film crystal tube preparation method of high k dielectric layer
Jeong et al. Photo-patternable ZnO thin films based on cross-linked zinc acrylate for organic/inorganic hybrid complementary inverters
CN103928350B (en) The transistorized preparation method of a kind of double channel layer film
US10032923B2 (en) Metal oxide thin film, method for manufacturing the same, and solution for metal oxide thin film
CN106025067A (en) Method for generating perovskite film through solution method and device application thereof
Jiang et al. High carrier mobility low-voltage ZnO thin film transistors fabricated at a low temperature via solution processing
Park et al. Significant performance improvement of solution-processed metal oxide transistors by ligand dissociation through coupled temperature–time treatment of aqueous precursors
CN101388335A (en) Preparation for ferroelectric material of quartz/lanthanum nickelate/bismuth ferrite-lead titanate
Zhang et al. Balanced performance improvement of a-InGaZnO thin-film transistors using ALD-derived Al2O3-passivated high-k HfGdOx dielectrics
CN103022077B (en) A kind of OLED device of oxycompound thin-film transistor
CN104934327A (en) Method for preparing thin-film transistor based on scandia high-k dielectric layer
Lee et al. Enhancement of the electrical performance and bias stability of RF-sputtered indium tin zinc oxide thin-film transistors with vertical stoichiometric oxygen control
Zhu et al. Water-derived all-oxide thin-film transistors with ZrAlO x gate dielectrics and exploration in digital circuits
Shan et al. Multi-stacking indium zinc oxide thin-film transistors post-annealed by femtosecond laser
CN108417495A (en) A kind of preparation of the thin film transistor (TFT) of metal oxide passivation
CN106952828A (en) A kind of preparation method of p-type metal oxide thin-film transistor
CN108987469B (en) Amorphous ZnMgSnO thin film and thin film transistor and preparation method thereof
CN106410041B (en) Polymer solar battery and preparation method
CN108493098A (en) Preparation method based on low temperature solution polycondensation p-type metal iodine compound film transistor
CN105742188B (en) Method for preparing p-type oxide thin film material by polyol reduction technology
WO2017143626A1 (en) Preparation method for oxide thin film, and thin film transistor
CN103346264A (en) Nano-zinc oxide film preparation method and organic solar cell preparation method

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20160831

Termination date: 20210613