CN104008984A - Method and system for detecting semiconductor device, semiconductor device and manufacturing method thereof - Google Patents
Method and system for detecting semiconductor device, semiconductor device and manufacturing method thereof Download PDFInfo
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- CN104008984A CN104008984A CN201410059737.0A CN201410059737A CN104008984A CN 104008984 A CN104008984 A CN 104008984A CN 201410059737 A CN201410059737 A CN 201410059737A CN 104008984 A CN104008984 A CN 104008984A
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N23/00—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00
- G01N23/22—Investigating or analysing materials by the use of wave or particle radiation, e.g. X-rays or neutrons, not covered by groups G01N3/00 – G01N17/00, G01N21/00 or G01N22/00 by measuring secondary emission from the material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N2223/00—Investigating materials by wave or particle radiation
- G01N2223/60—Specific applications or type of materials
- G01N2223/646—Specific applications or type of materials flaws, defects
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Health & Medical Sciences (AREA)
- Physics & Mathematics (AREA)
- Automation & Control Theory (AREA)
- Life Sciences & Earth Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Biochemistry (AREA)
- General Health & Medical Sciences (AREA)
- General Physics & Mathematics (AREA)
- Immunology (AREA)
- Pathology (AREA)
Abstract
The invention relates to a method and a system for detecting a semiconductor device, the semiconductor device and a manufacturing method thereof. Methods and systems for detecting defects in a semiconductor, semiconductor device, or substrate are provided. Semiconductors, semiconductor devices, or substrates having the new test patterns and/or designs are also provided. Wherein a semiconductor, semiconductor device or substrate having a plurality of circuit patterns is subjected to a reaction. The plurality of line patterns correspond to a response stimulus (e.g., electron beam radiation). The response stimulus may include an electron beam radiation, and the response produces image data that may be collected and processed to produce an image indicative of surface and/or internal defects.
Description
Technical field
The present invention relates to a kind of semiconductor device.Particularly relate to a kind of novel test pattern design and a kind of method of using this test pattern design defect in depositing metal layers with identification.
Background technology
The manufacture of semiconductor device normally needs to set up the line pattern of (creating) conducting metal, to interconnect the different layers of semiconductor device.This may relate to a kind of " embedded-type technical ".Therefore, line pattern may be formed on the dielectric layer on a surface of semiconductor device or in a dielectric layer on a surface of semiconductor device.For instance, line pattern can and be filled a conducting metal and make by etching one insulating barrier.One selective removal technique (being for example that mechanicalness is ground or chemical machinery grinds) can be used to guarantee that conducting metal is arranged in etched line pattern.
The persistent trend of semiconductor industry is towards high device density, but not affect the execution usefulness development of device.The arrangement of semiconductors size being formed on substrate (integral body is considered as chip) is contracted to time micron (sub-micron) grade constantly to reach this object.For instance, interval and the diameter of the width of the circuit that is connected and interval, contact hole, and geometric jacquard patterning unit surface (being for example corner or edge) is all and continues the feature that becomes less.For example, when conducting metal (being copper) is deposited on these narrow/little connected circuits, conducting metal may be filled in by halves in whole diameters of groove and cause the formation of a gap (gap) or a recess (pit).
Moreover due to this kind of situation, copper has the tendency that forms bridging line (oxide bridging line) between dielectric layer around or insulating barrier.This causes the increase of the conductivity of conductor wire/layer.And oxide bridging line (oxide bridge) may cause the incomplete division to dielectric layer (incomplete separation) from conductor wire/layer.This causes the pollution of dielectric layer or oxide layer.The dielectric layer having polluted may make the insulation characterisitic of dielectric layer reduce, and causes short circuit or leakage current.
For example, in order to detect the conventional method of defect (being gap, recess or oxide bridging line), be conventionally confined to be merely able to detect the optical detection apparatus of blemish.In order to detect the additive method of internal flaw, conventionally need defect detecting technique tediously long and consuming time.In measuring semiconductor conductive layer, the improvement method of defect is needed in this field.In addition, in order to reduce the cost relevant for thermometrically, need to develop a kind of can improve semiconductor fabrication process efficiency, fast, (in-line) detection method on line.The art also needs to develop the reliable method of improving defects detection.
Summary of the invention
The object of the invention is to, a kind of method and system, semiconductor device and manufacture method thereof of new detecting semiconductor device is provided, technical problem to be solved is to make it can effectively detect the defect in semiconductor device metal layer, is very suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.The method of a kind of detecting (inspect) semiconductor device proposing according to the present invention, the method comprises the following steps.Provide and there is the semiconductor device that is arranged at a plurality of line patterns on a substrate, expose a plurality of line patterns in a response stimulus (responsive stimuli), and measure a plurality of line patterns to a reaction of response stimulus.The reaction of a plurality of line patterns can be for example to point out there be (presence) or lack (absence) of a blemish, an internal flaw (being for example a recess or monoxide bridging line) or combination.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The method of aforesaid detecting semiconductor device, wherein a plurality of line patterns connect by least one interconnection line pattern.
The method of aforesaid detecting semiconductor device, wherein those line patterns are parallel to each other.
The method of aforesaid detecting semiconductor device, wherein this interconnection line pattern is perpendicular to those line patterns.
The method of aforesaid detecting semiconductor device, wherein this interconnection line pattern is the end (terminus) close to those line patterns.
The method of aforesaid detecting semiconductor device, wherein the method is (in-line), continuity method on a line.
The method of aforesaid detecting semiconductor device, wherein response stimulus comprise a light (irradiation), one conduction (conductance), a magnetic resonance (magnetic resonance), an acoustic stimulation (acoustical stimulation) and an electrostimulation (electrical stimulation) at least one of them.
The method of aforesaid detecting semiconductor device, wherein in certain embodiments, response stimulus comprises an electron beam irradiation (electron beam radiation).
The method of aforesaid detecting semiconductor device, also comprises and in electron beam irradiation, collects image data, and produces at least one image data, and image data shows a blemish, an internal flaw or its combination.
The method of aforesaid detecting semiconductor device, wherein this electron beam irradiation is to provide by an electron beam detecting instrument, and this electron beam detecting instrument is a jumping characteristic electron beam detecting instrument (leap electron beam inspection tool) or continuity electron beam detecting instrument (continuous electron beam inspection tool).
The method of aforesaid detecting semiconductor device, also comprises that application one external electrical field is to the step of semiconductor device.Application external electrical field is so that improve the contrast of development image.
The method of aforesaid detecting semiconductor device, wherein a plurality of line patterns are included in a plurality of grooves on semiconductor device and are deposited at least one conducting metal of a plurality of grooves.
The object of the invention to solve the technical problems also realizes by the following technical solutions.A kind of semiconductor device proposing according to the present invention.This semiconductor device comprises a substrate, a dielectric layer, a plurality of conductive pattern and at least one interconnection line pattern.A plurality of conductive patterns are deposited in dielectric layer.At least one interconnection line pattern is connected in a plurality of conducting wires pattern.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid semiconductor device, wherein a plurality of conducting wires pattern is parallel to each other.
Aforesaid semiconductor device, wherein at least one connected line pattern is to be close to an end (terminus) of a plurality of conducting wires pattern and perpendicular to a plurality of conducting wires pattern.
Aforesaid semiconductor device, wherein this dielectric layer comprise silicon monoxide (silicon oxide) and a silicon nitride (silicon nitride) at least one of them.
Aforesaid semiconductor device, wherein those conducting wire patterns comprise copper.The object of the invention to solve the technical problems realizes in addition more by the following technical solutions.A kind of method of manufacturing semiconductor device proposing according to the present invention, the method comprises the following steps.One substrate is provided.Form at least one dielectric layer on substrate.A plurality of grooves of etching are in dielectric layer.At least one interconnection channel of etching is in the dielectric layer that interconnects a plurality of grooves.Deposit an electric conducting material in a plurality of grooves and at least one interconnection channel.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The method of aforesaid manufacture semiconductor device, wherein electric conducting material is the group that selects free aluminium, copper, tungsten, gold, any its alloy and bond thereof to form.
The method of aforesaid manufacture semiconductor device, wherein those grooves are to be arranged in parallel.
The method of aforesaid manufacture semiconductor device, wherein this at least one interconnection channel is perpendicular to those grooves.
The method of aforesaid manufacture semiconductor device, wherein this at least one interconnection channel is an end that is close to those grooves.
The object of the invention to solve the technical problems also realizes in addition by the following technical solutions.The method of the detecting semiconductor device proposing according to the present invention.The method comprises the following steps.Semiconductor device is provided, semiconductor device has a substrate, a dielectric layer, a plurality of conducting wires pattern and at least one interconnect conductive circuit pattern, a plurality of conducting wires pattern setting is in dielectric layer, and at least one interconnect conductive circuit pattern is in order to be connected in conducting wire pattern.With an electron beam irradiation, irradiate semiconductor device.Be received from the image data of light (irradiation).The semiconductor device image that produces self imaging data, wherein image identification (identify) goes out defect.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
The method of aforesaid detecting semiconductor device, wherein the method is (in-line) on line, continuation method.
The object of the invention to solve the technical problems also realizes in addition by the following technical solutions.What according to the present invention, propose is direct in order to detect at least equipment of one of them of an internal flaw and a blemish of semiconductor device.
The object of the invention to solve the technical problems also realizes in addition by the following technical solutions.What according to the present invention, propose is a kind of in order to detect the system of defect in semiconductor device.Wherein semiconductor device has a test pattern.Semiconductor device also comprises a substrate, is arranged at the dielectric layer on substrate, a plurality of conducting wires pattern, and at least one interconnection line pattern.A plurality of conducting wires pattern setting is in dielectric layer, and at least one interconnection line pattern is in order to be connected in conducting wire pattern.System also comprises providing the irradiation unit of energy (energy) to test pattern, a receiving system and a device for image.Receiving system is accepted data from irradiation unit.Device for image shows arbitrary image wherein of a blemish, an internal flaw and combination thereof in semiconductor device.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further.
Aforesaid in order to detect the system of defect in semiconductor device, also comprise an external electrical field generator that is close to substrate.
The present invention compared with prior art has obvious advantage and beneficial effect.By technique scheme, the present invention detects the method and system of semiconductor device, the design of the check pattern of semiconductor device semiconductor device and manufacture thereof utilize method at least to have following advantages and beneficial effect: the method and system of detecting semiconductor device of the present invention, semiconductor device and manufacture method thereof can detect the defect in semiconductor device metal layer effectively.
In sum, the invention relates to a kind of method and system, semiconductor device and manufacture method thereof of detecting semiconductor device.It provides in order to detect the method and system of the defect in semiconductor, semiconductor device or substrate.Semiconductor, semiconductor device or the substrate with new shape test pattern and/or design are also provided.Semiconductor, semiconductor device or the substrate wherein with a plurality of line patterns produce a reaction.A plurality of line patterns are corresponding to a response stimulus thing (as electron beam irradiation).Response stimulus thing can comprise an electron beam irradiation, and this reaction generation one image data, and this image data can be collected and process to produce to point out the image of surface and/or internal flaw.The present invention has significant progress technically, has obvious good effect, is really a new and innovative, progressive, practical new design.
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to better understand technological means of the present invention, and can be implemented according to the content of specification, and for above and other object of the present invention, feature and advantage can be become apparent, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
Figure 1A is the schematic diagram illustrating according to having the semiconductor device of oxidation groove structure in embodiments of the invention.
Figure 1B is the generalized section illustrating in Figure 1A along the semiconductor device of B-B hatching.
Fig. 2 A is the generalized section illustrating according to having the semiconductor device of the conducting metal that is deposited on groove structure in embodiments of the invention.
Fig. 2 B is the generalized section illustrating in Fig. 2 A along the semiconductor device of B-B hatching.
Fig. 3 A is the schematic diagram of embodiment that illustrates the novel test pattern design of display section (certain) defect.
Fig. 3 B is the schematic diagram illustrating according to embodiments of the invention electron beam irradiation image of defect test pattern in Fig. 3 A.
Fig. 4 A illustrates according to embodiments of the invention to use the schematic diagram that detects an electron-beam inspection apparatus of defect in semiconductor device.
Fig. 4 B is the schematic diagram of an electron beam irradiation of the embodiment of test pattern of the present invention design.
Fig. 5 is the energy diagram that illustrates anodal pattern in part embodiment of the present invention (positive mode) and negative pole pattern (negative mode) electron beam irradiation.
Fig. 6 A-Fig. 6 E illustrates according to using a great-jump-forward scan method to detect the block diagram of defect in embodiments of the invention.
Fig. 7 A-Fig. 7 E illustrates according to using a continuity scan method to detect the block diagram of defect in embodiments of the invention.
1: substrate 2: dielectric layer
3: circuit groove 4: conducting wire
Within 5: one, interconnection channel 6: defect
7: damaged line 9: conductive interconnect structures
10: test pattern border 16: fragment shade
17: fragment 100: test pattern
200: electron beam equipment 210: negative electrode
220: capacitor lens 230: main light beam
240: light beam extinguishing means 250: astigmatic aberration compensator
260: hole 270: lens
280: reflective mirror 290: reflective mirror in lens
300: backscattering electronics 310: horizontal plane
400: test pattern 410:G
420: dark fragment 430: external electrical field
440: surface 450: positive charge
E1: the first ENERGY E 2: the second energy
Embodiment
For further setting forth the present invention, reach technological means and the effect that predetermined goal of the invention is taked, below in conjunction with accompanying drawing and preferred embodiment, the method and system of detecting semiconductor device that propose according to the present invention,, the design of the check pattern of semiconductor device semiconductor device and manufacture thereof utilize its embodiment of method, method, step, structure, feature and effect thereof, are described in detail as follows.
As used at specification and in claims, unless context clearly represent, otherwise singulative comprises most words and phrases.For example, mentioning of " semiconductor device " comprises a plurality of this semiconductor devices.
Although adopt certain party term at this, they are used with a kind of common and descriptive meaning, rather than the object in order to limit only.The all buzz words that comprise as used in this technology and science buzz word have one of them identical meaning of conventionally understanding of technical staff of haveing the knack of the technology with the technical field of the invention, unless a buzz word is otherwise defined.But we will further understand, for example defined those buzz words of general dictionary should be construed as having and as having, have the knack of the technical field of the invention and have the knack of the meaning that the technical staff of the technology understands conventionally.We will further understand, for example defined those buzz words of general dictionary should be construed as having the meaning that the meaning in the context disclosing with the present invention in correlation technique with them conforms to.Unless the present invention is in this clear and definite definition like this, otherwise this general buzz word will can not explained with meaning Utopian or exceedingly form.
The invention relates to checkout equipment and the method for inside and/or blemish, especially in semiconductor device manufacturing process.The present invention also designs (test pattern design) and manufactures the semiconductor device with this design relevant for the novel test pattern on semiconductor device or substrate.
As used herein one " semiconductor " or " semiconductor device " word refer to semiconductor device or semiconductor substrate.In general, these comprise the known device of technical staff or the substrate in semiconductor applications with common knowledge.Future may develop and so far unknown semiconductor device also can be regarded as semiconductor of the present invention.
As used herein " semiconductor substrate " word refers to any structure (construction) that comprises semiconductor material, and semi-conducting material comprises (but being not limited to this) whole (bulk) semi-conducting material (being for example semiconductor crystal wafer (separately or the assembly that comprises other materials that are located thereon)) and semiconductor material layer (separately or the assembly that comprises other materials)." substrate " word refers to any supporting construction (supporting structure), and supporting construction comprises that (but being not limited to this) is further described in semiconductor substrate herein.
In certain embodiments, the method for invention can be applied to part semiconductor device.Method of the present invention goes for having in this area the known part semiconductor device of technical staff of common knowledge.In some embodiments of the invention, semiconductor device can be semiconductor memory storage.Semiconductor memory can be a random access memory (random access memory, RAM) device or a read-only memory (read only memory, ROM) device.Random access memory device can be selected from Dynamic Random Access Memory (dynamic random access memory, DRAM), the Dynamic Random Access Memory of fast page mode (fast page mode DRAM, FPM DRAM), growth data output Dynamic Random Access Memory (extended data out DRAM, EDO DRAM), video random access memory device (video random access memory, VRAM), synchronous dynamic random-access memory body (synchronous dynamic random access memory, SDRAM), double data rate synchronous dynamic random-access memory body (double date rate SDRAM, DDR SDRAM), Rambus Dynamic Random Access Memory (Rambus DRAM, RDRAM), synchronizing pattern random access memory (synchronous graphics RAM, SGRAM), pseudo-static random-access memory internal body (pseudostatic RAM, PSRAM), magnetic-resistance random access memory body (mageneto resistive RAM, MRAM) and static random memory body (static RAM, SRAM) group forming.Read-only memory device can be selected from read-only memory able to programme (programmable ROM, PROM), erasable programmable read-only memory (erasable programmable read only memory, EPROM) and the group that forms of electronics erasable programmable read-only memory (electrically erasable programmable ROM, EEPROM).In some embodiments of the invention, semiconductor memory is a quick flashing memory device.
In the high density technique of semiconductor device structure, mosaic technology (damascene process) can, in order to improve the interconnective external form of metal, namely be deposited in groove to form the conducting metal of a metal interconnected circuit pattern.In mosaic technology, a conducting metal can be deposited on the groove being formed in a dielectric layer.Groove can be etched in dielectric layer.One metal all sidedly (blanket) is deposited on the groove being formed in dielectric layer.The metal that is placed in any part deposition of groove outside can be removed, for example, be to utilize a pure chemistry grinding technics (a purely mechanical polishing process), a CMP (Chemical Mechanical Polishing) process (a chemical mechanical planarization process) and/or other flatening process.The part embodiment according to the present invention, because each sidewall external form mutually linking is to define rather than define by patterned metal layer by patterning and etching dielectric layer, mosaic technology can be (desirable) being applicable to.By metal etching process make for reaching the vertical in fact difficulty that interconnects sidewall, in the field of semiconductor technology, be widely known by the people.Moreover a mosaic technology can cause substantially more smooth semiconductor surface, a continuous interconnect height (subsequent interconnect level) can be manufactured in more smooth in fact semiconductor surface top.
In general, semiconductor substrate can comprise inertia dielectric layer (inert dielectric layers) and conductive layer.For instance, some embodiments of the present invention can relate to and have the bond (as: silicon metal, silicon dioxide) that is selected from GaAs (GaAs), germanium (germanium), silicon (silicon), SiGe (silicon germanium), lithium niobate (lithium niobate), comprises silicon, and the semiconductor substrate of the group that forms of bond.In part embodiment of the present invention, semiconductor substrate silicon is semiconductor wafer, particularly a Silicon Wafer." " word means semiconductor structure, a substrate or a device to wafer, for example, be that boundary is in any state of the art of semiconductor device.Dielectric material can be for example to comprise the silicon that contains spin-on glasses (spin-on glass), spin-on glasses is for example alkoxy silane high molecular polymer (alkoxy silane polymer), siloxanes high molecular polymer (siloxane polymer), half siloxanes high molecular polymer (silsesquioxane polymer), stretch aryl ether (poly, arylene ether), fluoridize and stretch aryl ether (fluorinated poly, arylene ether), other polymerisation mediums (polymer dielectrics), nano-stephanoporate silicon dioxide (nanoporous silica) or its mixture.
Dielectric layer can form by any suitable technology.For example chemical vapour deposition (CVD) (chemical vapor deposition, CVD), plasma auxiliary chemical vapor deposition (plasma enhanced chemical vapor deposition, PECVD), low-pressure chemical vapor deposition (low pressure chemical vapor deposition, LPCVD), high-pressure chemical vapor deposition (high pressure chemical vapor deposition, HPCVD).Polymeric media also can be by using rotary coating (spin coating), dip-coating (dip-coating), spraying plating (spraying) or roller coating (roller coating) to form.
Dielectric layer can then provide selective etch to produce interface channel (contact tunnel)/groove (trench)/groove (groove)/opening (opening) and/or perforation (via).Etching can be by completing with any suitable etching solution.It is for example that a wet process (wet process), a dry process (dry process) and any its combined process carry out etching that oxide layer can be utilized.For instance, wet oxygen etching can complete in hydrofluoric acid (hydrofluoric acid, the HF) solution that has buffering or diluted.Hydrofluoric acid can be one completely in the method for domination and have very much optionally an etching layer of oxide layer in situation.The etched example of dry oxidation comprises that adopting fluorine carbon (fluorocarbon) gas (is for example tetrafluoromethane (tetrafluoromethane, CF4), perfluoroethane (hexafluoroethane, C2F6), fluoroform (fluoroform, CHF3) or octafluorobutane (ctaflurocyclobutane, C4F8)) plasma process (plasma-based process).This gas also can comprise oxygen (O2), nitrogen (N2), argon gas (Ar), helium (He) is any or its any composition.Dry or wet etching process of the present invention can example in this way on the platform of (batch) and/or single wafer by the gross.
After groove/recess forms, groove/recess is filled an electric conducting material.Electric conducting material can be any suitable material, for example, be a conducting metal, conductive metal alloy, conducting metal oxide, conducting polymer thin film, semi-conducting material or other similar materials.The concrete example of electric conducting material comprises any aluminium (aluminum), chromium (chromium), copper (copper), germanium (germanium), gold (gold), magnesium (magnesium), manganese (manganese), tungsten (tungsten), zinc (zinc), any its alloy or any its bond.Any technology of knowing in the art can be in order to filling groove or opening.Exemplary method can comprise plating, electroless-plating filling (electroless filling), sputter (sputtering), evaporation (evaporation), deposition (deposition) and similar approach thereof, and can be in order to filling groove or opening.
No matter adopt the method for which kind of deposits conductive material, the manufacture of semiconductor device needs dark and narrow contact circuit substantially.Therefore, inevitably in this process, can form surface and internal flaw.In the manufacturing process of semiconductor device, blemish can be any common defect.For instance, blemish can be any inhomogeneous or any inhomogeneous bond, the bond or the scratch that polluted by other materials.In the manufacturing process of semiconductor device, internal flaw can be to comprise being formed at inner any defect to conducting wire surface/pattern.For example, when using a conventional surface defect inspection method, internal flaw may be the defect that cannot be detected.These internal flaws may affect the conductivity that circulates in conducting wire.For instance, be for example the usefulness that the internal flaw of " recess (pit) " or " oxide bridging line (oxide bridge) " can seriously limit semiconductor device or semiconductor substrate." recess " represents gap (gap) or space (void) or crack (break) being formed in a smithcraft in a conducting wire in this article." oxide bridging line " means to be formed at semiconductor to the bridging line between conducting wire.For instance, monoxide bridging line can connect dielectric layer and falling property layer forms by conducting wire.Therefore oxide bridging line may not can be detected when using conventional surface detection technique.
An aspect of of the present present invention also comprises the line pattern being formed on semiconductor device or semiconductor substrate.In specific embodiments, novel line design (line design) or pattern are to be formed on the surface of semiconductor substrate or device.Novel line pattern can contribute to be used in the structure of different inner connecting structures and conductive pattern, for example, be metallic circuit, mosaic texture (damascene structures), dual-damascene structure (dual damascene structures), metal plug (metal plug), distribution (wiring), circuit (circuit) and similar pattern.The technical staff in this area with common knowledge is appreciated that it is for example that a metal etching process (the namely light lithography of plated metal, and this metal of etching that continuing) or a mosaic technology (damascene process) form that pattern of the present invention can utilize.In some embodiments of the invention, can use the mosaic technology of correction, for example, be a dual-damascene technics.
Figure 1A and Fig. 2 A have illustrated according to the generalized section of manufacturing semiconductor device in one embodiment of the invention.Figure 1B and Fig. 2 B have illustrated respectively in Figure 1A and Fig. 2 A the generalized section along B-B hatching.Refer to shown in Figure 1A to Fig. 2 B, provide substrate 1, one dielectric layer 2 to be formed on substrate 1, at least one channel shaped is formed on substrate 1.Shown in Figure 1B, by a test pattern boundary line, (test pattern boundary) 10 defines test pattern (test pattern).Groove in dielectric layer 2 comprises a plurality of circuit grooves 3 that are parallel to each other continuously and an interconnection channel 5, and wherein interconnection channel 5 is connected in a plurality of circuit grooves 3.According to embodiment of the present invention, interconnection channel 5 is vertical and is close to the end (terminus) of a plurality of circuit grooves 3.
Refer to shown in Fig. 2 A to Fig. 2 B, according to one embodiment of the invention, interconnection channel 5 and a plurality of circuit groove 3 are all filled an electric conducting material, to form a conducting wire 4 and a conductive interconnect structures 9.Conducting wire 4 and conductive interconnect structures 9 are in order to form the test pattern 100 of one embodiment of the invention.Electric conducting material can comprise a conducting metal, electrical conductivity alloy, metal bond or metal alloy.In part embodiment of the present invention, copper can be used as conducting metal.
According to an aspect of the present invention, a plurality of conducting wire of the present invention is exposed to a response stimulus (responsive stimuli).In another embodiment of the present invention, semiconductor device, semiconductor substrate (namely semiconductor crystal wafer) can be exposed to response stimulus thing.Response stimulus can comprise any known stimulation in affiliated technical field, and stimulation can be brought out a reaction from conducting wire pattern.In some embodiments of the invention, response stimulus comprise a light (irradiation), conduction (conductance), a nulcear magnetic resonance (NMR) (magnetic resonance), a sound stimulate (acoustical stimulation) and an electrostimulation (electrical stimulation) at least one of them.
In one embodiment of this invention, a plurality of conducting wires pattern is to irradiate with an electron beam irradiation (electron beam radiation).In some embodiments of the invention, semiconductor device and/or substrate are to irradiate with an electron beam irradiation.
Further, according to embodiments of the invention, can use a surface scan technology (surface scanning technique).For instance, the object in being detected or the surface of object can be irradiated by an electron beam irradiation, and the quantity of the image data secondary electron that can penetrate from object surface obtains.The quantity of the secondary electron penetrating from object surface is characteristic and changing per sample.The lip-deep pattern or the design (being for example semiconductor substrate) that are formed on object can be detected based on image data provided by the present invention in a high mode of production (throughput fashion).
One scanning type electron microscope (Scanning Electron Microscopy, SEM) can be used in part embodiment of the present invention.Therefore, an electron beam can concentrate on an object and irradiate an electron beam, and object is for example semiconductor device.It is upper that semiconductor device (being for example a silicon) can be placed on a step (stage), and step moves toward a vertical direction of electron beam scanning direction.Use is concentrated the light of electron beam may cause secondary electron and is penetrated in semiconductor device.Secondary electron can be used the detector (PIN diode type detector) of a detector (scintillator adds photomultiplier) or semiconductor type to detect.Can be in conjunction with the quantity (signal strength signal intensity) of coordinate and the secondary electron of electron beam irradiation position to produce an image.Collected image data can be stored in storage element.Optionally, image data can be output to a cathode ray tube.Thereby the image obtaining may be displayed on the defect in semiconductor device.In particular, method of the present invention can show it is no matter on transmission line pattern or in any defect of transmission line pattern inside.
In another specific embodiments of the present invention, can use following electron beam irradiation condition (condition).Therefore, electron beam field condition comprises a landing energy (landing energy) on boundary in approximately 200 to approximately 2500 volts (volts), from the electric current of selecting thing (extracting), from approximately 0 to approximately 90 ampere (Amperes) for one No. 5 of approximately 0 Zhi Yue 3000 units, and the hole (aperture) of approximately 0 Zhi Yue 30 units.This example scans simultaneously in X and Y-direction.According to one embodiment of the invention, around any an array (array) and of semiconductor device, (periphery) or its combination can irradiate to detect defect with electron beam irradiation device or irradiation unit.
Fig. 3 A and Fig. 3 B have illustrated in order to detect the application examples of the novel test pattern 100 of Fig. 2 B of one or more defects in semiconductor device.In one embodiment of this invention, Fig. 3 A has illustrated the defect 6 on a circuit of a plurality of conducting wires 4 that may be formed at semiconductor device.For instance, but not thereby limited, in a metal deposition process because manufacture method improperly may form this kind of defect 6.Fig. 3 B has illustrated according to producing an image on the semiconductor device of Fig. 3 A by an electron beam irradiation in one embodiment of the invention.
Embodiment shown in Fig. 3 A has also illustrated a defect conduction line pattern design and has comprised a damaged line 7 and defect 6, and defect 6 comprises recess or may be even oxide bridging line in addition.A plurality of conducting wires 4 of irradiating with electron beam irradiation the results are shown in the image in Fig. 3 B.The electronics penetrating from electron beam equipment accumulates on non-defect circuit.The degree of the electronics that can be accumulated in any conducting wire is the continuous surface area that is directly related to conducting wire.Due to the accumulation of negatron, many secondary electrons are penetrated from the surface of non-defect circuit, cause a brighter or whiter image.On the other hand, the electronics of minority accumulates in the defect circuit that comprises the bridging line of recess/oxide or damaged line.Therefore, minority secondary electron penetrates from surface, causes dark image.Thereby the image display producing goes out there be (presence) or lack (absence) of defect line pattern.
According to the embodiment shown in Fig. 3 A, damaged line 7 has a less successive range with the electronics of accumulation electron beam; Therefore, the image of damaged line 7 is the most black in the fragment (segment) 17 of Fig. 3 B.On the other hand, the metallic circuit 4 that recess or oxide bridging line defect 6 can hinder electronics to be positioned at by this defect; Therefore, fragment shade 16Ke circle in Fig. 3 B is in not having a circuit shade of any defect and representing between the shade of fragment 17 of damaged line 7.
As be illustrated in Fig. 3 B as described in embodiment, conducting wire deposition quality can be monitored be formed at any damaged line and/or the defect in one or more conducting wires to be used for identification (identify).Moreover owing to interconnecting the conductive interconnecting structure of all conducting wires, the continuum of a regular link can be exaggerated.Therefore, the contrast of image can be higher and be made the easier identification of image detecting.
One embodiment of the invention are to manufacture the image of the semiconductor device with line pattern design.According to one embodiment of the invention, according to the method herein that is further described in, can be mainly the method that semiconductor device is manufactured in further test.The method of manufacturing semiconductor device comprises the following steps.One substrate is provided.Form a plurality of grooves (trenches) in dielectric layer.Form at least one interconnection channel in dielectric layer with a plurality of grooves (trenches) that interconnect.Deposit an electric conducting material in a plurality of grooves (trenches) and at least one interconnection channel.
Fig. 4 A has illustrated an electron beam equipment that can be used in part embodiment of the present invention.For instance, the electron beam equipment 200 of Fig. 4 A can more comprise it being for example negative electrode 210 and capacitor lens (condenser lens) 220 of zirconia (zirconium oxide)/tungsten cathode (tungsten cathode).Negative electrode 210 is in order to produce an electron beam.Capacitor lens 220 are in order to concentrate by the electron beam of field remainder or the shade of main light beam (primary beam) 230.One light beam extinguishing means (A beam blanker) 240 can be in order to open or to turn off light beam.One astigmatic aberration compensator (stigmator) 250 can be in order to improve the symmetry (symmetry) of electron beam.One hole (aperture) 260 can be in order to limit the size (size) of electron beam.One lens 270(is for example the lens that are magnetic) can and improve the shade of light beam in order to convection light.One reflective mirror 280 can be provided to the path in order to isolated electron beam.Especially, in lens reflective mirror (in-lens deflector) 290 can reflection electronic bundle to produce secondary and backscattering electronics (back-scattered electrons) 300.Reflective mirror 280 can further comprise reflective mirror (in-lens deflector) 290 in lens.For instance, a horizontal plane 310 can be in order to control required beam intensity.
Similar in appearance to the electron beam equipment illustrating in Fig. 4 A, can be used in the defect of surveying in semiconductor device.Certainly, this semiconductor device has a test pattern, for example, be a test pattern of the present invention.Semiconductor device can generally include a substrate, is arranged at the dielectric layer on substrate, a plurality of conductive pattern and at least one interconnection line pattern.A plurality of conductive patterns are arranged in dielectric layer, and at least one interconnection line pattern setting is to connect a plurality of line patterns.Any irradiation unit can be in test process of the present invention.For example, yet according to part embodiment of the present invention, irradiation unit is similar in appearance to as being illustrated in the electron beam equipment as shown in Fig. 4 A.One receiving system is configured to for receiving the data from irradiation unit.In part embodiment of the present invention, a device for image is used to show an image, and the object of image is to survey wherein arbitrary of a blemish, an internal flaw and combination thereof.
Fig. 4 B is an embodiment who illustrates novel test pattern design, and how from the surface of conducting wire pattern, to penetrate the second electronics to produce an image.For instance, an electron beam is by producing similar in appearance to being illustrated in the equipment shown in Fig. 4 A.It is for example the patterned image of the present invention illustrating in Fig. 2 B that one electron beam can be considered as.Image pattern can identification pointed flawless in fact conducting wire of quilt " G " 410 in Fig. 4 B.Moreover, herein, further describe in conjunction with shown in Fig. 3 A and Fig. 3 B, the conducting wire with one or more defects will be labeled out by the fragment that reduces electronics or have no electronics, and as same dark fragment 420 illustrated out.
Further be illustrated in Fig. 4 B, according to one embodiment of the invention, an external electrical field maker (electrical field generator) is to be positioned near test pattern 400 parts and an external electrical field 430 to be applied to test pattern 400.Be not subject under theoretical restraining, external electrical field 430 allows more polyelectron to accumulate on the surface 440 of test pattern 400.The accumulation of electronics can cause the enhancing of the image contrast of test pattern like this.The embodiment illustrating according to the present invention, external electrical field maker is positioned at the top of test pattern 400 and the directed test pattern 400 of positive charge 450 so that the positive external electrical field 430 on test pattern 400 to be provided.Due to the cause of positive external electrical field 430, at the electronics of test pattern 400, be induced (attracted) to surperficial 440 over top so that the image contrast of the second electronics uprises.
In another embodiment of the present invention, external electrical field maker can be positioned at an opposite side of test pattern.And external electrical field is provided in order to the electronics in accelerated test pattern and moves toward the surface of test pattern opposite side.
Fig. 5 has illustrated an energy diagram of an anodal pattern and a negative pole pattern electron beam irradiation.One anodal pattern electron beam irradiation provide a positive charge surface to semiconductor device to accept analysis.One anodal pattern analysis and negative pole pattern analysis can be presented by an energy of suitable selection electron beam.For instance, when an energy of electron beam is between the first ENERGY E 1 and 2 of the second ENERGY E (illustrating in as Fig. 5), present an anodal pattern analysis.In part embodiment of the present invention, for example, when conducting metal is copper or copper alloy, one first energy can be about 200 volts (volts) and the second energy can be about 1500 volts (volts).
When electron beam energy surpasses the second ENERGY E 2, by providing a negative charged surface to semiconductor device to accept to analyze, carry out a negative sense pattern electron beam irradiation.Further be presented in this, use bright fragment and the dark fragment of an image of negative sense pattern electron beam irradiation acquisition will be reversed the homologous segment of comparing to an image that uses anodal pattern electron beam irradiation to obtain.
Semiconductor making method needs soon and meets the defect detecting technique of economic benefit.In addition, the method must be also reliable.Valuably, defect detection method of the present invention goes for carrying out (in-line) on the line of semiconductor device, analyzes continuously.Therefore, the method relates to and being written in (loading) semiconductor device to monitoring equipment.Semiconductor device more comprises a plurality of patterns that link by least one interconnection line pattern.In one embodiment of this invention, an electron beam detection equipment can be used as on a line, a monitoring equipment of continuation method.Semiconductor device can be scanned, and for instance, using a response stimulus thing is for example an electron beam irradiation.The in the situation that of electron beam irradiation, corresponding to the image data of electron beam irradiation, can be collected and process to obtain the image of semiconductor substrate.This image can be pointed out existence and/or the shortage of defect under detecting semiconductor device.In a continuation method, several batches of semiconductors can be admitted in a monitoring equipment, and image data can be collected and process to be transformed into the image of the shortage of existing of pointing out deficiencies or defect.
Aspects more of the present invention comprise the method for semiconductor detecting, and the method for semiconductor detecting comprises providing to have a plurality of line patterns that are arranged on substrate, and wherein a plurality of line patterns link by least one interconnection line pattern.Expose a plurality of line pattern to response stimulus.Measure a plurality of line patterns to a reaction of response stimulus, wherein the reaction of a plurality of line patterns refers to the arbitrary of the existence of a blemish, an internal flaw or its combination or shortage.
Line pattern of the present invention can be that straight line path, crooked circuit maybe can be rendered as geometry, such as being Curved, semicircle, circle, positive square, triangle etc.
" blemish " means any general defect occurring in a common semiconductor processes.For instance, the surface of transmission line pattern can be uneven (uneven), contaminated (contaminated), jagged (chipped) or incomplete (fragmented).Blemish may or may not can be seen by naked eyes.
In aspect more of the present invention, a plurality of line patterns can link by least one interconnection line pattern.Interconnection line pattern mutually links a plurality of line patterns and forms uniline pattern or a design.In of the present invention one special embodiment, a plurality of line patterns are parallel to each other.In part embodiment of the present invention, at least one interconnection line pattern can be perpendicular to a plurality of line patterns.In part embodiment of the present invention, at least one interconnection line pattern can be close to an end (terminus) of a plurality of line patterns." interconnect " and mean to connect a plurality of line patterns and formation uniline layout.
In some embodiments of the invention, a plurality of line patterns can be exposed to response stimulus.One " response stimulus thing " and/or " response stimulus " can be anyly can cause stimulus or the stimulation that a plurality of line patterns cause a reaction.In some embodiments of the invention, semiconductor can comprise a plurality of line patterns that are exposed to response stimulus, and semiconductor is for example semiconductor device or semiconductor substrate.In part embodiment of the present invention, response stimulus comprises at least one light (irradiation), conduction (conductance), a magnetic resonance (magnetic resonance), an acoustic stimulation (acoustical stimulation) and an electrostimulation (electrical stimulation).In some specific embodiments, expose a plurality of line patterns and comprise with an electron beam irradiation and irradiate a plurality of line patterns in response stimulus.In part embodiment of the present invention, method more comprises from electron beam irradiation collects image data, and produces at least one image, the existence of image display blemish, internal flaw and combination thereof or shortage arbitrary.
An aspect of of the present present invention, a plurality of line patterns can be included in the lip-deep a plurality of grooves of semiconductor device and be arranged at least one conducting metal in a plurality of grooves.In the text, " groove " or " recess " represents equivalent and can mutually replace in the text.Groove or recess can by any this area existing known etching technique be formed on the surface of semiconductor device.
In some embodiments of the invention, electron beam can be detected instrument (electron beam inspection tool) by electron beam provides.Then according to these embodiment, electron beam detecting instrument can be a jumping characteristic electron beam detecting instrument or continuity electron beam detecting instrument.According to one embodiment of the invention, the step of jumping characteristic method for detecting is illustrated in Fig. 6.Semiconductor device in Fig. 6 A is provided.Fig. 6 B has illustrated a diagram of a defect crystal grain, and Fig. 6 D has illustrated the flawless in fact diagram with reference to crystal grain.Fig. 6 C has illustrated a scope of the defect crystal grain that has a defect.Fig. 6 E is the corresponding scope with reference to crystal grain.The image of Fig. 6 C and Fig. 6 E is used to relatively come the defect of identification defective chips.
According to one embodiment of the invention, the step of continuity scan method is illustrated in Fig. 7.Provide similar in appearance to the semiconductor device illustrating in Fig. 7 A.One continuous sweep method can comprise that scanning is illustrated in whole length of conductive strips (conductive strip) of a defect crystal grain in Fig. 7 B with a defect.The image of whole length of conductive strips is illustrated in Fig. 7 D.The scan-image of the defective part defect of tool crystal grain is used to be compared to a corresponding part with reference to crystal grain, and a corresponding part with reference to crystal grain is illustrated in respectively in Fig. 7 C and Fig. 7 E.Defective chip institute sweep test with reference to the comparison of crystal grain institute sweep test in order to identification defect.
In other embodiments of the invention, use the image of anodal pattern electron beam irradiation and negative pole pattern electron beam irradiation can be in order to identification the defect in semiconductor device.
Another aspect of the present invention provides semiconductor device, and semiconductor device comprises a substrate, a dielectric layer, a plurality of conducting wires pattern and at least one interconnection line pattern.A plurality of conducting wires pattern is in dielectric layer, and at least one interconnect conductive circuit pattern is in order to connect a plurality of line patterns.In general, one " substrate " is typical semiconductor manufacture or the semiconductor substrate in semiconductor technology.In some cases, a substrate is semiconductor wafer.In certain embodiments, substrate is a Silicon Wafer.In some cases, dielectric layer is formed on substrate.In certain embodiments, a plurality of conducting wires pattern is parallel.In certain embodiments, at least one interconnection line pattern is close to an end of conducting wire and perpendicular to a plurality of conducting wires pattern.In certain embodiments, dielectric layer comprises silicon monoxide (silicon oxide).In certain embodiments, a plurality of conducting wires pattern comprises copper.
Some embodiments of the present invention refer to the method for manufacturing semiconductor device, and the method for manufacturing semiconductor device comprises the following steps.One substrate is provided.Form at least one dielectric layer on substrate.A plurality of grooves of etching are in dielectric layer.At least one interconnection channel of etching in dielectric layer to interconnect a plurality of grooves.Deposit an electric conducting material in a plurality of grooves and at least one interconnection channel.In part embodiment of the present invention, the deposition that each groove of a plurality of grooves is parallel to each other.In some embodiments of the invention, at least one interconnection channel is vertically installed in a plurality of grooves.In an embodiment of the present invention, at least one interconnection channel is an end that is close to a plurality of grooves.In some embodiments of the invention, electric conducting material is to be selected from by aluminium, copper, tungsten, gold, any its alloy, and the group that forms of any its bond.
Some embodiments of the present invention comprise the method for detecting semiconductor device, and the method for detecting semiconductor device comprises the following steps.Semiconductor device is provided, semiconductor device has a substrate, a dielectric layer, a plurality of conducting wires pattern and at least one interconnect conductive circuit pattern, a plurality of conducting wires pattern setting is in dielectric layer, and interconnect conductive circuit pattern is in order to connect a plurality of conducting wires pattern.With an electron beam irradiation, irradiate semiconductor device.In light, receive image data result.Self imaging data produces an image of semiconductor device, and wherein the existence of image identification defect or shortage is arbitrary.In part embodiment of the present invention, method can be on a line, continuous method.Some embodiments of the present invention refer to detect at least one of them equipment, method and/or the system of an internal flaw of semiconductor device and a blemish, in order to detect at least one internal flaw of semiconductor device and equipment, method and/or the system of a blemish comprise the following steps.Semiconductor device is provided, and semiconductor device has a substrate, a dielectric layer, a plurality of conducting wires pattern, and at least one interconnection line pattern.A plurality of conducting wires pattern setting is in dielectric layer, and at least one interconnect conductive circuit pattern is in order to connect a plurality of conducting wires pattern.With an electron beam irradiation, irradiate semiconductor device.In light, receive the image that image data result and self imaging data produce semiconductor device, wherein the existence of any defect of image identification or shortage is arbitrary.
Some embodiments of the present invention comprise the system in order to detecting any defect in semiconductor device.In this specific embodiments, this system comprises the semiconductor device with a test pattern.Semiconductor device comprises a substrate, is arranged at a dielectric layer, a plurality of conducting wires pattern and at least one interconnection line pattern on substrate.A plurality of conducting wires pattern setting is in dielectric layer, and at least one interconnect conductive circuit pattern is in order to connect a plurality of conducting wires pattern.This system also comprises a radiation appliance (irradiating device), a receiving system and a device for image.Radiation appliance is in order to provide energy to test pattern, and receiving system is in order to receive the data result of autoradiolysis, and a device for image is in order to be presented at an image of any defect in semiconductor device.
Under being benefited of the instruction proposing at above-mentioned explanation and correlative type, the technical staff who has the knack of the technology will appreciate that of the present invention a plurality of modifications and other embodiment proposing at this.Therefore, we it will be appreciated that the present invention is not limited to disclosed specific embodiment, and revise and within other embodiment are also intended to be included in the category of the claims in the present invention.In addition, although above-mentioned explanation and correlative type understand illustrative embodiments some illustration combination of element and/or function, we should recognize that the various combination of element and/or function may be provided by alternate embodiment under the category that does not deviate from the claims in the present invention.In this, for example, be different from above-mentioned at length those element and/or the combination of function and be also considered to be and may in following some the claims in the present invention, be suggested.Although adopt specific term at this, they are used with common and descriptive meaning, rather than the object in order to limit only.
The above, it is only preferred embodiment of the present invention, not the present invention is done to any pro forma restriction, although the present invention discloses as above with preferred embodiment, yet not in order to limit the present invention, any those skilled in the art, do not departing within the scope of technical solution of the present invention, when can utilizing the technology contents of above-mentioned announcement to make a little change or being modified to the equivalent embodiment of equivalent variations, in every case be not depart from technical solution of the present invention content, any simple modification of above embodiment being done according to technical spirit of the present invention, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (22)
1. detect a method for semiconductor device, it is characterized in that it comprises the following steps:
This semiconductor device with a plurality of line patterns is provided, and those line patterns are arranged on a substrate, and those line patterns are to connect by an interconnection line pattern;
Expose those line pattern to one response stimulus; And
Measure those line patterns to a reaction of this response stimulus, wherein a blemish, an internal flaw or its combination are pointed out in this reaction of those line patterns.
2. the method for detecting semiconductor device according to claim 1, is characterized in that wherein those line patterns are parallel to each other.
3. the method for detecting semiconductor device according to claim 2, is characterized in that wherein this interconnection line pattern is perpendicular to those line patterns.
4. the method for detecting semiconductor device according to claim 3, is characterized in that wherein this interconnection line pattern is the end close to those line patterns.
5. the method for detecting semiconductor device according to claim 1, is characterized in that wherein this response stimulus comprises: a light, a conduction, a magnetic resonance, an acoustic stimulation and an electrostimulation at least one of them.
6. the method for detecting semiconductor device according to claim 1, is characterized in that wherein exposing those line patterns to this response stimulus and comprises: with an electron beam irradiation, irradiate those line patterns to provide energy to those line patterns.
7. the method for detecting semiconductor device according to claim 6, is characterized in that it also comprises:
Collection is from the image data of this electron beam irradiation; And
Produce at least one image data, this image data display surface defect, internal flaw or its combination.
8. the method for detecting semiconductor device according to claim 1, it is characterized in that wherein those line patterns comprise a plurality of grooves and at least one conducting metal, those grooves are positioned on this surface of this semiconductor device, and this at least one conducting metal is arranged in those grooves.
9. the method for detecting semiconductor device according to claim 6, it is characterized in that wherein this electron beam irradiation is to provide by an electron beam detecting instrument, this electron beam detecting instrument is a jumping characteristic electron beam detecting instrument or continuity electron beam detecting instrument.
10. the method for detecting semiconductor device according to claim 1, is characterized in that it also comprises this semiconductor device to one external electrical field of exposure.
11. 1 kinds of semiconductor devices, is characterized in that it comprises:
One substrate;
One dielectric layer, is arranged on this substrate;
A plurality of conducting wires pattern, is arranged in this dielectric layer; And
At least one interconnection line pattern, in order to connect those conducting wire patterns.
12. semiconductor devices according to claim 11, is characterized in that wherein those conducting wire patterns are parallel to each other.
13. semiconductor devices according to claim 12, is characterized in that wherein this at least one interconnection line pattern is close to an end of those conducting wire patterns and perpendicular to those conducting wire patterns.
14. semiconductor devices according to claim 11, it is characterized in that this dielectric layer wherein comprise silicon monoxide and a silicon nitride at least one of them.
15. semiconductor devices according to claim 11, is characterized in that wherein those conducting wire patterns comprise copper.
16. 1 kinds of methods of manufacturing semiconductor device, is characterized in that it comprises the following steps:
One substrate is provided;
Form a dielectric layer on this substrate;
Form a plurality of grooves in this dielectric layer;
Form at least one interconnection channel in this dielectric layer to interconnect those grooves; And
Deposit an electric conducting material in those grooves and this at least one interconnection channel.
The method of 17. manufacture semiconductor devices according to claim 16, is characterized in that wherein those grooves are to be arranged in parallel.
The method of 18. manufacture semiconductor devices according to claim 17, is characterized in that wherein this at least one interconnection channel is perpendicular to those grooves.
The method of 19. manufacture semiconductor devices according to claim 18, is characterized in that wherein this at least one interconnection channel is an end that is close to those grooves.
The method of 20. manufacture semiconductor devices according to claim 16, is characterized in that wherein this electric conducting material is to be selected from by aluminium, copper, tungsten, gold, any its alloy, and the group that forms of any its bond.
21. 1 kinds of systems in order to the defect of detecting in semiconductor device, is characterized in that it comprises:
This semiconductor device with a test pattern, this semiconductor device comprises:
One substrate;
One dielectric layer, is arranged on this substrate;
A plurality of conducting wires pattern, is arranged in this dielectric layer; And
At least one interconnection line pattern, in order to connect those conducting wire patterns;
One radiation appliance, in order to provide energy to this test pattern;
One receiving system, in order to receive the data from this radiation appliance; And
One device for image, in order to be presented at arbitrary image wherein of a blemish, an internal flaw and combination thereof in this semiconductor device.
22. systems in order to the defect of detecting in semiconductor device according to claim 21, is characterized in that it also comprises an external electrical field generator, are positioned near this substrate place.
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| CN117912979A (en) * | 2024-03-20 | 2024-04-19 | 合肥晶合集成电路股份有限公司 | Method and structure for measuring critical dimension |
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| JP2006222317A (en) * | 2005-02-10 | 2006-08-24 | Consortium For Advanced Semiconductor Materials & Related Technologies | Damage detecting apparatus, electronic element, and element assembly |
| TW200917403A (en) * | 2007-06-20 | 2009-04-16 | Hamamatsu Photonics Kk | Semiconductor failure analyzer, semiconductor failure analysis method and semiconductor failure analysis program |
| CN101458442A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Production of layout and photo mask and graphic method |
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| JP2006222317A (en) * | 2005-02-10 | 2006-08-24 | Consortium For Advanced Semiconductor Materials & Related Technologies | Damage detecting apparatus, electronic element, and element assembly |
| TW200917403A (en) * | 2007-06-20 | 2009-04-16 | Hamamatsu Photonics Kk | Semiconductor failure analyzer, semiconductor failure analysis method and semiconductor failure analysis program |
| CN101458442A (en) * | 2007-12-13 | 2009-06-17 | 中芯国际集成电路制造(上海)有限公司 | Production of layout and photo mask and graphic method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117912979A (en) * | 2024-03-20 | 2024-04-19 | 合肥晶合集成电路股份有限公司 | Method and structure for measuring critical dimension |
| CN117912979B (en) * | 2024-03-20 | 2024-06-07 | 合肥晶合集成电路股份有限公司 | Method and structure for measuring critical dimension |
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| TW201433789A (en) | 2014-09-01 |
| TWI480543B (en) | 2015-04-11 |
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