CN103985694A - Integrated circuit module and packaging assembly thereof - Google Patents
Integrated circuit module and packaging assembly thereof Download PDFInfo
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- CN103985694A CN103985694A CN201410242479.XA CN201410242479A CN103985694A CN 103985694 A CN103985694 A CN 103985694A CN 201410242479 A CN201410242479 A CN 201410242479A CN 103985694 A CN103985694 A CN 103985694A
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- integrated circuit
- interconnecting member
- power bus
- pin
- power
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
Abstract
The invention discloses an integrated circuit module and a packaging assembly of the integrated circuit module. The integrated circuit module comprises a semiconductor bare chip, a first insulation layer and i power buses, wherein the semiconductor bare chip comprises a plurality of electronic devices which are divided into m sets, each electronic device comprises n electrodes with different polarities, and m and n are both integers larger than one; the first insulation layer is located on the surface of the semiconductor bare chip; the i power buses comprise a plane extending portion located on the first insulation layer and a plurality of perpendicular channel portions which penetrate through the first insulation layer and are connected with all electrodes of the devices, i is an integer larger than one and smaller than or equal to m*n, one electrode of each device in at least two electronic devices and one electrode of another device in at least two electronic devices are electrically connected through at least one power bus among the i power buses, and each power bus among the i power buses is connected to an external connecting terminal. By the adoption of the integrated circuit module, a lead frame with a finger-shaped lead fin is omitted, so that the design of the lead frame is simplified, the interconnection resistance is reduced, and heat dissipation performance is improved.
Description
Technical field
The present invention relates to semiconductor package, relate more specifically to be applied to integrated circuit package and the package assembling thereof of switch type regulator.
Background technology
Switch type regulator, for example DC-DC converter, is used for providing stable voltage source to various electric systems.In low power-supply device, (as laptop computer, mobile phone etc.) battery management especially needs high efficiency DC-DC converter.Switch type regulator converts high-frequency voltage to input direct voltage, then high-frequency output voltage is carried out to filtering and then converts VD to.
Fig. 1 shows the circuit diagram of typical switch type regulator 10.This switch type regulator comprises controlled stage and power stage.Controlled stage comprises control chip U1.Power stage comprises power device Q1 and Q2.Power device is for example field-effect transistor or bipolar transistor.Power device Q1 and Q2 are connected between input voltage vin and ground GND, and its intermediate node is as output Lx.The input and output electrode of control chip U1 is connected to input and output electrode IOs, and its drive electrode is connected to the gate electrode separately of power device Q1 and Q2, for conducting and the disconnection of power ratio control device Q1 and Q2, thereby produces output current.
In order to meet the demand to the miniaturization of switch type regulator, low control voltage and large output current, in switch type regulator, can adopt a plurality of power devices in parallel to replace single power device.Yet the electrical connection of a plurality of power devices need to be used the lead frame that comprises a plurality of finger-like pins, thereby may introduce additional interconnection resistance and heat dissipation problem.
Therefore,, in being applied to the integrated circuit package of switch type regulator, expectation further improves layout and the connected mode of power device.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of integrated circuit package and package assembling thereof, to solve the electrical connection of a plurality of electronic devices, its performance is caused to the problem of adverse effect.
According to a first aspect of the invention, provide a kind of integrated circuit package, comprising: semiconductor bare chip, comprise a plurality of electronic devices that are divided into m group, each electronic device comprises n electrode of opposed polarity, wherein m and n are greater than 1 integer; The first insulating barrier, is positioned at the described surface of semiconductor bare chip; And i power bus, comprise respectively the planar extension being positioned on the first insulating barrier and a plurality of vertical channel parts of passing each electrode of the first insulating barrier interface unit, wherein i is greater than 1 and be less than or equal to the integer of m*n, wherein, at least one power bus in a described i power bus is electrically connected to each other an electrode of all devices at least two electronic device groups, and each in a described i power bus is connected to an external connection terminals.
Preferably, in described integrated circuit package, described electronic device is at least one being selected from diode, transistor, resistance, inductance.
Preferably, in described integrated circuit package, the planar extension of at least one the first power bus in a described i power bus is ribbon; And the planar extension of at least one the second source bus in a described i power bus is sinuous polyline shaped, the direction of current flow that makes described at least one second source bus changes with respect to the direction of current flow of described at least one the first power bus.
Preferably, described integrated circuit package also comprises: the second insulating barrier, between semiconductor bare chip and the first insulating barrier; And j interconnecting member, comprise respectively the planar extension that is positioned on the second insulating barrier and through the second insulating barrier, be connected a plurality of vertical channel parts of each electrode of power device, wherein, at least two interconnecting members in a described j interconnecting member are electrically connected to each other an electrode of all devices in an electronic device group respectively, and at least one power bus in a described i power bus is electrically connected to each other described at least two interconnecting members.
Preferably, in described integrated circuit package, the plane bearing of trend of a described i power bus is first direction, and the plane bearing of trend of a described j interconnecting member is second direction, and first direction intersects with second direction.
Preferably, in described integrated circuit package, first direction is vertical with second direction.
Preferably, in described integrated circuit package, at least one in a described j interconnecting member is segmentation, and at least one in a described i power bus is electrically connected the different sections of segmentation interconnecting member.
Preferably, in described integrated circuit package, at least one in a described i power bus is segmentation.
Preferably, in described integrated circuit package, the plane bearing of trend of the Segmented electrical source bus in a described i power bus, vertical with the plane bearing of trend of segmentation interconnecting member in a described j interconnecting member, make the direction of current flow in Segmented electrical source bus vertical with the direction of current flow in segmentation interconnecting member.
Preferably, in described integrated circuit package, at least one in a described j interconnecting member is electrically connected the different sections of Segmented electrical source bus.
Preferably, described integrated circuit package also comprises lead frame, and described lead frame just at least two different sections of Segmented electrical source bus is electrically connected.
Preferably, in described integrated circuit package, described electronic device is field-effect transistor, and the electrode of described field-effect transistor comprises source electrode, drain and gate.
Preferably, described integrated circuit package also comprises lead frame, and a wherein said i power bus is connected to described lead frame.
According to a second aspect of the invention, a kind of integrated circuit package that is applied to switch type regulator is provided, comprise: semiconductor bare chip, comprise a plurality of power devices that are divided into two groups, each power device is included in the first electrode and the second electrode exposing on the surface of semiconductor bare chip, the first insulating barrier, is positioned at the described surface of semiconductor bare chip, and first to the 3rd power bus, comprise respectively the planar extension that is positioned on the first insulating barrier and through the first insulating barrier, be connected a plurality of vertical channel parts of each electrode of power device, wherein, the first power bus is electrically connected to each other the first electrode of first group of power device, second source bus is electrically connected to each other the first electrode of the second electrode of first group of power device and second group of power device, the 3rd power bus is electrically connected to each other the second electrode of second group of power device, and first to the 3rd each in power bus be connected to an external connection terminals.
Preferably, in described integrated circuit package, first and the planar extension of the 3rd power bus be ribbon; And the planar extension of second source bus is sinuous polyline shaped, the direction of current flow that makes second source bus changes with respect to the direction of current flow of the first and the 3rd power bus.
Preferably, described integrated circuit package also comprises: the second insulating barrier, between semiconductor bare chip and the first insulating barrier, and first to fourth interconnecting member, comprise respectively the planar extension that is positioned on the second insulating barrier and through the second insulating barrier, be connected a plurality of vertical channel parts of each electrode of power device, wherein, the first interconnecting member is electrically connected to each other the first electrode of first group of power device, the second interconnecting member is electrically connected to each other the second electrode of first group of power device, the 3rd interconnecting member is electrically connected to each other the first electrode of second group of power device, the 4th interconnecting member is electrically connected to each other the second electrode of second group of power device, and first power bus connect the first interconnecting member, second source bus connects the second and the 3rd interconnecting member, the 3rd power bus connects the 4th interconnecting member.
Preferably, in described integrated circuit package, the plane bearing of trend of the first to the 3rd power bus is first direction, and the plane bearing of trend of first to fourth interconnecting member is second direction, and first direction intersects with second direction.
Preferably, in described integrated circuit package, first direction is vertical with second direction.
Preferably, in described integrated circuit package, at least one of first to fourth interconnecting member is segmentation, and the first to the 3rd power bus is electrically connected the different sections of segmentation interconnecting member.
Preferably, in described integrated circuit package, at least one in the first to the 3rd power bus is segmentation.
Preferably, in described integrated circuit package, the second interconnecting member, the 3rd interconnecting member and second source bus are segmentation, every section of the second interconnecting member and every section of the 3rd interconnecting member stagger, and every section of bearing of trend of second source bus is vertical with every section of bearing of trend in the second interconnecting member, the 3rd interconnecting member, makes the direction of current flow in the second interconnecting member, the 3rd interconnecting member vertical with the direction of current flow in second source bus.
Preferably, in described integrated circuit package, described first to fourth interconnecting member is electrically connected the different sections of Segmented electrical source bus.
Preferably, described integrated circuit package also comprises lead frame, and described lead frame is electrically connected the different sections of Segmented electrical source bus.
Preferably, in described integrated circuit package, described power device is field-effect transistor, the source electrode that described the first electrode is field-effect transistor and drain electrode in one, the source electrode that described the second electrode is field-effect transistor and drain electrode in another.
Preferably, described integrated circuit package also comprises lead frame, and the wherein said first to the 3rd power bus is connected to described lead frame.
According to a third aspect of the invention we, provide a kind of package assembling, comprising: above-mentioned integrated circuit package; Lead frame, comprises a plurality of pins, and described integrated circuit package is arranged on described lead frame; And encapsulating compound, described encapsulating compound covers described integrated circuit package, and covers at least a portion of described lead frame, described a plurality of pin part is separately exposed and for outside, be electrically connected to.
Preferably, in described package assembling, described integrated circuit package comprises conductive projection, and the upper surface of described conductive projection and described pin forms welding flux interconnected.
Preferably, in described package assembling, described pin comprises the first of the first thickness and the second portion of the second thickness, wherein the second thickness is greater than the first thickness, the first of described pin is included in encapsulating compound, and the end of the second portion of described pin and/or lower surface expose for outside and are electrically connected to.
Preferably, in described package assembling, the bottom of described package assembling comprises four bottom sides, and at least one pin in wherein said pin comprises two or more second portions, thereby forms a plurality of external contacts.
Preferably, in described package assembling, at least one second portion of described at least one pin is positioned at the bottom zone line of package assembling, and at least another second portion is positioned near the bottom side of package assembling.
Preferably, in described package assembling, described at least one pin is connected internally to a power bus in the described first to the 3rd power bus at package assembling.
Preferably, in described package assembling, at least one in the described first to the 3rd power bus is segmentation, and at least one pin in described pin links together the different sections of the power bus of segmentation, thereby forms public external contact.
Preferably, described package assembling also comprises: the control chip that comprises a plurality of input and output electrodes, wherein, the bottom of described package assembling has first to fourth bottom side, described a plurality of pin comprises for first group of pin of power bus and for second group of pin of control chip, the first power bus is connected with the first pin in first group of pin, a plurality of second portions that are positioned at the first bottom side that described the first pin comprises; Second source bus is connected with the second pin in first group of pin, and described the second pin comprises a plurality of second portions that lay respectively at the second and the 3rd bottom side; The 3rd power bus is connected with the 3rd pin in first group of pin, and described the 3rd pin comprises a plurality of second portions that lay respectively at the second and the 3rd bottom side and bottom zone line; And described a plurality of input and output electrodes of described control chip are connected to respectively a plurality of pins in second group of pin, the described a plurality of pins in described second group of pin comprise and lay respectively at the second second portion to the 4th bottom side.
Preferably, in described package assembling, described a plurality of pins are identical with the quantity of the external contact forming on the 4th bottom side at the first bottom side, and identical with the quantity of the external contact forming on the 3rd bottom side at the second bottom side.
Preferably, in described package assembling, described a plurality of second portions of described the first pin provide in voltage signal terminal Vin and earth terminal GND, described a plurality of second portions of described the 3rd pin provide another in voltage signal terminal Vin and earth terminal GND, described a plurality of second portion switching node signal terminal LX of described the second pin.
According to integrated circuit package of the present invention, lead frame needn't design for power device group the finger-like pin of complex topology, thereby can simplify the design of lead frame.Even if the power device quantity in power device group changes, also can adopt the lead frame of same size, thereby can realize the standardization of lead frame.Further, above-mentioned power bus can with lead frame between realize large area and contact, thereby can reduce interconnection resistance and improve radiating effect.
In a preferred embodiment, power bus and optional interconnecting member can be segmentations, thereby not only can improve the layout degree of freedom, and can reduce stress.
In a preferred embodiment, power bus and optional interconnecting member can change direction of current flow, thereby have reduced stray inductance, have improved electrical property.
Accompanying drawing explanation
By the description to the embodiment of the present invention referring to accompanying drawing, above-mentioned and other objects of the present invention, feature and advantage will be more clear, in the accompanying drawings:
Fig. 1 shows the circuit diagram of typical switch type regulator;
Fig. 2 a, 2b and 2c illustrate respectively according to the perspective view of the integrated circuit package that is applied to switch type regulator of the first embodiment of the present invention with along the sectional view of different directions intercepting;
Fig. 3 a, 3b and 3c illustrate respectively the perspective view of the integrated circuit package that is applied to switch type regulator according to a second embodiment of the present invention and the sectional view intercepting along different directions;
Fig. 4 a, 4b and 4c illustrate respectively a third embodiment in accordance with the invention the integrated circuit package that is applied to switch type regulator perspective view and along the sectional view of different directions intercepting;
Fig. 5 a, 5b and 5c illustrate respectively a fourth embodiment in accordance with the invention the integrated circuit package that is applied to switch type regulator decomposition diagram and along the sectional view of different directions intercepting;
Fig. 6 a, 6b, 6c and 6d illustrate respectively a fourth embodiment in accordance with the invention the integrated circuit package that is applied to switch type regulator decomposition diagram and along the sectional view of different directions intercepting; And
Fig. 7 a, 7b, 7c and 7d illustrate respectively the sectional view of decomposition diagram, bottom view and the diverse location of the package assembling that is applied to switch type regulator according to a fifth embodiment of the invention; And
Fig. 8 a, 8b, 8c, 8d and 8e illustrate respectively the sectional view of decomposition diagram, bottom view and the diverse location of the package assembling that is applied to switch type regulator according to a sixth embodiment of the invention.
Embodiment
Hereinafter with reference to accompanying drawing, various embodiment of the present invention is described in more detail.In each accompanying drawing, identical element adopts same or similar Reference numeral to represent.
For the sake of clarity, the various piece in accompanying drawing is not drawn in proportion.For brevity, the modular construction obtaining can be described in a width figure after several steps.In addition, also may omit some known details, for example, in some drawings not shown scolder, encapsulating compound, for backing material and/or the external frame of supporting wire frame.
Be to be understood that, when describing modular construction, when one deck, region are called be positioned at another layer, another region " above " or when " top ", can refer to be located immediately at another layer, another is above region, or its and another layer, also comprise between another region other layer or region.And if by device upset, this one deck, a region will be positioned at another layer, another region " below " or " below ".If be located immediately at another layer, another situation above region in order to describe, will adopt herein " directly exist ... above " or " ... above and with it in abutting connection with " form of presentation.
Described hereinafter many specific details of the present invention, for example structure of integrated circuit package, material, size, treatment process and technology, to more clearly understand the disclosure.But just as the skilled person will understand, can realize the disclosure not according to these specific details.
Fig. 2 a, 2b and 2c illustrate respectively according to the perspective view of the integrated circuit package that is applied to switch type regulator 100 of the first embodiment of the present invention, and the sectional view of AA along the line and line BB intercepting.As shown in Figure 2 a, line AA is across not the first electrode and second electrode of power switch on the same group, and line BB is across the first electrode of all power switchs of same group of power switch.
Integrated circuit package 100 comprises semiconductor bare chip 110.Two power device groups and/or optional control chip in semiconductor bare chip 110, have at least been formed.Each power device group comprises a plurality of power devices that are connected in parallel.Each power device is included in the first electrode and the second electrode exposing on a surface of semiconductor bare chip, and is positioned at this surface or another lip-deep control electrode relative with this surface.In each power device, the first electrode, the second electrode and control electrode are electrically isolated from one.In following accompanying drawing, control electrode is not described for brevity.
Power device is be for example selected from bipolar transistor and field-effect transistor a kind of.Under the situation of bipolar transistor, the first electrode of power device is in emitter and collector, and the second electrode is another in emitter and collector, and control electrode is base stage.Under the transistorized situation of being on the scene effect, the first electrode of power device is in source electrode and drain electrode, and the second electrode is another in source electrode and leakage, and control electrode is grid.
In this embodiment, integrated circuit package 100 comprises 2 power device groups, and each power device group comprises 3 power devices, thereby forms the array of 2 * 3 power devices.In alternative embodiment, each power device group can comprise 2 or more power device.Power device of the first power device group and a corresponding power device of the second power device group form a line.For example, a power device of the first power device group comprises the first electrode 111-1a and the second electrode 111-2a, a power device of the second power device group comprises the first electrode 112-1a and the second electrode 112-2a, and the first electrode 112-1a of a power device is adjacent with the second electrode 111-2a of another power device, as shown in Figure 2 b.3 power devices of the first power device group are in line, and 3 power devices of the second power device group are lined up another row, thereby form the array of power device.For example, the second electrode 111-2a, 111-2b and the 111-2c of 3 power devices of the first power device group are adjacent one another are, as shown in Figure 2 c.
Integrated circuit package 100 also comprises the first insulating barrier 115 and the first power bus 116a, the second source bus 116b and the 3rd power bus 116c that for outside, are electrically connected to.The first insulating barrier 115 is for example comprised of silica, is positioned on the surface of semiconductor bare chip 110.The first power bus 116a, second source bus 116b and the 3rd power bus 116c are for example comprised of aluminium or copper, comprise respectively the planar extension that is positioned on the first insulating barrier 115 and through the first insulating barrier 115, contact a plurality of vertical channel parts of the electrode of power device.The planar extension separately of above-mentioned power bus is for example ribbon and parallel to each other.The first power bus 116a is electrically connected to the first electrode of each power device in first power device group.Second source bus 116b is electrically connected to the second electrode of each power device and the first electrode of each power device in second power device group in first power device group.The 3rd power bus 116c is electrically connected to the second electrode of each power device in second power device group.
In order to provide outside, be electrically connected to, between the first power bus 116a, second source bus 116b and the 3rd power bus 116c and lead frame, can be connected via conductive projection and/or soldered ball.In switch type regulator, the first power bus 116a is connected to voltage signal terminal Vin, and second source bus 116b is connected to switching node signal terminal LX, and the 3rd power bus 116c is connected to earth terminal GND.
In above-mentioned integrated circuit package 100, owing to using the first to the 3rd power bus, lead frame needn't design for power device group the finger-like pin of complex topology, thereby can simplify the design of lead frame.Even if the power device quantity in power device group changes, also can adopt the lead frame of same size, thereby can realize the standardization of lead frame.Further, above-mentioned power bus can with lead frame between realize large area and contact, thereby can reduce interconnection resistance and improve radiating effect.
Fig. 3 a, 3b and 3c illustrate respectively the perspective view of the integrated circuit package that is applied to switch type regulator 200 according to a second embodiment of the present invention, and the sectional view of AA along the line and line BB intercepting.As shown in Figure 3 a, line AA is across not the first electrode and second electrode of power switch on the same group, and line BB is across the first electrode of all power switchs of same group of power switch.
Integrated circuit package 200 comprises the first insulating barrier 215 and the first power bus 216a, the second source bus 216b and the 3rd power bus 216c that for outside, are electrically connected to.The first insulating barrier 215 is for example comprised of silica, is positioned on the surface of semiconductor bare chip 210.The first power bus 216a, second source bus 216b and the 3rd power bus 216c are for example comprised of aluminium or copper, comprise respectively the planar extension that is positioned on the first insulating barrier 215 and through the first insulating barrier 215, contact a plurality of vertical channel parts of the electrode of power device.The first power bus 216a is electrically connected to the first electrode of each power device in first power device group.Second source bus 216b is electrically connected to the second electrode of each power device and the first electrode of each power device in second power device group in first power device group.The 3rd power bus 216c is electrically connected to the second electrode of each power device in second power device group.
In order to provide outside, be electrically connected to, between the first power bus 216a, second source bus 216b and the 3rd power bus 216c and lead frame, can be connected via conductive projection and/or soldered ball.In switch type regulator, the first power bus 216a is connected to voltage signal terminal Vin, and second source bus 216b is connected to switching node signal terminal LX, and the 3rd power bus 216c is connected to earth terminal GND.
The difference of the second embodiment and the first embodiment is: in integrated circuit package 200, the planar extension of second source bus 216b is sinuous polyline shaped.According to other parts of the integrated circuit package 200 of the second embodiment with identical according to the appropriate section of the integrated circuit package 100 of the first embodiment.
Above-mentioned, according in the integrated circuit package 200 of the second embodiment, with respect to the first adjacent power bus 216a and the 3rd power bus 216b, electric current is along the flow direction of second source bus 216b almost parallel sometimes, sometimes substantially vertical.Therefore, integrated circuit package 200 has further reduced stray inductance, has improved the electrical property of integrated circuit package.
Fig. 4 a, 4b and 4c illustrate respectively the perspective view of the integrated circuit package that is applied to switch type regulator 300 of a third embodiment in accordance with the invention, and the sectional view of AA along the line and line BB intercepting.As shown in Fig. 4 a, line AA is across not the first electrode and second electrode of power switch on the same group, and line BB is across the first electrode of all power switchs of same group of power switch.
Integrated circuit package 300 comprises the first insulating barrier 313 and the first interconnecting member 314a, the second interconnecting member 314b, the 3rd interconnecting member 314c and the 4th interconnecting member 314d that for interlayer, are electrically connected to.The first insulating barrier 313 is for example comprised of silica, is positioned on the surface of semiconductor bare chip 310.The first interconnecting member 314a, the second interconnecting member 314b, the 3rd interconnecting member 314c and the 4th interconnecting member 314d are for example comprised of aluminium or copper, comprise respectively the planar extension that is positioned on the first insulating barrier 313 and through the first insulating barrier 313, contact a plurality of vertical channel parts of the electrode of power device.
The planar extension separately of above-mentioned interconnecting member is for example ribbon and parallel to each other.The first interconnecting member 314a is electrically connected to the first electrode of each power device in first power device group.The second interconnecting member 314b is electrically connected to the second electrode of each power device in first power device group.The 3rd interconnecting member 314c is electrically connected to the first electrode of each power device in second power device group.The 4th interconnecting member 314d is electrically connected to the second electrode of each power device in second power device group.
Integrated circuit package 300 also comprises the second insulating barrier 315 and the first power bus 316a, the second source bus 316b and the 3rd power bus 316c that for outside, are electrically connected to.The second insulating barrier 315 is for example comprised of silica, is positioned on the surface of the first insulating barrier 313.The first power bus 316a, second source bus 316b and the 3rd power bus 316c are for example comprised of aluminium or copper, comprise respectively the planar extension that is arranged on the second insulating barrier 315 and through the second insulating barrier 315, contact a plurality of vertical channel parts of at least one interconnecting member of the first interconnecting member 314a, the second interconnecting member 314b, the 3rd interconnecting member 314c and the 4th interconnecting member 314d.
The planar extension separately of above-mentioned power bus is for example ribbon and parallel to each other.The bearing of trend of the planar extension of power bus intersects with the bearing of trend of the extension of interconnecting member.Preferably, the bearing of trend of the bearing of trend of the planar extension of power bus and the extension of interconnecting member is perpendicular to one another.The first power bus 316a is electrically connected to the first interconnecting member 314a.Second source bus 316b is all electrically connected to the second interconnecting member 314b and the 3rd interconnecting member 314c.The 3rd power bus 316c is electrically connected to the 4th interconnecting member 314a.
In order to provide outside, be electrically connected to, between the first power bus 316a, second source bus 316b and the 3rd power bus 316c and lead frame, can be connected via conductive projection and/or soldered ball.In switch type regulator, the first power bus 316a is connected to voltage signal terminal Vin, and second source bus 316b is connected to switching node signal terminal LX, and the 3rd power bus 316c is connected to earth terminal GND.
The difference of the 3rd embodiment and the first embodiment is: in integrated circuit package 300, the first power bus 316a, second source bus 316b and the 3rd power bus 316c are connected to each electrode of power device via the first interconnecting member 314a, the second interconnecting member 314b, the 3rd interconnecting member 314c and the 4th interconnecting member 314.According to other parts of the integrated circuit package 300 of the 3rd embodiment with identical according to the appropriate section of the integrated circuit package 100 of the first embodiment.
Above-mentioned according in the integrated circuit package 300 of the 3rd embodiment, even if the corresponding power device in a power device in first power device group and second power device group is spaced from each other, or centre arranges other elements, all power devices that also can utilize interconnecting member first to interconnect mutually on the same group, then utilize power bus to realize outside connection.Therefore, integrated circuit package 300 further provides the layout degree of freedom of power device.
Fig. 5 a, 5b and 5c illustrate respectively the decomposition diagram of the integrated circuit package that is applied to switch type regulator 400 of a fourth embodiment in accordance with the invention, and the sectional view of AA along the line and line BB intercepting.As shown in Figure 5 a, line AA is across not the first electrode and second electrode of power switch on the same group, and line BB is across the first electrode of all power switchs of same group of power switch.
Integrated circuit package 400 comprises the first insulating barrier 413 and the first interconnecting member 414a, the second interconnecting member 414b, the 3rd interconnecting member 414c and the 4th interconnecting member 414d that for interlayer, are electrically connected to.The first insulating barrier 413 is for example comprised of silica, is positioned on the surface of semiconductor bare chip 410.The first interconnecting member 414a, the second interconnecting member 414b, the 3rd interconnecting member 414c and the 4th interconnecting member 414d are for example comprised of aluminium or copper, comprise respectively the planar extension that is positioned on the first insulating barrier 413 and through the first insulating barrier 413, contact a plurality of vertical channel parts of the electrode of power device.
The planar extension separately of above-mentioned interconnecting member is for example ribbon and parallel to each other.The first interconnecting member 414a is electrically connected to the first electrode of each power device in first power device group.The second interconnecting member 414b is electrically connected to the second electrode of each power device in first power device group.The 3rd interconnecting member 414c is electrically connected to the first electrode of each power device in second power device group.The 4th interconnecting member 414d is electrically connected to the second electrode of each power device in second power device group.
Integrated circuit package 400 comprises the second insulating barrier 415 and the first power bus 416a, the second source bus 416b and the 3rd power bus 416c that for outside, are electrically connected to.The second insulating barrier 415 is for example comprised of silica, is positioned on the surface of the first insulating barrier 413.The first power bus 416a, second source bus 416b and the 3rd power bus 416c are for example comprised of aluminium or copper, comprise respectively the planar extension that is arranged on the second insulating barrier 415 and through the second insulating barrier 415, contact a plurality of vertical channel parts of at least one interconnecting member of the first interconnecting member 414a, the second interconnecting member 414b, the 3rd interconnecting member 414c and the 4th interconnecting member 414d.
The planar extension separately of above-mentioned power bus is for example ribbon and parallel to each other.The bearing of trend of the bearing of trend of the planar extension of power bus and the extension of interconnecting member is parallel or intersect.Preferably, the bearing of trend of the bearing of trend of the planar extension of power bus and the extension of interconnecting member is perpendicular to one another.The first power bus 416a is electrically connected to the first interconnecting member 414a.Second source bus 416b is all electrically connected to the second interconnecting member 414b and the 3rd interconnecting member 414c.The 3rd power bus 416c is electrically connected to the 4th interconnecting member 414d.
In order to provide outside, be electrically connected to, between the first power bus 416a, second source bus 416b and the 3rd power bus 416c and lead frame, can be connected via conductive projection and/or soldered ball.In switch type regulator, the first power bus 416a is connected to voltage signal terminal Vin, and second source bus 416b is connected to switching node signal terminal LX, and the 3rd power bus 416c is connected to earth terminal GND.
The difference of the 4th embodiment and the 3rd embodiment is: in integrated circuit package 400, the second interconnecting member 414b, the 3rd interconnecting member 414c and second source bus 416b are segmentation, as shown in Fig. 5 b and 5c.Every section of the second interconnecting member 414b and every section of the 3rd interconnecting member 414c stagger.Every section of bearing of trend of second source bus 416b is vertical with every section of bearing of trend in the second interconnecting member 414b, the 3rd interconnecting member 414c, and connects a section in the second interconnecting member 414b a section and the 3rd interconnecting member 414c.The second interconnecting member 414b and the 3rd interconnecting member 414c link together the different sections of second source bus 416b.On the other hand, the different sections of second source bus 416b link together the different sections of the second interconnecting member 414b and the 3rd interconnecting member 414c.According to other parts of the integrated circuit package 400 of the 4th embodiment with identical according to the appropriate section of the integrated circuit package 100 of the 3rd embodiment.
Above-mentioned, according in the integrated circuit package 400 of the 4th embodiment, the power bus of segmentation and interconnecting member not only can improve the layout degree of freedom, and can reduce stress.In addition, the direction of current flow in the second interconnecting member 414b, the 3rd interconnecting member 414c is vertical with the direction of current flow in second source bus 416b.With respect to the first adjacent power bus 416a and the 3rd power bus 416b, electric current is along the flow direction of the second interconnecting member 414b, the 3rd interconnecting member 414c and second source bus 416b almost parallel sometimes, sometimes substantially vertical.Therefore, integrated circuit package 400 has further reduced stray inductance, has improved the electrical property of integrated circuit package.
Fig. 6 a, 6b, 6c and 6d illustrate respectively the decomposition diagram of the integrated circuit package that is applied to switch type regulator 500 according to a fifth embodiment of the invention, and the sectional view of AA, line B1B1 along the line and B2B2 intercepting.As shown in Figure 6 a, line AA is across not the first electrode and second electrode of power switch on the same group, and line B1B1 is across the second electrode of all power switchs of second group of power switch, and line B2B2 is across the second electrode of all power switchs of first group of power switch.
Integrated circuit package 500 comprises the first insulating barrier 513 and the first interconnecting member 514a, the second interconnecting member 514b, the 3rd interconnecting member 514c and the 4th interconnecting member 514d that for interlayer, are electrically connected to.The first insulating barrier 513 is for example comprised of silica, is positioned on the surface of semiconductor bare chip 410.The first interconnecting member 514a, the second interconnecting member 514b, the 3rd interconnecting member 514c and the 4th interconnecting member 514d are for example comprised of aluminium or copper, comprise respectively the planar extension that is positioned on the first insulating barrier 513 and through the first insulating barrier 513, contact a plurality of vertical channel parts of the electrode of power device.
The planar extension separately of above-mentioned interconnecting member is for example ribbon and parallel to each other.The first interconnecting member 514a is electrically connected to the first electrode of each power device in first power device group.The second interconnecting member 514b is electrically connected to the second electrode of each power device in first power device group.The 3rd interconnecting member 514c is electrically connected to the first electrode of each power device in second power device group.The 4th interconnecting member 514d is electrically connected to the second electrode of each power device in second power device group.
Integrated circuit package 500 comprises the second insulating barrier 515 and the first power bus 516a, the second source bus 516b and the 3rd power bus 516c that for outside, are electrically connected to.The second insulating barrier 515 is for example comprised of silica, is positioned on the surface of the first insulating barrier 513.The first power bus 516a, second source bus 516b and the 3rd power bus 516c are for example comprised of aluminium or copper, comprise respectively the planar extension that is arranged on the second insulating barrier 515 and through the second insulating barrier 515, contact a plurality of vertical channel parts of at least one interconnecting member of the first interconnecting member 514a, the second interconnecting member 514b, the 3rd interconnecting member 514c and the 4th interconnecting member 514d.
The planar extension separately of above-mentioned power bus is for example ribbon and parallel to each other.The bearing of trend of the planar extension of power bus intersects with the bearing of trend of the extension of interconnecting member.Preferably, the bearing of trend of the bearing of trend of the planar extension of power bus and the extension of interconnecting member is perpendicular to one another.The first power bus 516a is all electrically connected to the second interconnecting member 514b and the 4th interconnecting member 514d.Second source bus 516b is electrically connected to the 3rd interconnecting member 514c.The 3rd power bus 516c is electrically connected to the first interconnecting member 514a.
In order to provide outside, be electrically connected to, between the first power bus 516a, second source bus 516b and the 3rd power bus 516c and lead frame, can be connected via conductive projection and/or soldered ball.In switch type regulator, a part of the first power bus 516a can be used as voltage signal terminal LX, and a part of second source bus 516b can be used as switching node signal terminal Vin, and the 3rd power bus 516c is connected to earth terminal GND.
The difference of the 5th embodiment and the 3rd embodiment is: in integrated circuit package 500, the first interconnecting member 514a, the 3rd interconnecting member 514c and the 4th power bus 514d are segmentation, as shown in Fig. 5 b and 5c.Every section of the first interconnecting member 514a, the 3rd interconnecting member 514c and the 4th power bus 514d is staggered.The first power bus 516a is not only electrically connected the second interconnecting member 514b and the 4th interconnecting member 514d, and the different sections of the 4th interconnecting member 514d are electrically connected.Second source bus 516b is electrically connected the different sections of the 3rd interconnecting member 514c.The 3rd power bus 516c is electrically connected the different sections of the first interconnecting member 514a.According to other parts of the integrated circuit package 500 of the 5th embodiment with identical according to the appropriate section of the integrated circuit package 100 of the 3rd embodiment.
Above-mentioned, according in the integrated circuit package 500 of the 5th embodiment, the interconnecting member of segmentation not only can improve the layout degree of freedom, and can reduce stress.Even if the corresponding power device in a power device in first power device group and second power device group is spaced from each other, or centre arranges other elements, all power devices that also can utilize interconnecting member first to interconnect mutually on the same group, then utilize power bus to realize outside connection.Therefore, integrated circuit package 500 further provides the layout degree of freedom of power device.
Fig. 7 a, 7b, 7c and 7d illustrate respectively decomposition diagram, bottom view and the AA along the line of the package assembling that is applied to switch type regulator 1000 according to a fifth embodiment of the invention and the sectional view of line BB intercepting.As shown in Figure 7b, line AA extends along the length direction of a power bus wherein, and across the external pin of this power bus, line BB extends along the length direction of another power bus, and across the external pin of this power bus.
As example, in package assembling 1000, comprise the integrated circuit package 100 according to the first embodiment of the present invention.As described above, integrated circuit package 100 comprises semiconductor bare chip 110, the first power bus 116a, second source bus 116b and the 3rd power bus 116c, and the first insulating barrier 115.In semiconductor bare chip 110 inside, the first power bus 116a is electrically connected to each other the first electrode of first group of power device, second source bus 116b is electrically connected to each other the first electrode of the second electrode of first group of power device and second group of power device, and the 3rd power bus 116c is electrically connected to each other the second electrode of second group of power device.
Integrated circuit package 100 comprises a plurality of conductive projections 118 (and/or soldered ball).In Fig. 7 a, for the sake of clarity, conductive projection 118 is expressed as separated with integrated circuit package 100.Yet, should be appreciated that conductive projection 118 is actually a part for integrated circuit package 100.Each and at least one conductive projection of the first power bus 116a, second source bus 116b and the 3rd power bus 116c interconnects.Integrated circuit package 100 can also comprise the control chip (not shown) being formed on together with power device in semiconductor bare chip 110.The input and output electrode of control chip interconnects with conductive projection 118 respectively.
Integrated circuit package 100 is arranged on lead frame 600.For example, the conductive projection 118 of integrated circuit package 100 forms welding flux interconnected with the upper surface of the pin of lead frame 600.The pin of lead frame 600 comprises the first of the first thickness and the second portion of the second thickness, and wherein the first thickness is less than the second thickness.
Encapsulating compound 700 covers integrated circuit package 100, and covers at least a portion of lead frame 600.In lead frame 600, the first of pin is included in encapsulating compound 700, and the end of second portion or lower surface expose for outside and be electrically connected to.Each pin can comprise two or more second portions, thereby forms a plurality of external contacts.First and the second portion that can form pin by etching or the impression of selection area.
The bottom of package assembling 1000 has first to fourth bottom side.Described a plurality of pin comprises for first group of pin of power bus and for second group of pin of control chip.For example, described a plurality of pins are identical with the quantity of the external contact forming on the 4th bottom side at the first bottom side, and identical with the quantity of the external contact forming on the 3rd bottom side at the second bottom side.
In an example, the first pin 601a of lead frame 600 is connected with the first power bus 116a of integrated circuit package 100, the second pin 601b of lead frame 600 is connected with the second source bus 116b of integrated circuit package 100, and the 3rd pin 601c of lead frame 600 is connected with the 3rd power bus 116c of integrated circuit package 100.For example, the first pin 601a of lead frame 600 provides voltage signal terminal Vin, and the second pin 601b of lead frame 600 provides switching node signal terminal LX, and the 3rd pin 601c of lead frame 600 provides earth terminal GND.
The first pin 601a comprises three second portions of the first side that is positioned at package assembling 1000, the second pin 601b comprises each second portion that lays respectively at the second side of package assembling 1000 and the 3rd side, and the 3rd pin 601c comprises and lays respectively at the second side of package assembling 1000 and each second portion of the 3rd side and be positioned at a second portion in the middle of package assembling 1000.
Fig. 8 a, 8b, 8c, 8d and 8e illustrate respectively the sectional view of decomposition diagram, bottom view and AA, the line BB along the line of the package assembling that is applied to switch type regulator 2000 according to a sixth embodiment of the invention and the diverse location of line CC intercepting.As shown in Figure 8 b, line AA, line BB and line CC extend along the length direction of different electrical power bus respectively, and across the external pin of respective electrical source bus.
As example, in package assembling 2000, comprise the integrated circuit package 400 of a fourth embodiment in accordance with the invention.As described above, integrated circuit package 400 comprises semiconductor bare chip 410, the first power bus 416a, second source bus 416b and the 3rd power bus 416c, and the first insulating barrier 415.In semiconductor bare chip 410 inside, the first power bus 416a is electrically connected to each other the first electrode of first group of power device, second source bus 416b is electrically connected to each other the first electrode of the second electrode of first group of power device and second group of power device, and the 3rd power bus 416c is electrically connected to each other the second electrode of second group of power device.
Integrated circuit package 400 comprises a plurality of conductive projections 418 (and/or soldered ball).In Fig. 8 a, for the sake of clarity, conductive projection 418 is expressed as separated with integrated circuit package 400.Yet, should be appreciated that conductive projection 418 is actually a part for integrated circuit package 400.Each and at least one conductive projection of the first power bus 416a, second source bus 416b and the 3rd power bus 416c interconnects.Integrated circuit package 400 can also comprise the control chip (not shown) being formed on together with power device in semiconductor bare chip 410.The input and output electrode of control chip interconnects with conductive projection 418 respectively.
Integrated circuit package 400 is arranged on lead frame 600.For example, the conductive projection 418 of integrated circuit package 400 forms welding flux interconnected with the upper surface of the pin of lead frame 600.The pin of lead frame 600 comprises the first of the first thickness and the second portion of the second thickness, and wherein the first thickness is less than the second thickness.
Encapsulating compound 700 covers integrated circuit package 400, and covers at least a portion of lead frame 600.In lead frame 600, the first of pin is included in encapsulating compound 700, and the end of second portion or lower surface expose for outside and be electrically connected to.Each pin can comprise two or more second portions, thereby forms a plurality of external contacts.First and second portion that the first that can form pin by etching or the impression of selection area and second portion form pin.
The bottom of package assembling 2000 has first to fourth bottom side.Described a plurality of pin comprises for first group of pin of power bus and for second group of pin of control chip.For example, described a plurality of pins are identical with the quantity of the external contact forming on the 4th bottom side at the first bottom side, and identical with the quantity of the external contact forming on the 3rd bottom side at the second bottom side.
In an example, the first pin 601a of lead frame 600 is connected with the first power bus 416a of integrated circuit package 400, the second pin 601b of lead frame 600 is connected with the second source bus 416b of integrated circuit package 400, and the 3rd pin 601c of lead frame 600 is connected with the 3rd power bus 416c of integrated circuit package 400.For example, the first pin 601a of lead frame 600 provides voltage signal terminal Vin, and the second pin 601b of lead frame 600 provides switching node signal terminal LX, and the 3rd pin 601c of lead frame 600 provides earth terminal GND.
Referring to the 4th embodiment shown in Fig. 5 a, the second source bus 416b in integrated circuit package 400 is segmentation.In integrated circuit package 400 inside, the second interconnecting member 414b and the 3rd interconnecting member 414c link together the different sections of second source bus 416b, and be electrically connected to the second electrode of each power device in first power device group, thereby realize being electrically connected between second source bus 416b and power device.In integrated circuit package 400 outsides, the second pin 601b of lead frame 600 links together the different sections of second source bus 416b, thereby provides public outside to be electrically connected to, as shown in Fig. 8 d.
The first pin 601a comprises three second portions of the first side that is positioned at package assembling 2000, the second pin 601b comprises each second portion that lays respectively at the second side of package assembling 2000 and the 3rd side, and the 3rd pin 601c comprises and lays respectively at the second side of package assembling 2000 and each second portion of the 3rd side and be positioned at a second portion in the middle of package assembling 2000.Other pins of lead frame 600 can be used to the electrode of the control chip in semiconductor bare chip 410 to provide outside and be electrically connected to.
Different from the package assembling of prior art, in package assembling 1000 of the present invention and 2000, lead frame 600 is not only included at least one second portion of four the side exposures in bottom of package assembling, and comprise at least another second portion of the bottom zone line that is positioned at package assembling, for example mid portion shown in Fig. 7 b, Fig. 8 b.This mid portion can reduce contact resistance, improves current carrying capacity, and can be used as heat sink pad, improves the radiating effect of package assembling.
For example, conventional QFN encapsulation (QFN) comprises the die pad and a plurality of external connection terminals that are positioned at four sides in bottom of package assembling of the bottom zone line that is positioned at package assembling.At package assembling 1000 of the present invention and 2000, when being applied to QFN, adopt the second portion of the bottom zone line that is positioned at package assembling to replace die pad.Also,, in package assembling of the present invention, the bottom zone line of package assembling is also used as to external connection terminals and heat sink pad.
In the above-described embodiments, integrated circuit package and the package assembling that comprises power device and power bus described.
In alternative embodiment, can adopt at least one electronic device being selected from diode, transistor, resistance, inductance to replace power device.
In addition, in alternative embodiment, electronic device can be divided into m group, and each electronic device can comprise n electrode, and wherein m and n are greater than 1 integer.The first insulating barrier is positioned at the described surface of semiconductor bare chip.Integrated circuit package also comprises i power bus, comprises respectively the planar extension that is positioned on the first insulating barrier and through a plurality of vertical channel parts of each electrode of the first insulating barrier interface unit, and wherein i is greater than 1 and be less than or equal to the integer of m*n.At least one power bus in a described i power bus is electrically connected to each other an electrode of all devices at least two electronic device groups, and each in a described i power bus is connected to an external connection terminals.
Should be noted that, in this article, relational terms such as the first and second grades is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply and between these entities or operation, have the relation of any this reality or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby the process, method, article or the equipment that make to comprise a series of key elements not only comprise those key elements, but also comprise other key elements of clearly not listing, or be also included as the intrinsic key element of this process, method, article or equipment.The in the situation that of more restrictions not, the key element being limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
According to embodiments of the invention as described above, these embodiment do not have all details of detailed descriptionthe, and also not limiting this invention is only described specific embodiment.Obviously, according to above description, can make many modifications and variations.These embodiment are chosen and specifically described to this specification, is in order to explain better principle of the present invention and practical application, thereby under making, technical field technical staff can utilize the present invention and the modification on basis of the present invention to use well.The present invention is only subject to the restriction of claims and four corner and equivalent.
Claims (32)
1. an integrated circuit package, comprising:
Semiconductor bare chip, comprises a plurality of electronic devices that are divided into m group, and each electronic device comprises n electrode of opposed polarity, and wherein m and n are greater than 1 integer;
The first insulating barrier, is positioned at the described surface of semiconductor bare chip; And
I power bus, comprises respectively the planar extension that is positioned on the first insulating barrier and through a plurality of vertical channel parts of each electrode of the first insulating barrier interface unit, and wherein i is greater than 1 and be less than or equal to the integer of m*n,
Wherein, at least one power bus in a described i power bus is electrically connected to each other an electrode of all devices at least two electronic device groups, and
Each in a described i power bus is connected to an external connection terminals.
2. integrated circuit package according to claim 1, wherein
The planar extension of at least one the first power bus in a described i power bus is ribbon; And
The planar extension of at least one the second source bus in a described i power bus is sinuous polyline shaped, makes the direction of current flow of described at least one second source bus with respect to the direction of current flow change of described at least one the first power bus.
3. integrated circuit package according to claim 1, also comprises:
The second insulating barrier, between semiconductor bare chip and the first insulating barrier; And
J interconnecting member, comprises respectively the planar extension that is positioned on the second insulating barrier and through the second insulating barrier, is connected a plurality of vertical channel parts of each electrode of power device,
Wherein, at least two interconnecting members in a described j interconnecting member are electrically connected to each other an electrode of all devices in an electronic device group respectively, and
At least one power bus in a described i power bus is electrically connected to each other described at least two interconnecting members.
4. integrated circuit package according to claim 3, the plane bearing of trend of a wherein said i power bus is first direction, the plane bearing of trend of a described j interconnecting member is second direction, and first direction intersects with second direction.
5. integrated circuit package according to claim 4, wherein first direction is vertical with second direction.
6. integrated circuit package according to claim 3, wherein
At least one in a described j interconnecting member is segmentation, and at least one in a described i power bus is electrically connected the different sections of segmentation interconnecting member.
7. integrated circuit package according to claim 6, wherein
At least one in a described i power bus is segmentation.
8. integrated circuit package according to claim 7, wherein
The plane bearing of trend of the Segmented electrical source bus in a described i power bus, vertical with the plane bearing of trend of segmentation interconnecting member in a described j interconnecting member, make the direction of current flow in Segmented electrical source bus vertical with the direction of current flow in segmentation interconnecting member.
9. according to the integrated circuit package described in claim 7, wherein, at least one in a described j interconnecting member is electrically connected the different sections of Segmented electrical source bus.
10. according to the integrated circuit package described in claim 7, also comprise lead frame, described lead frame just at least two different sections of Segmented electrical source bus is electrically connected.
11. according to the integrated circuit package described in any one in claim 1-8, also comprises lead frame, and a wherein said i power bus is connected to described lead frame.
12. 1 kinds of integrated circuit packages that are applied to switch type regulator, comprising:
Semiconductor bare chip, comprises a plurality of power devices that are divided into two groups, and each power device is included in the first electrode and the second electrode exposing on the surface of semiconductor bare chip;
The first insulating barrier, is positioned at the described surface of semiconductor bare chip; And
The first to the 3rd power bus, comprises respectively the planar extension that is positioned on the first insulating barrier and through the first insulating barrier, is connected a plurality of vertical channel parts of each electrode of power device,
Wherein, the first power bus is electrically connected to each other the first electrode of first group of power device, second source bus is electrically connected to each other the first electrode of the second electrode of first group of power device and second group of power device, the 3rd power bus is electrically connected to each other the second electrode of second group of power device, and
Each in the first to the 3rd power bus is connected to an external connection terminals.
13. integrated circuit packages according to claim 12, wherein
First and the planar extension of the 3rd power bus be ribbon; And
The planar extension of second source bus is sinuous polyline shaped, makes the direction of current flow of second source bus with respect to the direction of current flow change of the first and the 3rd power bus.
14. integrated circuit packages according to claim 12, also comprise:
The second insulating barrier, between semiconductor bare chip and the first insulating barrier; And
First to fourth interconnecting member, comprises respectively the planar extension that is positioned on the second insulating barrier and through the second insulating barrier, is connected a plurality of vertical channel parts of each electrode of power device,
Wherein, the first interconnecting member is electrically connected to each other the first electrode of first group of power device, the second interconnecting member is electrically connected to each other the second electrode of first group of power device, the 3rd interconnecting member is electrically connected to each other the first electrode of second group of power device, the 4th interconnecting member is electrically connected to each other the second electrode of second group of power device, and
The first power bus connects the first interconnecting member, and second source bus connects the second and the 3rd interconnecting member, and the 3rd power bus connects the 4th interconnecting member.
15. integrated circuit packages according to claim 14, wherein the plane bearing of trend of the first to the 3rd power bus is first direction, the plane bearing of trend of first to fourth interconnecting member is second direction, and first direction intersects with second direction.
16. integrated circuit packages according to claim 14, wherein first direction is vertical with second direction.
17. integrated circuit packages according to claim 14, wherein
At least one of first to fourth interconnecting member is segmentation, and the first to the 3rd power bus is electrically connected the different sections of segmentation interconnecting member.
18. integrated circuit packages according to claim 17, wherein
At least one in the first to the 3rd power bus is segmentation.
19. integrated circuit packages according to claim 18, wherein
The second interconnecting member, the 3rd interconnecting member and second source bus are segmentation, every section of the second interconnecting member and every section of the 3rd interconnecting member stagger, and every section of bearing of trend of second source bus is vertical with every section of bearing of trend in the second interconnecting member, the 3rd interconnecting member, makes the direction of current flow in the second interconnecting member, the 3rd interconnecting member vertical with the direction of current flow in second source bus.
20. integrated circuit packages according to claim 18, wherein, described first to fourth interconnecting member is electrically connected the different sections of Segmented electrical source bus.
21. integrated circuit packages according to claim 18, also comprise lead frame, and described lead frame is electrically connected the different sections of Segmented electrical source bus.
22. according to the integrated circuit package described in any one in claim 12-19, also comprises lead frame, and the wherein said first to the 3rd power bus is connected to described lead frame.
23. 1 kinds of package assemblings, comprising:
According to the integrated circuit package described in any one in claim 12-22;
Lead frame, comprises a plurality of pins, and described integrated circuit package is arranged on described lead frame; And
Encapsulating compound, described encapsulating compound covers described integrated circuit package, and covers at least a portion of described lead frame, described a plurality of pin part is separately exposed and for outside, be electrically connected to.
24. package assemblings according to claim 23, wherein, described integrated circuit package comprises conductive projection, and the upper surface of described conductive projection and described pin forms welding flux interconnected.
25. package assemblings according to claim 24, wherein, described pin comprises the first of the first thickness and the second portion of the second thickness, wherein the second thickness is greater than the first thickness, the first of described pin is included in encapsulating compound, and the end of the second portion of described pin and/or lower surface expose for outside and are electrically connected to.
26. package assemblings according to claim 25, the bottom of described package assembling comprises four bottom sides, at least one pin in wherein said pin comprises two or more second portions, thereby forms a plurality of external contacts.
27. package assemblings according to claim 26, at least one second portion of wherein said at least one pin is positioned at the bottom zone line of package assembling, and at least another second portion is positioned near the bottom side of package assembling.
28. package assemblings according to claim 26, wherein said at least one pin is connected internally to a power bus in the described first to the 3rd power bus at package assembling.
29. package assemblings according to claim 25, at least one in the wherein said first to the 3rd power bus is segmentation, and at least one pin in described pin links together the different sections of the power bus of segmentation, thereby forms public external contact.
30. package assemblings according to claim 25, also comprise:
The control chip that comprises a plurality of input and output electrodes,
Wherein, the bottom of described package assembling has first to fourth bottom side, and described a plurality of pins comprise for first group of pin of power bus and for second group of pin of control chip,
The first power bus is connected with the first pin in first group of pin, a plurality of second portions that are positioned at the first bottom side that described the first pin comprises;
Second source bus is connected with the second pin in first group of pin, and described the second pin comprises a plurality of second portions that lay respectively at the second and the 3rd bottom side;
The 3rd power bus is connected with the 3rd pin in first group of pin, and described the 3rd pin comprises a plurality of second portions that lay respectively at the second and the 3rd bottom side and bottom zone line; And
Described a plurality of input and output electrodes of described control chip are connected to respectively a plurality of pins in second group of pin, and the described a plurality of pins in described second group of pin comprise and lay respectively at the second second portion to the 4th bottom side.
31. package assemblings according to claim 30, wherein, described a plurality of pin is identical with the quantity of the external contact forming on the 4th bottom side at the first bottom side, and identical with the quantity of the external contact forming on the 3rd bottom side at the second bottom side.
32. package assemblings according to claim 30, wherein, described a plurality of second portions of described the first pin provide in voltage signal terminal and earth terminal, described a plurality of second portions of described the 3rd pin provide another in voltage signal terminal and earth terminal, described a plurality of second portion switching node signal terminals of described the second pin.
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| CN2014100804332 | 2014-03-06 | ||
| CN201410242479.XA CN103985694B (en) | 2014-03-06 | 2014-05-30 | Integrated circuit package and package assembling thereof |
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| CN108807316A (en) * | 2017-08-14 | 2018-11-13 | 苏州捷芯威半导体有限公司 | Semiconductor package and semiconductor devices |
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| CN1893094A (en) * | 2005-06-30 | 2007-01-10 | 株式会社半导体能源研究所 | Semiconductor device and manufacturing method thereof |
| CN101523611A (en) * | 2006-10-04 | 2009-09-02 | 株式会社半导体能源研究所 | Semiconductor device and manufacturing method thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108807316A (en) * | 2017-08-14 | 2018-11-13 | 苏州捷芯威半导体有限公司 | Semiconductor package and semiconductor devices |
| CN108807316B (en) * | 2017-08-14 | 2020-07-10 | 苏州捷芯威半导体有限公司 | Semiconductor packaging structure and semiconductor device |
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| CN103824838A (en) | 2014-05-28 |
| CN103985694B (en) | 2016-11-02 |
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