CN103984268B - The input/output unit of a kind of signal logic controller and signal logic controller - Google Patents
The input/output unit of a kind of signal logic controller and signal logic controller Download PDFInfo
- Publication number
- CN103984268B CN103984268B CN201410232646.2A CN201410232646A CN103984268B CN 103984268 B CN103984268 B CN 103984268B CN 201410232646 A CN201410232646 A CN 201410232646A CN 103984268 B CN103984268 B CN 103984268B
- Authority
- CN
- China
- Prior art keywords
- input
- output
- differential
- shift register
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The invention discloses input/output unit and the signal logic controller of a kind of signal logic controller, described input/output unit includes: input equipment and/or output device；Described input equipment includes the input module of N number of cascade；Described output device includes M the output module cascaded；Each input module all includes the input submodule that two structures are identical；Described input submodule includes: differential receiver I；Differential driver I；Differential receiver II；Shift register I and shift register II；Each output module all includes the output sub-module that two structures are identical；Described output sub-module includes: differential receiver III；Differential driver III；Differential receiver IV；Shift register III and shift register IV；The present invention is easy to signal logic controller can need to carry out according to the actual IO of controlled device extension and the modularity setting of cascade structure, and the pin resource taking central processing unit is few, it is possible to meet the controlled device use demand to I/O resource easily.
Description
Technical field
The present invention relates to input and output and control technical field, the input of a kind of signal logic controller is defeated
Go out device and signal logic controller.
Background technology
Signal logic controller is that Crane Industry replaces PLC to realize input and output point information gathering and signal
The control electronics controlled.At present, in prior art, the signal logic controller of Crane Industry is used
Input/output unit be simple parallel communication structure, i.e. have how many I O point just to connect the most parallel winding displacement,
And there is no IO cascade function, so make the I O point number that can use limited, be unfavorable for field programming, account for simultaneously
Big with PCB fabric swatch area, the pin resource taking central processor core is many, and maintenance cost is high, equipment body
Long-pending big, it is impossible to realizing dexterous modular construction, a lot of situation I/O resource all can not meet use demand.
Summary of the invention
The present invention is directed to the proposition of problem above, and develop a kind of pin resource taking central processing unit few,
The input/output unit of the signal logic controller that volume is little and signal logic controller.
The technological means of the present invention is as follows:
The input/output unit of a kind of signal logic controller, described signal logic controller includes central authorities' process
Device, and be connected with the controlled device with input port and output port, including:
Input equipment and/or output device；Described input equipment one end connects controlled device output port, another
End connects central processing unit；Described output device one end connects central processing unit, and the other end connects controlled device
Input port；
Described input equipment includes the input module of N number of cascade, and wherein N is integer；
Described output device includes M the output module cascaded, and wherein M is integer；
Each input module all includes the input submodule that two structures are identical；Described input submodule includes:
For receiving difference control signal and described difference control signal being converted to the difference of single-ended control signal
Receptor I；
Connect differential receiver I, be converted to difference for the single-ended control signal exported by differential receiver I
The differential driver I of control signal；
For receiving differential data signals and described differential data signals being converted to the difference of single ended data signal
Receptor II；
Shift register I that parallel input terminal is connected with controlled device output port and shift register II；
Being incorporated to of described shift register I and shift register II seals in control end and input end of clock and described difference
The outfan of receptor I is connected；The serial input terminal of described shift register I connects described differential received
The outfan of device II；The serial input terminal of described shift register II connects the serial of described shift register I
Outfan；The serial output terminal of described shift register II connects differential driver II；
For receiving single ended data signal and described single ended data signal being converted to the difference of differential data signals
Driver II；
Each output module all includes the output sub-module that two structures are identical；Described output sub-module includes:
For receiving difference control signal and described difference control signal being converted to the difference of single-ended control signal
Receptor III；
Connect differential receiver III, be converted to difference for the single-ended control signal exported by differential receiver III
The differential driver III of control signal；
For receiving differential data signals and described differential data signals being converted to the difference of single ended data signal
Receptor IV；
Shift register III that parallel output terminal is connected with controlled device input port and shift register IV；
Described shift register III and shift register IV and go out to go here and there out control end and input end of clock and described difference
The outfan of receptor III is connected；The serial input terminal of described shift register III connects described differential received
The outfan of device IV；The serial input terminal of described shift register IV connects the serial of described shift register III
Outfan；The serial output terminal of described shift register IV connects differential driver IV；
For receiving single ended data signal and described single ended data signal being converted to the difference of differential data signals
Driver IV；
The input of the differential receiver I that the input submodule of N level includes connects described central processing unit,
The input of the differential receiver I that the input submodule of remaining N-1 level includes is sequentially connected with next stage input
The outfan of the differential driver I that module includes；The differential receiver II that the input submodule of the first order includes
Input unsettled, the input of differential receiver II that the input submodule of remaining N-1 level includes connects successively
Connecting the outfan of the differential driver II that one-level input submodule includes, the input submodule of N level includes
Differential driver II outfan connect described central processing unit；
The input of the differential receiver III that the output sub-module of the first order includes connects described central processing unit,
The input of the differential receiver III that the output sub-module of remaining M-1 level includes is sequentially connected with upper level output
The outfan of the differential driver III that module includes；The differential receiver IV that the output sub-module of the first order includes
Input connect described central processing unit, the differential receiver IV that the output sub-module of remaining M-1 level includes
Input be sequentially connected with the outfan of the differential driver IV that upper level output sub-module includes, M level
The outfan of the differential driver IV that output sub-module includes is unsettled；
Further, described shift register I and shift register II use 74HC165 chip；
Further, described shift register III and shift register IV use 74HC594 chip；
Further, described differential receiver I, differential receiver II, differential receiver III and differential received
Device IV uses 26LS32 chip；
Further, described differential driver I, differential driver II, differential driver III and differential driving
Device IV uses 26LS31 chip；
Further, the outfan of the differential driver II that the input submodule of N level includes is double by shielding
Twisted wire connects central processing unit, the input of the differential receiver II that the input submodule of remaining N-1 level includes
The outfan of the differential driver II that upper level input submodule includes all is connected by Shielded Twisted Pair；
Further, the input of the differential receiver IV that the output sub-module of the first order includes is double by shielding
Twisted wire connects described central processing unit, the differential receiver IV that the output sub-module of remaining M-1 level includes defeated
Enter end and all connected the outfan of the differential driver IV that upper level output sub-module includes by Shielded Twisted Pair；
Further, the parallel output terminal of described shift register III and shift register IV is defeated by relay
Go out circuit to be connected with controlled device input port；
Further, the outfan of the differential driver II that the input submodule of N level includes is anti-by triggering
Phase device connects described central processing unit.
A kind of signal logic controller, including the input/output unit described in any of the above-described item；N number of input module
2N included input submodule constitutes two-way input cascade structure；2M included by M output module
Output sub-module constitutes two-way output cascade structure；Described central processing unit is also defeated by two-way to controlled device
The data signal entering cascade structure input the most unanimously compares, and when inconsistent, described central processing unit produces
Raw warning message.
Owing to have employed technique scheme, the input and output of a kind of signal logic controller that the present invention provides
Device and signal logic controller, including the input equipment and/or the output device that use cascade structure, it is simple to letter
Number logic controller can need to carry out the extension of cascade structure according to the actual IO of controlled device and modularity sets
Putting, the pin resource taking central processing unit is few, it is possible to meet the controlled device use to I/O resource easily
Demand, application is flexible, and compact structure, beneficially field programming, the more market competitiveness solve existing skill
The input/output unit that in art, signal logic controller is used is simple parallel communication structure, and then makes
The problem that available I O point number is limited.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the input/output unit of signal logic controller of the present invention；
Fig. 2 is the structured flowchart of input module of the present invention；
Fig. 3 is the structured flowchart of output module of the present invention；
Fig. 4 is the structured flowchart of signal logic controller of the present invention.
Detailed description of the invention
The input/output unit of a kind of signal logic controller as shown in Figure 1 to Figure 3, described signal logic
Controller includes central processing unit, and is connected with the controlled device with input port and output port, bag
Include: input equipment and/or output device；Described input equipment one end connects controlled device output port, another
End connects central processing unit；Described output device one end connects central processing unit, and the other end connects controlled device
Input port；Described input equipment includes the input module of N number of cascade, and wherein N is integer；Described output
Device includes M the output module cascaded, and wherein M is integer；Each input module all includes two structures
Identical input submodule；Described input submodule includes: be used for receiving difference control signal and by described difference
Dividing control signal is converted to the differential receiver I of single-ended control signal；Connecting differential receiver I, being used for will
The single-ended control signal of differential receiver I output is converted to the differential driver I of difference control signal；For
Receive differential data signals and described differential data signals is converted to the differential receiver of single ended data signal
Ⅱ；Shift register I that parallel input terminal is connected with controlled device output port and shift register II；
Being incorporated to of described shift register I and shift register II seals in control end and input end of clock and described difference
The outfan of receptor I is connected；The serial input terminal of described shift register I connects described differential received
The outfan of device II；The serial input terminal of described shift register II connects the serial of described shift register I
Outfan；The serial output terminal of described shift register II connects differential driver II；For receiving single-ended number
Described single ended data signal is also converted to the differential driver II of differential data signals by the number of it is believed that；Each output
Module all includes the output sub-module that two structures are identical；Described output sub-module includes: be used for receiving difference
Described difference control signal is also converted to the differential receiver III of single-ended control signal by control signal；It is poor to connect
Divide receptor III, be converted to difference control signal for the single-ended control signal exported by differential receiver III
Differential driver III；For receiving differential data signals and described differential data signals being converted to single ended data
The differential receiver IV of signal；The shift register III that parallel output terminal is connected with controlled device input port
With shift register IV；Described shift register III and shift register IV and go out to go here and there out control end and clock
Input is connected with the outfan of described differential receiver III；The serial input terminal of described shift register III
Connect the outfan of described differential receiver IV；The serial input terminal of described shift register IV connects described shifting
The serial output terminal of bit register III；The serial output terminal of described shift register IV connects differential driver IV；
For receiving single ended data signal and described single ended data signal being converted to the differential driving of differential data signals
Device IV；The input of the differential receiver I that the input submodule of N level includes connects described central processing unit,
The input of the differential receiver I that the input submodule of remaining N-1 level includes is sequentially connected with next stage input
The outfan of the differential driver I that module includes；The differential receiver II that the input submodule of the first order includes
Input unsettled, the input of differential receiver II that the input submodule of remaining N-1 level includes connects successively
Connecting the outfan of the differential driver II that one-level input submodule includes, the input submodule of N level includes
Differential driver II outfan connect described central processing unit；The difference that the output sub-module of the first order includes
The input dividing receptor III connects described central processing unit, the difference that the output sub-module of remaining M-1 level includes
The input dividing receptor III is sequentially connected with the output of the differential driver III that upper level output sub-module includes
End；The input of the differential receiver IV that the output sub-module of the first order includes connects described central processing unit,
The input of the differential receiver IV that the output sub-module of remaining M-1 level includes is sequentially connected with upper level output
The outfan of the differential driver IV that module includes, the differential driver IV that the output sub-module of M level includes
Outfan unsettled；Further, described shift register I and shift register II use 74HC165 core
Sheet；Further, described shift register III and shift register IV use 74HC594 chip；Further
Ground, described differential receiver I, differential receiver II, differential receiver III and differential receiver IV use
26LS32 chip；Further, described differential driver I, differential driver II, differential driver III and
Differential driver IV uses 26LS31 chip；Further, the difference that the input submodule of N level includes is driven
The outfan of dynamic device II connects central processing unit, the input submodule bag of remaining N-1 level by Shielded Twisted Pair
The input of the differential receiver II included all connects, by Shielded Twisted Pair, the difference that upper level input submodule includes
Divide the outfan of driver II；Further, the differential receiver IV that the output sub-module of the first order includes
Input connects described central processing unit by Shielded Twisted Pair, and the output sub-module of remaining M-1 level includes
The difference that the input of differential receiver IV is all included by Shielded Twisted Pair connection upper level output sub-module is driven
The outfan of dynamic device IV；Further, described shift register III and the parallel output terminal of shift register IV
It is connected with controlled device input port by outputting circuit for relay；Further, input of N level
The outfan of the differential driver II that module includes connects described central processing unit by triggering phase inverter；Described
Trigger phase inverter and use 74HC14 chip.
A kind of signal logic controller as shown in Figure 1 and Figure 4, defeated including the input described in any of the above-described item
Go out device；2N input submodule included by N number of input module constitutes two-way input cascade structure；M
2M output sub-module included by output module constitutes two-way output cascade structure；Described central processing unit is also
Controlled device is the most unanimously compared, when differing by the data signal of two-way input cascade structure input
During cause, described central processing unit produces warning message；As shown in Figure 4, signal logic controller of the present invention
In addition to including central processing unit, input equipment, output device, also include being connected with central processing unit
Analog input differential receiver, Analog control differential driver, encoder input difference receptor, see
Door Canis familiaris L. circuit, ferroelectric memory, peripheral storage, JTAG emulation interface, AS DLL, key circuit,
LCD shows and backlight lamp control circuit and PIC single chip microcomputer, and the master station communication being connected with PIC single chip microcomputer
Unit, slave station communication unit, BCD address dial-up circuit, PIC32 download interface and watchdog circuit etc..
The parallel data such as scene that controlled device output port can be exported by the present invention by described input equipment
Collection information is converted to high-speed serial data and is supplied to central processing unit, simultaneously permissible by described output device
The serial data such as control instruction information that central processing unit sends is converted to parallel data and controls controlled device, N
Individual input module cascades, and each input module includes the input submodule that two structures are identical, and then constitutes two
Road input cascade structure, two-way input cascade structure is mutually redundant structure, and M output module cascades, each defeated
Going out the output sub-module that module includes that two structures are identical, and then constitute two-way output cascade structure, two-way is defeated
Going out cascade structure and be mutually redundant structure, wherein N and M is integer, specifically can be according to actual design demand
Set；Described central processing unit runs two sets completely self-contained input and output point scanning imaging system simultaneously, and to quilt
Control equipment is the most unanimously compared, when inconsistent by the data signal of two-way input cascade structure input
Described central processing unit produces warning message, and the data signal of transmission is also simple two-way signal, in order to through logic
With computing, jointly guarantee to export correct duty, play protection security of system and increase the work of reliability
With.
Present invention could apply to Crane Industry, it is achieved signal logic controller and this quilt of crane system
Signal high speed serial communication between control equipment and cascade Mach-Zehnder interferometer；Described shift register I and shift register
II is connected with the output port of controlled device by input point testing circuit；Described shift register III and shifting
Bit register IV is connected with the input port of controlled device by outputting circuit for relay.
The input point (the controlled device output port i.e. connected) setting each input module has 16 tunnels, often
The output point (the controlled device input port i.e. connected) of one output module has 16 tunnels, when needs are by IO
In the case of scan period controls within 0.1ms, the input module of every signal logic controller and output
Each 5 pieces of module, then input equipment and output device are able to realize 80 way switch amount inputs, 80 way switch
The information gathering of amount output and logic control function, as cascaded more IO input/output module, often increase by one
Block, I/O scan cycle stretch-out is less than 20us, i.e. 0.02ms, further input equipment and output device and realizes
16*N way switch amount input signal, the signals collecting of 16*M way switch amount output signal and logic control function；
Signal logic controller can carry out module according to actually entering output point quantity to input equipment and output device
Change configuration, to meet respective input and output needs；Meanwhile, the present invention input equipment, output device with
During central processing unit and controlled device carry out signal transmission, differential signal transmission mode is used to subtract
The few site environment various interference to signal logic controller, and then the reliability of enhancing signal transmission.
During actual application, the present invention is constituted between each input submodule of input cascade structure, and constitutes defeated
Going out can use DB socket and plug to be attached between each output module of cascade structure, uses corresponding simultaneously
Fixture strengthens the stability of connector, additionally for preventing wrong plug, between different input modules and difference
Different number of DB socket and plug can be used respectively between output module.In the selection of transmission cable,
Use the pair cable differential signal transmission on band shielding ground.
By the structure of input equipment of the present invention, the input module phase that controlled device output port cascades with each
Connect, for first order input submodule (i.e. arbitrary input submodule included by input module 1 in figure)
For, the parallel data of controlled device output port is converted to serial data by shift register I, and with
Serial manner reaches shift register II, and its parallel input terminal can be received by shift register II with timesharing
The parallel data that controlled device output port transmits is converted to serial data and is exported by serial output terminal, with
And the serial data that the shift register I received by its serial input terminal exports is exported by serial output terminal, defeated
The serial data gone out is transformed to the transmission of corresponding differential data signals via differential driver II and inputs to the second level
Submodule (i.e. included by input module 2 one input submodule in figure), second level input submodule is to the
The controlled device that its parallel input terminal all can be received by the shift register I in N level input submodule with timesharing
The parallel data that output port transmits is converted to serial data and is exported by serial output terminal, and is gone here and there
The serial data of the upper level input submodule output that row input receives is exported by serial output terminal, and will string
The transmission of row data is to shift register II, the displacement in second level input submodule to N level input submodule
Depositor II function is identical with shift register II function in first order input submodule, N level input
The converting serial data of reception is to be transferred to centre after differential data signals by the differential driver II in module
Reason device；The input of the differential receiver I that the input submodule of N level includes connects described central processing unit,
Realize moving for controlling shift register I and shift register II for receive that central processing unit sends over
The clock pulses of bit manipulation and be incorporated to seal in control signal, described in be incorporated to seal in control signal for controlling defeated
The parallel data or the serial data that enter shift, and clock pulses here with being incorporated to seal in control signal is all
Differential signalling form, differential receiver I is by the clock pulses of differential signalling form and is incorporated to seal in control signal
Be converted to corresponding single-ended signal and be transferred to shift register I, shift register II and differential driver respectively
I, shift register I and shift register II are according to the clock pulses received and to be incorporated to seal in control signal complete
Becoming to be incorporated to go here and there out or seal in the shifting function gone here and there out, differential driver I is by the clock pulses of single-ended signal form
Be converted to differential signalling form be transferred to N-1 level input submodule, remaining N-1 with being incorporated to seal in control signal
The input of the differential receiver I that the input submodule of level includes is sequentially connected with next stage input submodule and includes
The outfan of differential driver I, for receiving the shift control signal transmitted from central processing unit,
Being incorporated to of the shift register I of each input submodule and shift register II seals in control end and clock input
End is sequentially connected with the outfan of differential receiver I；The structure respectively constituted by 2N input submodule is identical
Two-way input cascade structure all uses above-mentioned work process.
Central processing unit of the present invention includes that MCU or FPGA, described central processing unit can use difference to connect
Receive chip and receive the differential data signals that input equipment transmits, and be converted into single ended data signal, afterwards
Meet 74HC14 and trigger phase inverter, the single ended data signal of reception can be converted into clearly, the output of non-jitter is believed
Number it is supplied to FPGA or MCU and gathers information.
By the structure of output device of the present invention, the output module phase that controlled device input port cascades with each
Connect, for first order output sub-module (i.e. arbitrary output sub-module included by output module 1 in figure)
For, the serial data that central processing unit sends such as control instruction information is transferred to shift register III, described
The serial data that serial input terminal receives can be converted to parallel data by the most defeated with timesharing by shift register III
Go out end and be transferred to controlled device input port, and by the serial data that receives by serial output terminal with serial
Mode reaches shift register IV, the serial number that its serial input terminal can be received by shift register IV with timesharing
It is transferred to controlled device input port, and the serial that will receive by parallel output terminal according to being converted to parallel data
Data are exported by serial output terminal, and the serial data of output is transformed to corresponding difference via differential driver IV
Data signal transmission is to a second level output sub-module (i.e. output submodule included by output module 2 in figure
Block), the shift register I in second level output sub-module to M level output sub-module all can be with timesharing by upper
The serial data that one-level output sub-module transmits is converted to parallel data and is transferred to by parallel output terminal controlled
Equipment input port, and the serial data that upper level output sub-module is transmitted by serial output terminal with
Serial manner reaches shift register IV, the shifting in second level output sub-module to M level output sub-module
Bit register IV function is identical with shift register IV function in first order output sub-module, and M level exports
Differential driver IV in submodule (output sub-module included by afterbody output module) is when being not required to
When continuing cascade, its outfan can be unsettled；The differential receiver III that the output sub-module of the first order includes
Input connect described central processing unit, for receive that central processing unit sends over for controlling displacement
Depositor III and shift register IV realize shifting function clock pulses and and go out to go here and there out control signal, described
And go out to go here and there out control signal for exporting parallel data or serial data, clock pulses here and and go out to go here and there out
Control signal is all differential signalling form, and differential receiver III is by the clock pulses of differential signalling form and and goes out
Control signal of going here and there out is converted to corresponding single-ended signal and is transferred to shift register III, shift register IV respectively
According to the clock pulses received and and string is gone out with differential driver III, shift register III and shift register IV
Going out control signal and complete to seal in the shifting function gone here and there out or seal in and go out, differential driver III is by single-ended signal shape
The clock pulses of formula and and go out to go here and there out control signal be converted to differential signalling form be transferred to the second level output submodule
Block, it is defeated that the input of the differential receiver III that the output sub-module of remaining M-1 level includes is sequentially connected with upper level
Go out the outfan of the differential driver III that submodule includes, for receiving the shifting transmitted from central processing unit
Position control signal, the shift register III of each output sub-module and shift register IV and go out to go here and there out control
End and input end of clock are sequentially connected with the outfan of differential receiver III；Respectively constituted by 2M output sub-module
The identical two-way output cascade structure of structure all use above-mentioned work process.
The input/output unit of a kind of signal logic controller that the present invention provides and signal logic controller, bag
Include input equipment and/or the output device using cascade structure, it is simple to signal logic controller can be according to controlled
The actual IO of equipment needs to carry out the extension of cascade structure and modularity is arranged, and takies the pin of central processing unit
Resource is few, it is possible to meet the controlled device use demand to I/O resource easily, and application is flexible, compact structure,
It is beneficial to field programming, the more market competitiveness, solves what signal logic controller in prior art was used
Input/output unit is simple parallel communication structure, and then makes the limited problem of the I O point number that can use, this
Invention both can be applicable to crane machinery industry market, it is possible in being applied to, extensive logic control is with the most logical
The relatively fixing Enterprise Equipment Management System of news；It addition, use differential signal transmission mode and utilize shielding
Twisted-pair feeder be easy to reduce the site environment various interference to signal logic controller, and then enhancing signal transmission
Reliability；Each input module includes the input submodule that two structures are identical, and N number of input module constitutes two-way
Input cascade structure, each output module includes the output sub-module that two structures are identical, N number of output module structure
Become two-way output cascade structure, strengthen data transmission and the safety processed, increase system reliability.
The above, the only present invention preferably detailed description of the invention, but protection scope of the present invention not office
Being limited to this, any those familiar with the art is in the technical scope that the invention discloses, according to this
The technical scheme of invention and inventive concept thereof in addition equivalent or change, all should contain the protection in the present invention
Within the scope of.
Claims (10)
1. an input/output unit for signal logic controller, described signal logic controller includes centre
Reason device, and be connected with the controlled device with input port and output port, it is characterised in that including:
Input equipment and output device；Described input equipment one end connects controlled device output port, the other end
Connect central processing unit；Described output device one end connects central processing unit, and it is defeated that the other end connects controlled device
Inbound port；
Described input equipment includes the input module of N number of cascade, and wherein N is integer；
Described output device includes M the output module cascaded, and wherein M is integer；
Each input module all includes the input submodule that two structures are identical；Described input submodule includes:
For receiving difference control signal and described difference control signal being converted to the difference of single-ended control signal
Receptor I；
Connect differential receiver I, be converted to difference for the single-ended control signal exported by differential receiver I
The differential driver I of control signal；
For receiving differential data signals and described differential data signals being converted to the difference of single ended data signal
Receptor II；
Shift register I that parallel input terminal is connected with controlled device output port and shift register II；
Being incorporated to of described shift register I and shift register II seals in control end and input end of clock and described difference
The outfan of receptor I is connected；The serial input terminal of described shift register I connects described differential received
The outfan of device II；The serial input terminal of described shift register II connects the serial of described shift register I
Outfan；The serial output terminal of described shift register II connects differential driver II；
For receiving single ended data signal and described single ended data signal being converted to the difference of differential data signals
Driver II；
Each output module all includes the output sub-module that two structures are identical；Described output sub-module includes:
For receiving difference control signal and described difference control signal being converted to the difference of single-ended control signal
Receptor III；
Connect differential receiver III, be converted to difference for the single-ended control signal exported by differential receiver III
The differential driver III of control signal；
For receiving differential data signals and described differential data signals being converted to the difference of single ended data signal
Receptor IV；
Shift register III that parallel output terminal is connected with controlled device input port and shift register IV；
Described shift register III and shift register IV and go out to go here and there out control end and input end of clock and described difference
The outfan of receptor III is connected；The serial input terminal of described shift register III connects described differential received
The outfan of device IV；The serial input terminal of described shift register IV connects the serial of described shift register III
Outfan；The serial output terminal of described shift register IV connects differential driver IV；
For receiving single ended data signal and described single ended data signal being converted to the difference of differential data signals
Driver IV；
The input of the differential receiver I that the input submodule of N level includes connects described central processing unit,
The input of the differential receiver I that the input submodule of remaining N-1 level includes is sequentially connected with next stage input
The outfan of the differential driver I that module includes；The differential receiver II that the input submodule of the first order includes
Input unsettled, the input of differential receiver II that the input submodule of remaining N-1 level includes connects successively
Connecting the outfan of the differential driver II that one-level input submodule includes, the input submodule of N level includes
Differential driver II outfan connect described central processing unit；
The input of the differential receiver III that the output sub-module of the first order includes connects described central processing unit,
The input of the differential receiver III that the output sub-module of remaining M-1 level includes is sequentially connected with upper level output
The outfan of the differential driver III that module includes；The differential receiver IV that the output sub-module of the first order includes
Input connect described central processing unit, the differential receiver IV that the output sub-module of remaining M-1 level includes
Input be sequentially connected with the outfan of the differential driver IV that upper level output sub-module includes, M level
The outfan of the differential driver IV that output sub-module includes is unsettled.
The input/output unit of a kind of signal logic controller the most according to claim 1, its feature exists
74HC165 chip is used in described shift register I and shift register II.
The input/output unit of a kind of signal logic controller the most according to claim 1, its feature exists
74HC594 chip is used in described shift register III and shift register IV.
The input/output unit of a kind of signal logic controller the most according to claim 1, its feature exists
26LS32 is used in described differential receiver I, differential receiver II, differential receiver III and differential receiver IV
Chip.
The input/output unit of a kind of signal logic controller the most according to claim 1, its feature exists
26LS31 is used in described differential driver I, differential driver II, differential driver III and differential driver IV
Chip.
The input/output unit of a kind of signal logic controller the most according to claim 1, its feature exists
The outfan inputting the differential driver II that submodule includes in N level connects central authorities by Shielded Twisted Pair
Processor, the input of the differential receiver II that the input submodule of remaining N-1 level includes is all double by shielding
Twisted wire connects the outfan of the differential driver II that upper level input submodule includes.
The input/output unit of a kind of signal logic controller the most according to claim 1, its feature exists
The input of the differential receiver IV included in the output sub-module of the first order connects described by Shielded Twisted Pair
Central processing unit, the input of the differential receiver IV that the output sub-module of remaining M-1 level includes is all by screen
Cover the outfan of the differential driver IV that twisted pair line connection upper level output sub-module includes.
The input/output unit of a kind of signal logic controller the most according to claim 1, its feature exists
Parallel output terminal in described shift register III and shift register IV passes through outputting circuit for relay with controlled
Equipment input port is connected.
The input/output unit of a kind of signal logic controller the most according to claim 1, its feature exists
The outfan inputting the differential driver II that submodule includes in N level connects described by triggering phase inverter
Central processing unit.
10. a signal logic controller, it is characterised in that include described in any one of claim 1 to 9
Input/output unit；2N input submodule included by N number of input module constitutes two-way input cascade structure；
2M output sub-module included by M output module constitutes two-way output cascade structure；Described central authorities process
Controlled device is also the most unanimously compared by device by the data signal of two-way input cascade structure input, when
Time inconsistent, described central processing unit produces warning message.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410232646.2A CN103984268B (en) | 2014-05-28 | 2014-05-28 | The input/output unit of a kind of signal logic controller and signal logic controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410232646.2A CN103984268B (en) | 2014-05-28 | 2014-05-28 | The input/output unit of a kind of signal logic controller and signal logic controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103984268A CN103984268A (en) | 2014-08-13 |
| CN103984268B true CN103984268B (en) | 2016-11-23 |
Family
ID=51276287
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410232646.2A Active CN103984268B (en) | 2014-05-28 | 2014-05-28 | The input/output unit of a kind of signal logic controller and signal logic controller |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103984268B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107977332A (en) * | 2017-11-13 | 2018-05-01 | 浪潮金融信息技术有限公司 | The input and output control panel of self-aided terminal |
| CN108108319A (en) * | 2017-11-15 | 2018-06-01 | 北京橄榄家园科技有限公司 | Turn the Intelligent electronic toy of serial input reading manner based on parallel input |
| CN108107753B (en) * | 2017-11-15 | 2021-12-31 | 北京小探客科技有限公司 | Intelligent electronic toy |
| CN109256097A (en) * | 2018-11-16 | 2019-01-22 | 合肥惠科金扬科技有限公司 | A kind of backlight circuit, back lighting device and display device |
| CN109752992B (en) * | 2018-12-06 | 2022-01-21 | 贵州航天电子科技有限公司 | FPGA +8051 system controller |
| CN110109414A (en) * | 2019-06-12 | 2019-08-09 | 盈春 | A kind of logic controller system |
| CN117155372B (en) * | 2023-09-06 | 2024-02-06 | 苏州异格技术有限公司 | Input/output driver structure, input/output control method and communication system |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201373993Y (en) * | 2008-11-18 | 2009-12-30 | Abb股份有限公司 | Flexibly expanded central component of automation equipment |
| CN102591244A (en) * | 2012-03-26 | 2012-07-18 | 中国科学院自动化研究所 | Bus-based input/output (IO) acquisition and control extending device |
| CN102981996A (en) * | 2012-11-26 | 2013-03-20 | 福州瑞芯微电子有限公司 | Expansion device and method for periphery interfaces |
| DE102011120954A1 (en) * | 2011-12-14 | 2013-06-20 | Phoenix Contact Gmbh & Co. Kg | Multifunctional input / output module |
| CN103439905A (en) * | 2013-08-29 | 2013-12-11 | 广州视源电子科技股份有限公司 | IO input port expanded circuit |
| CN203858480U (en) * | 2014-05-28 | 2014-10-01 | 大连美恒时代科技有限公司 | Input-output device of signal logic controller and signal logic controller |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN203588020U (en) * | 2013-11-20 | 2014-05-07 | 浙江亚龙教育装备股份有限公司 | Logic control circuit |
-
2014
- 2014-05-28 CN CN201410232646.2A patent/CN103984268B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201373993Y (en) * | 2008-11-18 | 2009-12-30 | Abb股份有限公司 | Flexibly expanded central component of automation equipment |
| DE102011120954A1 (en) * | 2011-12-14 | 2013-06-20 | Phoenix Contact Gmbh & Co. Kg | Multifunctional input / output module |
| WO2013087302A1 (en) * | 2011-12-14 | 2013-06-20 | Phoenix Contact Gmbh & Co. Kg | Multifunctional input/output module |
| CN102591244A (en) * | 2012-03-26 | 2012-07-18 | 中国科学院自动化研究所 | Bus-based input/output (IO) acquisition and control extending device |
| CN102981996A (en) * | 2012-11-26 | 2013-03-20 | 福州瑞芯微电子有限公司 | Expansion device and method for periphery interfaces |
| CN103439905A (en) * | 2013-08-29 | 2013-12-11 | 广州视源电子科技股份有限公司 | IO input port expanded circuit |
| CN203858480U (en) * | 2014-05-28 | 2014-10-01 | 大连美恒时代科技有限公司 | Input-output device of signal logic controller and signal logic controller |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103984268A (en) | 2014-08-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103984268B (en) | The input/output unit of a kind of signal logic controller and signal logic controller | |
| US3924240A (en) | System for controlling processing equipment | |
| DE3422363A1 (en) | METHOD AND DEVICE FOR DATA TRANSFER | |
| CN109429016B (en) | Display control system | |
| EP1617337A2 (en) | Galvanic separation by means of radio technologies | |
| DE102011114077A1 (en) | PLC system | |
| CN102981431A (en) | Nuclear power station diversity protective system hardware architecture based on field programmable gate array (FPGA) | |
| CN107682667A (en) | Video processor and multisignal source premonitoring method | |
| CN205353663U (en) | Extensible multichannel IO interface board | |
| CN102012884A (en) | Kvm management system and method of providing adaptable synchronization signal | |
| CN109683593A (en) | A kind of impulse type servo-driver Basic function testing method and apparatus | |
| CN203858480U (en) | Input-output device of signal logic controller and signal logic controller | |
| CN102780598B (en) | A kind of bus communication, bus communication unit and system | |
| DE102011105712B4 (en) | Coupling device for communication devices | |
| CN206848803U (en) | MVB failure simulation device | |
| CN203232419U (en) | Bus input/output interface circuit | |
| CN103186248B (en) | Remote management system and remote management method thereof | |
| CN107024921A (en) | MVB failure simulation device | |
| CN105259784B (en) | Signalling coding method towards electric system simulation and its high-speed data transmission method | |
| WO1994024647A1 (en) | Control cubicle with data bus | |
| CN202904288U (en) | FPGA (field-programmable gate array) based nuclear power station diversity protection system hardware architecture | |
| CN204495966U (en) | A kind of straight-throughization proving installation of low-power consumption differential transfer chip | |
| CN107272915B (en) | Intelligent intrinsic safety communication keyboard device | |
| CN203595923U (en) | RS485 star-type photoelectric hybrid transmission equipment | |
| DE202011003748U1 (en) | screwsystem |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20181206 Address after: 116023 No. 35 Torch Road, Qixianling, Dalian High-tech Industrial Park, Liaoning Province Patentee after: MH Automation Dalian Co., Ltd. Address before: 116023 No. 35 Torch Road, Qixianling, Dalian High-tech Zone, Liaoning Province Patentee before: Dalian MH Times Technology Co., Ltd. |
|
| TR01 | Transfer of patent right |