CN103973296B - A kind of two-seat cabin instruction integrated approach and its circuit based on sequential logic - Google Patents
A kind of two-seat cabin instruction integrated approach and its circuit based on sequential logic Download PDFInfo
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- CN103973296B CN103973296B CN201310034327.6A CN201310034327A CN103973296B CN 103973296 B CN103973296 B CN 103973296B CN 201310034327 A CN201310034327 A CN 201310034327A CN 103973296 B CN103973296 B CN 103973296B
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Abstract
The invention belongs to digital circuit technique field, is related to a kind of two-seat cabin instruction integrated approach and its circuit based on sequential logic.To the effective two-seat cabin instruction synthetic circuit of instruction, the circuit judges instruction input after one kind（1）And instruction input（2）The time of transmission, and the instruction output after synthesis is used as using the newest instruction sent.The present invention can be such that the instruction transmission in forward and backward cabin is not limited by other side's command status；The use for more meeting people using the control principle after the logic of the present invention recognizes custom.
Description
Technical field
The invention belongs to digital circuit technique field, be related to a kind of two-seat cabin instruction integrated approach based on sequential logic and
Its circuit.
Background technology
The needs of flight training and increasingly complicated operational environment force aircraft the form of two-seat cabin occur, therewith with regard to band
The problem of how two-seat cabin control instruction carries out logic synthesis carried out.Instruction integrated logic common at present has two kinds, the first
It is exactly that universal authority mask logic is applied on trainer aircraft, this logic assigns coach with highest control authority so that
The instruction output of coach can mask the instruction output of student at any time, to correct the faulty operation of student；The
Two kinds are to apply more logic in parallel on current domestic two-seat cabin fighter plane, and this logic passes through two of forward and backward cockpit
Instruct simple parallel connection to realize, but export 1 two instruction outputs when being exactly positive connect the problem of this way is brought and be or patrol
Volume, and 0 two outputs are exported when reversely disconnecting and have been reformed into and logic, it is necessary to two input instructions are all that off-state could most
Output open command eventually, as shown in Fig. 1 and following table.
| in1 | in2 | out |
| 1 | 0 | 1 |
| 0 | 1 | 1 |
| 1 | 1 | 1 |
| 0 | 0 | 0 |
The content of the invention
The purpose of the present invention is：Integrated logic is instructed to the effective two-seat cabin of instruction after realizing one kind for two-seat cabin aircraft,
So that forward and backward cockpit can be sent when needed is effectively switched on or switched off instruction, do not limited by the opposing party's command status；
There is provided a kind of circuit for realizing the instruction integrated logic simultaneously.
The technical scheme is that：As shown in Fig. 2 to effective two-seat cabin instruction synthetic circuit is instructed after one kind, should
The time that circuit judges instruction input 1 and instruction input 2 are sent, and it is defeated as the instruction after synthesis using the newest instruction sent
Go out.
As shown in figure 3, a kind of described two-seat cabin instruction synthetic circuit based on sequential logic, including the first d type flip flop
3rd, the second d type flip flop 4,3d flip-flop 5, four d flip-flop 6, the first XOR gate 7, the second XOR gate 8 and OR gate 9；Its
In,
The input termination instruction input 1 of first d type flip flop 3, output the second d type flip flop 4 of termination of the first d type flip flop 3
The first input end of input, the first input end of the first XOR gate 7 and OR gate 9, the clearing termination the of the first d type flip flop 3
The output end of two XOR gates 8；Second input of output the first XOR gate 7 of termination of the second d type flip flop 4, the second d type flip flop 4
Clearing termination the second XOR gate 8 output end；
The input termination instruction input 2 of four d flip-flop 6, the output termination 3d flip-flop 5 of four d flip-flop 6
Second input of input, the first input end of the second XOR gate 8 and OR gate 9, the clearing termination the of four d flip-flop 6
The output end of one XOR gate 7；Second input of output the second XOR gate 8 of termination of 3d flip-flop 5,3d flip-flop 5
Clearing termination the first XOR gate 7 output end；
The output end output output order 10 of OR gate 9.
A kind of two-seat cabin instruction integrated approach based on sequential logic, comprises the following steps：
The first step, instruction input 1 is input to the first d type flip flop 3 and two bit shifts of the second d type flip flop 4 composition are posted
In storage, instruction input 2 is input in two bit shift registers that 3d flip-flop 5 and four d flip-flop 6 form；
Second step, in two bit shift registers, the previous moment state output of instruction input 1 is given second by the first d type flip flop 3
D type flip flop 4, preserve instruction input 1 current time state and output it to the first XOR gate 7, the second d type flip flop 4, which preserves, to be referred to
Order 1 previous moment state of input simultaneously outputs it to the first XOR gate 7；
In two bit shift registers, four d flip-flop 6 gives the previous moment state output of instruction input 2 to 3d flip-flop
5, preserve instruction input 2 current time state and output it to the second XOR gate 8 and OR gate 9,3d flip-flop 5, which preserves, to be referred to
Order 2 previous moment states of input simultaneously output it to the second XOR gate 8；
3rd step, the first XOR gate 7 are compared to the previous moment state of instruction input 1 and current time state, and will
As a result the clear terminal to 3d flip-flop 5 and four d flip-flop 6 is exported；
Second XOR gate 8 is compared to the previous moment state of instruction input 2 and current time state, and result is exported
To the first d type flip flop 3 and the clear terminal of the second d type flip flop 4；
4th step, if be not cleared, the first d type flip flop 3 is by current time state output to OR gate 9；It is if clear
Zero, OR gate 9 is given in the first d type flip flop 3 output 0；
If be not cleared, four d flip-flop 6 is by current time state output to OR gate 9；If be cleared, the 4th D
OR gate 9 is given in the output of trigger 60；
5th step, output of the OR gate 9 to the first d type flip flop 3 for receiving and four d flip-flop 6 carry out logic or, by results
As final output.
The beneficial effects of the invention are as follows：
The present invention can be such that the instruction transmission in forward and backward cabin is not limited by other side's command status；After the application of the present invention logic
Control principle more meet people use cognition custom.
Brief description of the drawings
Fig. 1 is that two-seat cabin instructs integrated logic figure in parallel；
Fig. 2 be two-seat cabin instruction sequencing after arrive effective logic chart；
Fig. 3 be sequential after arrive effective logical circuitry.
Embodiment
The present invention is described in further detail below in conjunction with the accompanying drawings：
To instructing effective two-seat cabin instruction synthetic circuit after one kind, and though instruction input 1 and instruction input 2 input be
Connect or open command, two-seat cabin instruction synthetic circuit decision instruction input the time of 1 and the transmission of instruction input 2, and with most
The instruction newly sent is as the instruction output after synthesis.
It is different that the circuit includes the first d type flip flop 3, the second d type flip flop 4,3d flip-flop 5, four d flip-flop 6, first
OR gate 7, the second XOR gate 8 and OR gate 9；Wherein,
The input termination instruction input 1 of first d type flip flop 3, output the second d type flip flop 4 of termination of the first d type flip flop 3
The first input end of input, the first input end of the first XOR gate 7 and OR gate 9, the clearing termination the of the first d type flip flop 3
The output end of two XOR gates 8；Second input of output the first XOR gate 7 of termination of the second d type flip flop 4, the second d type flip flop 4
Clearing termination the second XOR gate 8 output end；
The input termination instruction input 2 of four d flip-flop 6, the output termination 3d flip-flop 5 of four d flip-flop 6
Second input of input, the first input end of the second XOR gate 8 and OR gate 9, the clearing termination the of four d flip-flop 6
The output end of one XOR gate 7；Second input of output the second XOR gate 8 of termination of 3d flip-flop 5,3d flip-flop 5
Clearing termination the first XOR gate 7 output end；
The output end output output order 10 of OR gate 9.
The state change of the circuit only decision instruction input, appoints instruction input 1 and the side's instruction input of instruction input 2 one to have change
During change, the output of its shift register can make its XOR gate export 1, so as to shield the instruction input of other side, make logic circuit
Output only follow oneself current value to export.
The present invention is described in further detail with one embodiment below, this method comprises the following steps：
The first step, it is 4 groups of the 0 to the first d type flip flop 3 and the second d type flip flop that instruction input 1, which inputs original state to disconnect i.e. value,
Into two bit shift registers in, instruction input 2 input original state disconnect i.e. value for 0 to 3d flip-flop 5 and the 4th
In two bit shift registers that d type flip flop 6 forms；
Second step, the state of instruction input 1 is turned on by the disconnect, and in two bit shift registers, the first d type flip flop 3 will refer to
It is that value is exported to the second d type flip flop 4 for 0 that order 1 previous moment state of input, which disconnects, preserves instruction input 1 current time state and connects
Logical i.e. value is 1 and outputs it to the first XOR gate 7, and the second d type flip flop 4, which preserves the previous moment state of instruction input 1 and disconnected, is
It is worth 0 and to output it to the first XOR gate 7；
The state of instruction input 2 remains open, in two bit shift registers, four d flip-flop 6 by instruction input 2 it is previous when
Quarter state to disconnect be that value is 0 to export to 3d flip-flop 5, preserve instruction input 2 current time state disconnect i.e. value for 0 and by
It is exported to the second XOR gate 8 and OR gate 9, and 3d flip-flop 5, which preserves the previous moment state of instruction input 2 and disconnected, to be worth for 0 simultaneously
Output it to the second XOR gate 8；
3rd step, it is that value is that 0 and current time state connect that the first XOR gate 7 disconnects to the previous moment state of instruction input 1
Logical i.e. value is compared for 1, and result 1 is exported to the clear terminal to 3d flip-flop 5 and four d flip-flop 6；
It is that value is 0 and current time state disconnection is that value is that second XOR gate 8 disconnects to the previous moment state of instruction input 2
0 is compared, and result 0 is exported to the clear terminal to the first d type flip flop 3 and the second d type flip flop 4；
4th step, the first d type flip flop 3 are not cleared, and current time state ON is worth defeated for 1 by the first d type flip flop 3
Go out to OR gate 9；
Four d flip-flop 6 is cleared, and OR gate 9 is given in the output of four d flip-flop 60；
5th step, OR gate 9 carry out logic to the output valve 1 of the first d type flip flop 3 and the output valve 0 of four d flip-flop 6 that receive
Or, using result 1 as final output.
Understood through above-mentioned analysis：To the state change of effective logic circuit only decision instruction input after sequential, either one refers to
When making the input change, the output of its shift register can make its XOR gate export 1, so as to shield the instruction input of other side,
The output of logic circuit is set only to follow oneself current value to export.
Claims (2)
1. to the effective two-seat cabin instruction synthetic circuit of instruction after one kind, it is characterized in that, the circuit judges instruction input 1 and instruction
The time that input 2 is sent, and the instruction output after synthesis is used as using the newest instruction sent；
The circuit includes the first d type flip flop (3), the second d type flip flop (4), 3d flip-flop (5), four d flip-flop (6), the
One XOR gate (7), the second XOR gate (8) and OR gate (9)；Wherein,
The input termination instruction input 1 of first d type flip flop (3), the output of the first d type flip flop (3) terminate the second d type flip flop (4)
Input, the first input end of the first XOR gate (7) and the first input end of OR gate (9), the first d type flip flop (3) it is clear
The output end of zero the second XOR gate of termination (8)；The output of second d type flip flop (4) terminates the second input of the first XOR gate (7)
End, the clearing of the second d type flip flop (4) terminate the output end of the second XOR gate (8)；
The input termination instruction input 2 of four d flip-flop (6), the output termination 3d flip-flop (5) of four d flip-flop (6)
Input, the first input end of the second XOR gate (8) and the second input of OR gate (9), four d flip-flop (6) it is clear
The output end of zero the first XOR gate of termination (7)；The output of 3d flip-flop (5) terminates the second input of the second XOR gate (8)
End, the clearing of 3d flip-flop (5) terminate the output end of the first XOR gate (7)；
The output end output output order (10) of OR gate (9).
2. a kind of two-seat cabin instruction integrated approach based on sequential logic, it is characterized in that, this method comprises the following steps：
The first step, instruction input 1 is input to the first d type flip flop (3) and first liang of bit shift of the second d type flip flop (4) composition is posted
In storage, instruction input 2 is input to second liang of bit shift register of 3d flip-flop (5) and four d flip-flop (6) composition
In；
Second step, in first liang of bit shift register, the first d type flip flop (3) is by the previous moment state output of instruction input 1 to the
2-D trigger (4), preserve instruction input 1 current time state and output it to the first XOR gate (7), the second d type flip flop
(4) preserve the previous moment state of instruction input 1 and output it to the first XOR gate (7)；
In second liang of bit shift register, four d flip-flop (6) triggers the previous moment state output of instruction input 2 to the 3rd D
Device (5), preserve instruction input 2 current time state and output it to the second XOR gate (8) and OR gate (9), 3d flip-flop
(5) preserve the previous moment state of instruction input 2 and output it to the second XOR gate (8)；
3rd step, the first XOR gate (7) are compared to the previous moment state of instruction input 1 and current time state, and will knot
Fruit exports the clear terminal to 3d flip-flop (5) and four d flip-flop (6)；
Second XOR gate (8) is compared to the previous moment state of instruction input 2 and current time state, and by result export to
The clear terminal of first d type flip flop (3) and the second d type flip flop (4)；
4th step, if be not cleared, the first d type flip flop (3) gives current time state output to OR gate (9)；It is if clear
Zero, OR gate (9) is given in the first d type flip flop (3) output 0；
If be not cleared, four d flip-flop (6) gives current time state output to OR gate (9)；If be cleared, the 4th D
OR gate (9) is given in trigger (6) output 0；
5th step, the output of first d type flip flop (3) and four d flip-flop (6) of the OR gate (9) to receiving carry out logic or, will knots
Fruit is as final output.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1307748A (en) * | 1998-05-29 | 2001-08-08 | 埃德加·丹尼·奥尔森 | Multiple-valued logic circuit arthitecture: supplementary symmetrical logic circuit structure (SUS-LOG) |
| CN1950811A (en) * | 2004-05-13 | 2007-04-18 | 松下电器产业株式会社 | An information processing apparatus, an integrated circuit, a data transfer controlling method, a data transfer controlling program, a program storage medium, a program transmission medium and a data |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6977528B2 (en) * | 2002-09-03 | 2005-12-20 | The Regents Of The University Of California | Event driven dynamic logic for reducing power consumption |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1307748A (en) * | 1998-05-29 | 2001-08-08 | 埃德加·丹尼·奥尔森 | Multiple-valued logic circuit arthitecture: supplementary symmetrical logic circuit structure (SUS-LOG) |
| CN1950811A (en) * | 2004-05-13 | 2007-04-18 | 松下电器产业株式会社 | An information processing apparatus, an integrated circuit, a data transfer controlling method, a data transfer controlling program, a program storage medium, a program transmission medium and a data |
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