CN103973241B - It is dynamically adapted the power amplification circuit of gain - Google Patents
It is dynamically adapted the power amplification circuit of gain Download PDFInfo
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- CN103973241B CN103973241B CN201410132411.6A CN201410132411A CN103973241B CN 103973241 B CN103973241 B CN 103973241B CN 201410132411 A CN201410132411 A CN 201410132411A CN 103973241 B CN103973241 B CN 103973241B
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Abstract
The present invention provides a kind of power amplification circuit being dynamically adapted gain, including a power supply unit, an input power detector unit and a power amplification unit；Power supply unit is in order to provide a power supply signal；Input power detector unit receives a differential input signals and power supply signal, and the power of detection differential input signals, to produce a detection signal, utilizes detection signal to increase or downgrade a bias voltage signal；Power amplification unit receives differential input signals and bias voltage signal, adjusts gain according to bias voltage signal, and the gain after recycling adjusts exports a differential output signal to amplify differential input signals；Then, according to the power of detection differential input signals dynamically to adjust the gain of power amplification circuit, cause to export a differential output signal according with actual power.
Description
Technical field
The present invention is related to a kind of power amplification circuit, a kind of power amplification electricity being dynamically adapted gain
Road.
Background technology
Power amplification circuit is widely used in field of wireless communication.Many wireless telecommunication systems are in transmission
Before signal, it will usually use power amplification circuit to be amplified for signal, so that signal can be amplified to
One rational power or amplitude.
Refer to Fig. 1, for the circuit diagram of known power amplification circuit.As it can be seen, power amplification is electric
Road 100 includes power amplification unit 11, power detecting unit 13 and a bias control unit 15.
The input of power amplification unit 11 couples input signal f via one first electric capacity 121in.Power is examined
Surveying unit 13 and include a N-type transistor 131, the gate terminal of transistor 131 couples via one second electric capacity 122
Input signal fin.First electric capacity 121 and the second electric capacity 122 are in order to completely cut off input signal finUnidirectional current splenium
Point, so that power amplification unit 11 and power detecting unit 13 would only receive the input of an alternating voltage part
Signal fin.Bias control unit 15 include one be made up of two P-type transistor 151,152 current mirror,
One N-type transistor 153 connecting into diode and an inducer 154.
The gate terminal of power detecting unit 13 receives input signal fin, detect input signal finPower with leakage
The extreme current signal producing a half-wave type.Then, the electric current being made up of two P-type transistor 151,152
Current signal can be coupled to N-type transistor 153 by mirror.Inducer 154 biases to produce one according to current signal
The input of 111 to power amplification circuit 11.When input signal finPower the biggest time, bias 111 draws relatively
Rise, so that power amplification circuit 11 flows through more electric current IOUTAnd increase gain.Otherwise, when input letter
Number finPower more hour, bias 111 draws fall, relatively so that power amplification unit 11 flows through less electricity
Stream IOUTAnd reduce gain.So, via detection input signal finWatt level put dynamically adjusting power
The gain of big circuit 100.
Or, refer to Fig. 2, for the circuit diagram of known another power amplification circuit.As it can be seen,
Power amplification circuit 200 includes power amplification unit 21 and a peakvalue's checking feedback unit 23.
Power amplification unit 21 includes a load resistance 211 and two transistor 213,215.Load resistance 211
It is connected to voltage source VDDAnd between the outfan 203 of power amplification circuit 200.Two transistor 213,215 connects
Becoming the framework that splices, wherein the input 201 of the gate terminal connection power amplification circuit 200 of transistor 215 receives
One input signal (in), two transistor 213,215 amplifies input signal and produces with the drain electrode end at transistor 213
One output signal (OUT).
Peakvalue's checking feedback unit 23 include one first peak detector 231,1 second peak detector 233,
One attenuator 235 and a differential amplifier 237.Input signal is sent to the first peak detector 231 with detection
The power of input signal and produce one first detection signal, the first detection signal is sent to differential amplifier 237
Positive terminal.Output signal is sent to attenuator 235 with according to a proportionality coefficient decaying output signal, such as:
Power amplification unit 21 has the gain of A times, and attenuator 235 is by the increasing for attenuated output signal 1/A times
Benefit.Output signal after decay is sent to the second peak detector 233 with the output signal after detection decay
Power and produce one second detection signal, the second detection signal is sent to the negative pole end of differential amplifier 237.
Differential amplifier 237 compares the difference between the first detection signal and the second detection signal to export a bias
210, bias 210 will be sent to the gate terminal of transistor 215 to determine the gain of power amplification unit 21.If
The power of input signal, more than the power of the output signal after decay, will be indicative the mesh of power amplification unit 21
Front ratio of gains demand gain is also little, and differential amplifier 237 will produce higher bias 210 a to transistor
The gate terminal of 215, so that power amplification unit 21 flows through more electric current IOUTAnd increase gain.Contrary,
If the power of input signal is less than the power of the output signal after decay, will be indicative power amplification unit 21
Current ratio of gains demand gain also want big, differential amplifier 237 will produce relatively low bias 210 a to crystal
The gate terminal of pipe 215, so that power amplification unit 21 flows through less electric current IOUTAnd reduce gain.So,
Via the power difference between comparator input signal and output signal dynamically to adjust the increasing of power amplification circuit 200
Benefit.
Then, being different from conventional power amplifying circuit 100,200, the present invention proposes an innovative circuits framework
Power amplification circuit, is possible not only to dynamically adjust gain, and can maintain preferably gain linearity degree, it will
It it is the purpose to be reached of the present invention.
Summary of the invention
One purpose of the present invention, is to provide a kind of power amplification circuit being dynamically adapted gain, its circuit
A differential input signals can be received, via detection differential input signals power dynamically to adjust gain, cause
Make to produce a differential output signal according with actual power, so, be possible not only to reduce power amplification electricity
The electrical source consumption on road, and maintain preferably gain linearity degree.
One purpose of the present invention, is to provide a kind of power amplification circuit being dynamically adapted gain, is with one
Translinear loop, as the major design framework of power amplification circuit, can avoid the inclined of power amplification circuit
Pressure produces non-linear change, improves the stability on Gain tuning.
One purpose of the present invention, is to provide a kind of power amplification circuit being dynamically adapted gain, its circuit
Before gain does not adjusts, inside delay transmission differential input signals to circuit, use and avoid circuit use not adjust
Differential input signals is amplified in the gain haveing suffered.
One purpose of the present invention, is to provide a kind of power amplification circuit being dynamically adapted gain, and it utilizes
The bias of two different time points produced detection signal adjustment circuit, enough by making circuit to flow through
Export electric current and make the gain of circuit maintain higher state.
One purpose of the present invention, is to provide a kind of power amplification circuit being dynamically adapted gain, its circuit
The detection signal and that arrived in advance by one of bias delay and the detection signal that arrives adjusts together, can expand
The operating time that big circuit amplifies for differential input signals.
In order to achieve the above object, the present invention provides a kind of power amplification circuit being dynamically adapted gain, bag
Include: a power supply unit, it is provided that a power supply signal；One input power detector unit, first differential including a pair
Transistor, the first end of the first differential transistor connects a supply voltage, and the second end flows through one first electric current,
Control end receive a differential input signals via one first electric capacity respectively and connect power supply unit, wherein input work
The power of rate detector unit detection differential input signals produces one the with the second end at the first differential transistor
One detection signal, utilizes the first detection signal to increase or downgrade a bias voltage signal；And a power amplification unit,
Including a pair second differential transistors, the first end of the second differential transistor connects supply voltage and has one
Differential output signal, the second end ground connection, control end and receive differential input signals via one second electric capacity respectively,
Wherein bias voltage signal is sent to the control end of the second differential transistor, utilizes bias voltage signal to adjust power amplification list
The gain of unit.
In one embodiment of the invention, wherein this is also associated with an electric capacity list to the second end of the first differential transistor
Unit.
In one embodiment of the invention, wherein this is negative via one first respectively to the control end of the first differential transistor
Carrying element and connect power supply unit, the first load elements is a resistance or an inductance.
In one embodiment of the invention, wherein power supply unit includes at least two and connects into the power supply that diode is formed
Transistor, two power supply strings of transistors are connected into one and splice framework, first end for electric transistor of the top and the
Two ends connect this control end to the first differential transistor via the first load elements.
In one embodiment of the invention, wherein power supply unit includes one for electric transistor, for the of electric transistor
One end connects this control end to the first differential transistor, the second end ground connection via the first load elements, controls
End connects this to the second end of the first differential transistor and via a load unit ground connection.
In one embodiment of the invention, wherein this is negative via one second respectively to the control end of the second differential transistor
Carrying element and connect this second end to the first differential transistor, the second load elements is a resistance or an inductance.
In one embodiment of the invention, wherein this is negative via one the 3rd respectively to the first end of the second differential transistor
Carrying element and connect supply voltage, the 3rd load elements is a resistance or an inductance.
In one embodiment of the invention, also including one first delay amplifier, power amplification unit prolongs via first
Amplifier receives differential input signals late, and wherein the first delay amplifier is set with a signal delay time, letter
Number time delay performs the running required for a power detection program more than or equal to input power detector unit
Time, when differential input signals is separately input into input power detector unit and the first delay amplifier, the
One delay amplifier is transmitting differential input after the signal delay time set by the first delay amplifier
Signal is to power amplification unit.
In one embodiment of the invention, also include one first delay amplifier and one second delay amplifier, power
Amplifying unit receives differential input signals via the first delay amplifier, and input power detector unit is via second
Delay amplifier receives differential input signals, and wherein the first delay amplifier is set with a signal delay time,
Second delay amplifier is set with another signal delay time, the time delay set by the first delay amplifier
Hold plus input power detector unit more than or equal to the signal delay time set by the second delay amplifier
The running time required for row one power detection program, put when differential input signals is separately input into the first delay
When big device and the second delay amplifier, the second delay amplifier is through the letter set by the second delay amplifier
Transmit differential input signals after number time delay to input power detector unit, and the first delay amplifier is at warp
Differential input signals is transmitted to power amplification list after spending the signal delay time set by the first delay amplifier
Unit.
In one embodiment of the invention, also including an output detector unit, output detector unit includes
A pair the 3rd differential transistors, this connects supply voltage, the second end stream to the first end of the 3rd differential transistor
Cross one second electric current and connect this to the second end of the first differential transistor, control end respectively via one the 3rd electricity
Hold and connect this first end to the second differential transistor, wherein output detector unit detection differential output letter
Number power with the 3rd differential transistor second end produce one second detection signal, utilize first detection letter
Number and second detection signal increase together or downgrade bias voltage signal.
In one embodiment of the invention, wherein this is negative via one the 4th respectively to the control end of the 3rd differential transistor
Carrying element to connect altogether, the 4th load elements is a resistance or an inductance.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of known power amplification circuit；
Fig. 2 is the circuit diagram of known another power amplification circuit；
Fig. 3 is the circuit signal that the present invention is dynamically adapted power amplification circuit one preferred embodiment of gain
Figure；
Fig. 4 is the circuit diagram that the present invention is dynamically adapted the another embodiment of power amplification circuit of gain；
Fig. 5 is the circuit diagram that the present invention is dynamically adapted the another embodiment of power amplification circuit of gain；
Fig. 6 is the circuit diagram that the present invention is dynamically adapted the another embodiment of power amplification circuit of gain；
Fig. 7 is the circuit diagram that the present invention is dynamically adapted the another embodiment of power amplification circuit of gain.
Fig. 8 is that the present invention first detects signal and the oscillogram of the second detection signal.
Wherein, reference:
100 power amplification circuit 11 power amplification units
111 bias 121 first electric capacity
122 second electric capacity 13 power detecting unit
131 transistor 15 bias control units
151 transistor 152 transistors
153 transistor 154 inducers
200 power amplification circuit 201 inputs
203 outfan 21 power amplification units
210 bias 211 load resistances
213 transistor 215 transistors
23 peakvalue's checking feedback unit 231 first peak detectors
233 second peak detector 235 attenuators
237 differential amplifier 300 power amplification circuits
301 power amplification circuit 302 power amplification circuits
303 power amplification circuit 304 power amplification circuits
31 power supply units 311 are for electric transistor
312 for electric transistor 32 power supply unit
321 for electric transistor 33 input power detector unit
331 first differential transistor 333 first electric capacity
334 first load elements 335 capacitor cells
336 load unit 35 power amplification units
351 second differential transistor 353 second electric capacity
354 second load elements 355 the 3rd load elements
36 first delay amplifier 37 second delay amplifiers
38 output detector unit 381 the 3rd differential transistors
383 the 3rd electric capacity 384 the 4th load elements
Detailed description of the invention
Refer to Fig. 3, be dynamically adapted the electricity of power amplification circuit one preferred embodiment of gain for the present invention
Road schematic diagram.As it can be seen, power amplification circuit 300 of the present invention is a rf power amplifier circuit, its bag
Include power supply unit 31, input power detector unit 33 and a power amplification unit 35.
Power supply unit 31 includes at least two and connects into the confession electric transistor 311,312 that diode is formed.Two supply
Electric transistor 311,312 is concatenated into one and splices framework, it is provided that a stable power supply signal SP。
Input power detector unit 33 is ripple envelope detector unit (Envelope Dectector), and it includes one
To the first differential transistor 331.First end of the first differential transistor 331 connects a supply voltage VDD, the
Two ends flow through one first electric current I1, control end and receive a differential input letter via one first electric capacity 333 respectively
Number RF_inn, RF_inp and connect power supply unit 31 to receive power supply signal SP。
Power amplification unit 35 includes a pair second differential transistors 351.The first of second differential transistor 351
End connects supply voltage VDD, the second end ground connection, control end and receive differential via one second electric capacity 353 respectively
Input signal RF_inn, RF_inp.Furthermore, the first electric capacity 333 and the second electric capacity 353 are differential defeated in order to completely cut off
Enter the direct current part of signal RF_inn, RF_inp, so that input power detector unit 33 and power amplification
Unit 35 would only receive differential input signals RF_inn, RF_inp of alternating voltage part.
In one embodiment of the invention, the control end of the first differential transistor 331 is respectively via one first load cell
Part 334 connects first end for electric transistor 311 of power supply unit 31 and controls end, the second differential transistor
The end that controls of 351 connects the second end of the first differential transistor 331 respectively via one second load elements 354,
And the first end of the second differential transistor 351 connects supply voltage via one the 3rd load elements 355 respectively
VDD.In an embodiment of the present invention, transistor 311,312,331,351 can be metal semitransistor
(MOS), CMOS (CMOS), field-effect transistor (FET) or double carrier transistor (BJT).
In an embodiment of the present invention, the first end of transistor 311,312,331,351 is drain electrode end or collector terminal,
Second end is source terminal or emitter-base bandgap grading end, and controlling end is gate terminal or base terminal.
Input power detector unit 33 in order to detect differential input signals RF_inn, RF_inp power (or claim
For amplitude), reflect one first detection signal S with the second end at the first differential transistor 331D1.Furthermore,
Second load elements 354 of power amplification unit 35 has a bias voltage signal SB, utilize the first detection
Signal SD1Increase or downgrade bias voltage signal SB。
If the power of differential input signals RF_inn, RF_inp is higher, the first detection signal SD1Increase partially
Pressure signal SB, bias voltage signal S after increasingBIncrease ordering about power amplification unit 35 to flow through more electric current
Gain.If the power of differential input signals RF_inn, RF_inp is relatively low, the first detection signal SD1Downgrade
Bias voltage signal SB, bias voltage signal S after downgradingBPower amplification unit 35 will be ordered about flow through less electric current and drop
Low gain.Then, differential input signals is amplified in the i.e. available gain being dynamically adjusted of power amplification unit 35
RF_inn, RF_inp, to export differential output signal RF_outn, the RF_outp according with actual power,
And can therefore reduce the electrical source consumption of power amplification circuit 300.
Also, the transistor 311 of power supply unit 31 of the present invention, 312, the transistor of input power detector unit 33
331 and the transistor 351 of power amplification unit 35 can consist of a translinear loop (translinear
loop).Then, the first electric current I that input power detector unit 33 and power amplification unit 35 are flow through1And output
Electric current IOUTThe input current I that power supply unit 31 is flow through will be followedinProduce relative steady change, such as:
Iin 2=I1×IOUT.So, the factor that can avoid process variations is caused bias voltage signal SBProduce non-linear
Change, and improve the stability on power amplification unit 35 Gain tuning.
In one embodiment of the invention, the second end of the first differential transistor 331 is also connected with a capacitor cell 335.
Capacitor cell 335 is set up among translinear loop, so that bias voltage signal SB boosts, and
Make power amplification unit 35 can flow through more output electric current I all the timeOUTAnd improve power amplification unit 35
Gain.
Refer to Fig. 4, be dynamically adapted the circuit of the another embodiment of power amplification circuit of gain for the present invention
Schematic diagram.As it can be seen, the power supply unit 32 of the present embodiment power amplification circuit 301 can also only use list
One provides power supply signal S for electric transistor 321P。
The first end for electric transistor 321 connects the first differential transistor 331 via the first load elements 334
Control end, the second end ground connection, and control end and connect the second end of the first differential transistor 331 and via one
Load unit 336 ground connection.
In the present embodiment, the transistor 321 of power supply unit 32, the transistor of input power detector unit 33
331 and the transistor 351 of power amplification unit 35 equally consist of a translinear loop, cause to produce
Raw stable bias voltage signal SB adjusts the gain of power amplification unit 35.
Refer to Fig. 5, be dynamically adapted the circuit of the another embodiment of power amplification circuit of gain for the present invention
Schematic diagram.As it can be seen, the present embodiment power amplification circuit 302 also includes one first delay amplifier 36.
First delay amplifier 36 is sent to power amplification unit in order to postpone differential input signals RF_inn, RF_inp
35。
In the present embodiment, the first delay amplifier 36 be set with one signal delay time TX.This signal delay
Time TXDuring the running performing required for a power detection program more than or equal to input power detector unit 33
Between TD, such as TX≧TD。
Circuit 302 comes into operation, and differential input signals RF_inn, RF_inp are respectively sent to the first delay and put
Big device 36 and input power detector unit 33.First delay amplifier 36 postpones output differential input signals
RF_inn, RF_inp, input power detector unit 33 detects the merit of differential input signals RF_inn, RF_inp
Rate is to obtain the first detection signal SD1.Afterwards, the first detection signal SD1It is sent to power amplification unit 35,
To increase or to downgrade bias voltage signal SBAnd adjust the gain of power amplification unit 35.
When circuit 302 operates to time TXTime, the first delay amplifier 36 export differential input signals RF_inn,
RF_inp is to power amplification unit 35.Power amplification unit 35 uses the gain after adjusting to amplify differential input letter
Number RF_inn, RF_inp.
In this, before the gain of power amplification unit 35 does not adjusts, the first delay amplifier 36 is utilized to postpone
Differential input signals RF_inn, RF_inp are to power amplification unit 35, to avoid power amplification unit 35 in transmission
The most adjusted gain is used to amplify differential input signals RF_inn, RF_inp.
Refer to Fig. 6, be dynamically adapted the circuit of the another embodiment of power amplification circuit of gain for the present invention
Schematic diagram.As it can be seen, the present embodiment power amplification circuit 303 also includes one second delay amplifier 37.
Second delay amplifier 37 is sent to input power detection in order to postpone differential input signals RF_inn, RF_inp
Unit 33.
In the present embodiment, the first delay amplifier 36 be set with one signal delay time TX, second postpones to amplify
Device 37 is set with another signal delay time of TY.Signal delay time set by first delay amplifier 36
TXMore than or equal to T signal delay time set by the first delay amplifier 36YDetect plus input power
Unit 33 performs the running time T required for power detection programD, such as TX≧TY+TD。
Circuit 303 comes into operation, and differential input signals RF_inn, RF_inp are respectively sent to the first delay and put
Big device 36 and the second delay amplifier 37, the first delay amplifier 36 and the second delay amplifier 37 postpone output
Differential input signals RF_inn, RF_inp.When circuit 303 operates to time TY, the second delay amplifier
37 output differential input signals RF_inn, RF_inp are to input power detector unit 33.
After continuing through a power detection running time TD, input power detector unit 33 has detected differential defeated
Enter the power of signal RF_inn, RF_inp to obtain the first detection signal SD1.Afterwards, the first detection signal
SD1It is sent to power amplification unit 35, to increase or to downgrade bias voltage signal SBAnd adjust power amplification unit 35
Gain.
Continue, when circuit 303 operates to time TXTime, the first delay amplifier 36 exports differential input signals
RF_inn, RF_inp are to power amplification unit 35.It is poor that power amplification unit 35 uses the gain after adjusting to amplify
Dynamic input signal RF_inn, RF_inp.
Here, by the first delay amplifier 36 and setting of the second delay amplifier 37, merit not only can be avoided
Rate amplifying unit 35 uses the most adjusted gain to amplify differential input signals RF_inn, RF_inp, and guarantees
First input signal RF_inn of differential input signals and the second input signal RF_inp can synchronize to input to
Among input power detector unit 33 or power amplification unit 35, during to avoid circuit to operate, produce mistake.
In one embodiment of the invention, power amplification circuit 302/303 can provide with Selection utilization power supply unit 31
Power supply signal VS, or Selection utilization power supply unit 32 provides power supply signal VS。
Refer to Fig. 7, be dynamically adapted the circuit of the another embodiment of power amplification circuit of gain for the present invention
Schematic diagram.As it can be seen, the present embodiment power amplification circuit 304 also includes an output detector unit 38.
Output detector unit 38 includes a pair the 3rd differential transistors 381.The first of 3rd differential transistor 381
End connects supply voltage VDD, the second end flows through one second electric current I2 and connects the of the first differential transistor 331
Two ends, control the first end that end connects the second differential transistor 351 of correspondence respectively via one the 3rd electric capacity 383
To receive differential output signal RF_oupn, RF_oupt.Output detector unit 38 is differential in order to detect
Output signal RF_outn, the power of RF_outp, reflect with the second end at the 3rd differential transistor 381
One second detection signal SD2。
Additionally, the control end of two the 3rd differential transistors 381 can be respectively via one the 4th load elements 384
Connect.In various embodiments of the present invention, first load elements the 334, second load elements the 354, the 3rd is negative
Carry element 355 or the 4th load elements 384 can be a resistance or an inductance.
Continuing, coordinate refering to Fig. 8, circuit 304 comes into operation, differential input signals RF_inn, RF_inp
It is respectively sent to the first delay amplifier 36 and the second delay amplifier 37.When circuit 304 operates to time TY
Time, input power detector unit 33 receives the differential input signals that the second delay amplifier 37 is exported
RF_inn、RF_inp。
When circuit 304 operates to time T0, input power detector unit 33 detects differential input signals
The power of RF_inn, RF_inp is to produce the first detection signal SD1.Afterwards, the first detection signal SD1Transmit
To power amplification unit 35, to increase or to downgrade bias voltage signal SBAnd adjust the gain of power amplification unit 35.
When circuit 304 operates to time TX, the first delay amplifier 36 exports differential input signals
RF_inn, RF_inp are to power amplification unit 35.Afterwards, power amplification unit 35 uses the first detection signal
SD1Differential input signals RF_inn, RF_inp are amplified in the gain adjusted.
When circuit 304 operates to time T1, output detector unit 38 detects differential output signal
The power of RF_outn, RF_outp is to produce the second detection signal SD2.Afterwards, the first detection signal SD1And
Second detection signal SD2It is sent to power amplification unit 35 together, to increase further or to downgrade bias voltage signal
SBAnd adjust the gain of power amplification unit 35.The running of circuit 304 is persistently carried out by upper type, until complete
Till differential input signals RF_inn, the RF_inp in portion is amplified to output.
As it has been described above, utilize two different time points produced detection signal SD1、SD2Adjust power amplification list
The bias of unit 35, can flow through enough output electric current I by making power amplification unit 35OUTAnd make gain tie up
Hold in higher state.Additionally, the first detection signal S that the bias of power amplification unit 35 is shifted to an earlier date and arrivesD1
The the second detection signal S adjusting and being delayed and arriveD2Adjust together, power amplification unit 35 can be expanded
The operating time that differential input signals RF_inn, RF_inp are amplified.If differential input signals RF_inn,
RF_inp shift to an earlier date because of the factor of process shifts or delay input to power amplification unit 35, its signal
The input time of RF_inn, RF_inp still can fall among the operating time that power amplification unit 35 is expanded,
And make power amplification unit 35 can smoothly in advance or delay input differential input signals RF_inn,
The action that RF_inp is amplified.
As described above, an only preferred embodiment of the present invention, not it is used for limiting the present invention and implements
Scope, the most all according to the shape described in scope of the present invention patent, structure, feature and spirit do equal
Deng change and modification, all should be included in the claim of the present invention.
Claims (11)
1. the power amplification circuit being dynamically adapted gain, it is characterised in that including:
One power supply unit a, it is provided that power supply signal；
One input power detector unit, including a pair first differential transistors, the first of the first differential transistor
End connects a supply voltage, and the second end flows through one first electric current, controls end and receives via one first electric capacity respectively
One differential input signals and connection power supply unit, wherein input power detector unit detects differential input signals
Power produces one first detection signal with the second end at the first differential transistor, utilizes the first detection signal to adjust
Rise or downgrade a bias voltage signal；And
One power amplification unit, including a pair second differential transistors, the first end of the second differential transistor is even
Connect supply voltage and have a differential output signal, the second end ground connection, control end respectively via one second electricity
Holding and receive differential input signals, wherein bias voltage signal is sent to the control end of the second differential transistor, utilizes partially
Pressure signal adjusts the gain of power amplification unit.
2. power amplification circuit as claimed in claim 1, it is characterised in that wherein this is differential to first
Second end of transistor is also associated with a capacitor cell.
3. power amplification circuit as claimed in claim 1, it is characterised in that wherein this is differential to first
The control end of transistor connects this power supply unit via one first load elements respectively, and this first load elements is
One resistance or an inductance.
4. power amplification circuit as claimed in claim 3, it is characterised in that wherein this power supply unit bag
Include at least two connect into that diode formed for electric transistors, this at least two connects into the confession that diode is formed
Electric transistor is concatenated into one and splices framework, this of the top for first end of electric transistor and the second end via this
First load elements connects this control end to the first differential transistor.
5. power amplification circuit as claimed in claim 3, it is characterised in that wherein this power supply unit bag
Having included one and supplied electric transistor, the first end of this confession electric transistor connects this to first via this first load elements
The control end of differential transistor, the second end ground connection, control end and connect this second end to the first differential transistor
And via a load unit ground connection.
6. power amplification circuit as claimed in claim 1, it is characterised in that wherein this is differential to second
The end that controls of transistor connects this second end to the first differential transistor via one second load elements respectively,
This second load elements is a resistance or an inductance.
7. power amplification circuit as claimed in claim 1, it is characterised in that wherein this is differential to second
First end of transistor connects this supply voltage via one the 3rd load elements respectively, and the 3rd load elements is
One resistance or an inductance.
8. power amplification circuit as claimed in claim 1, it is characterised in that also include that one first postpones
Amplifier, this power amplification unit receives this differential input signals via this first delay amplifier, wherein should
First delay amplifier is set with a signal delay time, and this signal delay time is more than or equal to this input work
Rate detector unit performs the running time required for a power detection program, when this differential input signals is the most defeated
When entering to this input power detector unit and this first delay amplifier, this first delay amplifier is through being somebody's turn to do
This differential input signals is transmitted to this power amplification after signal delay time set by first delay amplifier
Unit.
9. power amplification circuit as claimed in claim 1, it is characterised in that also include that one first postpones
Amplifier and one second delay amplifier, this power amplification unit receives this difference via this first delay amplifier
Dynamic input signal, this input power detector unit receives this differential input letter via this second delay amplifier
Number, wherein this first delay amplifier is set with a signal delay time, and this second delay amplifier is set with
Another signal delay time, this signal delay time set by the first delay amplifier more than or equal to this
Signal delay time set by two delay amplifiers performs a power inspection plus this input power detector unit
The running time required for ranging sequence, when this differential input signals be separately input into this first delay amplifier and
During this second delay amplifier, this second delay amplifier is through the letter set by this second delay amplifier
Transmit this differential input signals after number time delay to this input power detector unit, and this first postpones to amplify
Device is transmitting this differential input signals extremely after the signal delay time set by this first delay amplifier
This power amplification unit.
10. power amplification circuit as claimed in claim 1, it is characterised in that also include an output
Detector unit, this output detector unit includes a pair the 3rd differential transistors, and this is to the 3rd differential crystal
First end of pipe connects this supply voltage, the second end flows through one second electric current and connects this to the first differential crystal
Second end of pipe, control end connect this first end to the second differential transistor via one the 3rd electric capacity respectively,
Wherein this output detector unit detects the power of this differential output signal with at the 3rd differential transistor
Second end produce one second detection signal, utilize this first detection signal and this second detection signal adjust together
Rise or downgrade this bias voltage signal.
11. power amplification circuits as claimed in claim 10, it is characterised in that wherein this is differential to the 3rd
The control end of transistor connects altogether via one the 4th load elements respectively, and the 4th load elements is an electricity
Resistance or an inductance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410132411.6A CN103973241B (en) | 2014-04-03 | 2014-04-03 | It is dynamically adapted the power amplification circuit of gain |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410132411.6A CN103973241B (en) | 2014-04-03 | 2014-04-03 | It is dynamically adapted the power amplification circuit of gain |
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| CN105048977A (en) * | 2015-07-30 | 2015-11-11 | 络达科技股份有限公司 | Amplifier having dynamic bias voltage |
| CN107124143B (en) * | 2017-03-30 | 2020-08-25 | 江苏理工学院 | Bidirectional high-voltage output linear amplifying circuit |
| CN112865729B (en) * | 2021-02-01 | 2023-02-28 | 展讯通信（上海）有限公司 | Amplifier circuit and electronic device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1436398A (en) * | 2000-08-31 | 2003-08-13 | 株式会社日立制作所 | Power amplifier module |
| CN101521490A (en) * | 2008-02-26 | 2009-09-02 | 瑞昱半导体股份有限公司 | Power amplifying circuit for providing bias voltage signal to input end and method thereof |
| CN101764580A (en) * | 2008-12-11 | 2010-06-30 | 三星电机株式会社 | Systems and methods for an adaptive bias circuit for a differential power amplifier |
| CN101986560A (en) * | 2009-07-28 | 2011-03-16 | 索尼公司 | Amplifying circuit, semiconductor integrated circuit, wireless transmission system, and communication apparatus |
| CN102064774A (en) * | 2009-11-18 | 2011-05-18 | 中兴通讯股份有限公司 | Implementation method of power amplifying circuit and power amplifying device |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1436398A (en) * | 2000-08-31 | 2003-08-13 | 株式会社日立制作所 | Power amplifier module |
| CN101521490A (en) * | 2008-02-26 | 2009-09-02 | 瑞昱半导体股份有限公司 | Power amplifying circuit for providing bias voltage signal to input end and method thereof |
| CN101764580A (en) * | 2008-12-11 | 2010-06-30 | 三星电机株式会社 | Systems and methods for an adaptive bias circuit for a differential power amplifier |
| CN101986560A (en) * | 2009-07-28 | 2011-03-16 | 索尼公司 | Amplifying circuit, semiconductor integrated circuit, wireless transmission system, and communication apparatus |
| CN102064774A (en) * | 2009-11-18 | 2011-05-18 | 中兴通讯股份有限公司 | Implementation method of power amplifying circuit and power amplifying device |
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