CN103944372A - IGBT driving protection circuit - Google Patents
IGBT driving protection circuit Download PDFInfo
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Abstract
The invention discloses an IGBT driving protection circuit which comprises an input terminal, an upper tube short pulse suppression circuit, an upper tube first-order circuit, an upper tube dead zone delay circuit, an upper tube clamping protection circuit, a lower tube short pulse suppression circuit, a lower tube first-order circuit, a lower tube dead zone delay circuit and a lower tube clamping protection circuit. The input terminal, the upper tube short pulse suppression circuit, the upper tube first-order circuit, the upper tube dead zone delay circuit and the upper tube clamping protection circuit are arranged between the input terminal and an output terminal, used for controlling an upper tube IGBT, and connected in sequence; the lower tube short pulse suppression circuit, the lower tube first-order circuit, the lower tube dead zone delay circuit and the lower tube dead zone delay circuit are used for controlling a lower tube IGBT and connected in sequence. By means of the IGBT driving protection circuit, a simple hardware circuit structure is adopted, short pulses are suppressed, upper tube dead zone delay control and lower tube dead zone delay control of the IGBTs are achieved, the diode clamping protection circuits are adopted for resisting interference, cost is low, and reliability is high.
Description
Technical field
The present invention relates to current transformer, especially a kind of IGBT Drive Protecting Circuit of current transformer internal power unit.
Background technology
In current transformer when work,, upper pipe IGBT and lower pipe IGBT on the inner same brachium pontis of its power cell can not be simultaneously open-minded when driving, and during upper and lower two pipe alternation switch, a pipe is opened with another pipe and turn-offed and must ensure in time certain dead band time delay.
The scheme that solves at present above-mentioned dead band latency issue has: 1, adopt special-purpose integrated drive, but this special-purpose integrated drive price is high, Lead Time is long, maintainability is poor; 2, adopt software control, but software control anti-interference is poor, software run fly or crash after IGBT fragile.
Summary of the invention
For solving the problems of the technologies described above, the object of this invention is to provide the IGBT Drive Protecting Circuit that a kind of price is lower, be convenient to maintenance, strong interference immunity.
The technical solution used in the present invention is:
An IGBT Drive Protecting Circuit, is characterized in that comprising:
One input terminal, this input terminal receives the two-way pwm signal of peripheral control unit output, and this two-way pwm signal is designated as PWM-A, PWM-B;
On one, manage short pulse suppression circuit, its input is connected with the PWM-A signal end of input terminal;
Manage short pulse suppression circuit once, its input is connected with the PWM-B signal end of input terminal;
On one, manage firstorder circuit, it is connected to pipe short pulse suppression circuit output end, for time constant t1 is provided;
Manage firstorder circuit once, it is connected to lower pipe short pulse suppression circuit output end, for time constant t2 is provided;
On one, manage dead band delay circuit, its input is connected to pipe short pulse suppression circuit output end;
Manage dead band delay circuit once, its input is connected to lower pipe short pulse suppression circuit output end;
On one, manage clamping protective circuit, its input is connected to the output of pipe dead band delay circuit;
Manage clamping protective circuit once, its input is connected to the output of lower pipe dead band delay circuit;
One lead-out terminal, this lead-out terminal comprises two-way pwm signal end, is respectively PWM1, PWM2, and wherein, PWM1 signal end connects upper pipe clamping protective circuit, and PWM2 signal end connects lower pipe clamping protective circuit.
Further, described upper pipe short pulse suppression circuit comprises the first electric capacity, the first comparator, the 3rd resistance, the first diode; This first electric capacity one end connects PWM-A signal end, other end ground connection; The 3rd resistance and the first diode are connected between the positive input terminal and output of the first comparator, the positive input terminal of this first comparator is also connected with PWM-A signal end, the negative input end of this first comparator is threshold voltage input, and the output of this first comparator is the output of upper pipe short pulse suppression circuit.
Further, described lower pipe short pulse suppression circuit comprises the second electric capacity, the second comparator, the 4th resistance, the second diode; This second electric capacity one end connects PWM-B signal end, other end ground connection; The 4th resistance and the second diode are connected between the positive input terminal and output of the second comparator, the positive input terminal of this second comparator is also connected with PWM-B signal end, the negative input end of this second comparator is threshold voltage input, and the output of this second comparator is the output of lower pipe short pulse suppression circuit.
Further, described upper pipe firstorder circuit comprises the 5th resistance, the 3rd electric capacity connecting successively from power input+VCC, the 3rd capacity earth, tie point Q1 between the 5th resistance and the 3rd electric capacity is connected with upper pipe short pulse suppression circuit output end, and time constant t1 equals the product of the 5th resistance and the 3rd electric capacity.
Further, described upper pipe dead band delay circuit comprises the 3rd comparator, the first schmitt inverter, the 7th resistance, the 9th resistance; The 3rd be input as+VCC of comparator power supply and ground, the reverse input end of the 3rd comparator is connected with upper pipe short pulse suppression circuit output end, its positive input is that threshold V T H2 input connect successively the 7th resistance, the 9th resistance are to+VCC, its output is connected with input, the 7th resistance and the tie point Q3 of the 9th resistance of the first schmitt inverter respectively, and the output of the first schmitt inverter is the output of upper pipe dead band delay circuit; The difference that the 3rd comparator output terminal lagged behind for the 3rd comparator input time flip-flop transition is Dead Time Td, and the functional relation of Td and threshold V T H2 is VTH2=VCC*[1-exp (Td/t1)].
Further, described lower pipe firstorder circuit comprises the 6th resistance, the 4th electric capacity connecting successively from power input+VCC, the 4th capacity earth, tie point Q2 between the 6th resistance and the 4th electric capacity is connected with upper pipe short pulse suppression circuit output end, and time constant t2 equals the product of the 6th resistance and the 4th electric capacity.
Further, described lower pipe dead band delay circuit comprises the 4th comparator, the second schmitt inverter, the 8th resistance, the tenth resistance; The 4th be input as+VCC of comparator power supply and ground, the reverse input end of the 4th comparator is connected with lower pipe short pulse suppression circuit output end, its positive input is that threshold V T H2 input connect successively the 8th resistance, the tenth resistance are to+VCC, its output is connected with input, the 8th resistance and the tie point Q4 of the tenth resistance of the second schmitt inverter respectively, and the output of the second schmitt inverter is the output of lower pipe dead band delay circuit; The difference that the 4th comparator output terminal lagged behind for the 4th comparator input time flip-flop transition is Dead Time Td, and the functional relation of Td and threshold V T H2 is VTH2=VCC*[1-exp (Td/t1)].
Further, described upper pipe clamping protective circuit comprises the 3rd diode, the 4th diode connecting successively from power supply+VCC, the 4th diode ground connection, and the tie point Q5 between its 3rd diode the 4th diode is connected to the output of pipe dead band delay circuit; Described lower pipe clamping protective circuit comprises the 5th diode, the 6th diode connecting successively from power supply+VCC, the 6th diode ground connection, and the tie point Q6 between its 5th diode, the 6th diode is connected to the output of lower pipe dead band delay circuit.
Further, between the positive input terminal of the first comparator and PWM-A signal end, be connected with the first resistance.
Further, between the positive input terminal of described the second comparator and PWM-B signal end, be connected with the second resistance.
Beneficial effect of the present invention:
IGBT Drive Protecting Circuit of the present invention adopts simple hardware circuit, suppresses short pulse, realize the time delay of IGBT upper, lower tube dead band and control, and it is anti-interference to have diode clamping circuit, and not only cost is low, and reliability is also high.
Accompanying drawing explanation
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described further.
Fig. 1 is the schematic diagram of IGBT temperature sensing circuit of the present invention;
Fig. 2 is the input voltage waveform figure of the 3rd comparator U1D and the 4th comparator U1A;
Fig. 3 is the oscillogram that PWM pulse-width signal generates Dead Time Td.
Embodiment
Shown in Fig. 1, a kind of IGBT Drive Protecting Circuit, comprising:
One input terminal J1, this input terminal receives the two-way pwm signal of peripheral control unit output, and this two-way pwm signal is designated as PWM-A, PWM-B;
On one, manage short pulse suppression circuit 10, on this, pipe short pulse suppression circuit 10 comprises the first capacitor C 1, the first comparator U1C, the 3rd resistance R 3, the first diode D1; This first capacitor C 1 one end connects PWM-A signal end, other end ground connection; The 3rd resistance R 3 and the first diode D1 are connected between the positive input terminal and output of the first comparator U1C, between the positive input terminal of the first comparator U1C and PWM-A signal end, be connected with the first resistance R 1, the negative input end of this first comparator U1C is threshold V T H1 input, and the output of this first comparator U1C is the output of upper pipe short pulse suppression circuit 10;
Manage short pulse suppression circuit 20 once, this lower pipe short pulse suppression circuit 20 comprises the second capacitor C 2, the second comparator U1B, the 4th resistance R 4, the second diode D2; These the second capacitor C 2 one end connect PWM-B signal end, other end ground connection; The 4th resistance R 4 and the second diode D2 are connected between the positive input terminal and output of the second comparator U1B, between the positive input terminal of the second comparator U1B and PWM-B signal end, be connected with the second resistance R 2, the negative input end of this second comparator U1B is threshold voltage input, and the output of this second comparator U1B is the output of lower pipe short pulse suppression circuit 20;
On one, manage firstorder circuit 30, be used for providing time constant t1, on this, pipe firstorder circuit 30 comprises the 5th resistance R 5, the 3rd capacitor C 3 connecting successively from power input+VCC, the 3rd capacitor C 3 ground connection, tie point Q1 between the 5th resistance R 5 and the 3rd capacitor C 3 is connected with upper pipe short pulse suppression circuit 10 outputs, and time constant t1 equals the product of the 5th resistance R 5 and the 3rd capacitor C 3;
Manage firstorder circuit 40 once, be used for providing time constant t2, this lower pipe firstorder circuit 40 comprises the 6th resistance R 6, the 4th capacitor C 4 connecting successively from power input+VCC, the 4th capacitor C 4 ground connection, tie point Q2 between the 6th resistance R 6 and the 4th capacitor C 4 is connected with upper pipe short pulse suppression circuit 10 outputs, and time constant t2 equals the product of the 6th resistance R 6 and the 4th capacitor C 4;
On one, manage dead band delay circuit 50, on this, pipe dead band delay circuit 50 comprises the 3rd comparator U1D, the first schmitt inverter U2A, the 7th resistance R 7, the 9th resistance R 9; The 3rd be input as+VCC of comparator U1D power supply and ground, the reverse input end of the 3rd comparator U1D is connected with upper pipe short pulse suppression circuit 10 outputs, its positive input is that threshold V T H2 input connect successively the 7th resistance R 7, the 9th resistance R 9 are to+VCC, its output is connected with input, the 7th resistance R 7 and the tie point Q3 of the 9th resistance R 9 of the first schmitt inverter U2A respectively, and the output of the first schmitt inverter U2A is the output of upper pipe dead band delay circuit 50; The difference that the 3rd comparator U1D output lagged behind for the 3rd comparator U1D input time flip-flop transition is Dead Time Td, and the functional relation of Td and threshold V T H2 is VTH2=VCC*[1-exp (Td/t1)];
Manage dead band delay circuit 60 once, this lower pipe dead band delay circuit 60 comprises the 4th comparator U1A, the second schmitt inverter U2B, the 8th resistance R 8, the tenth resistance R 10; The 4th be input as+VCC of comparator U1A power supply and ground, the reverse input end of the 4th comparator U1A is connected with lower pipe short pulse suppression circuit 20 outputs, its positive input is that threshold V T H2 input connect successively the 8th resistance R 8, the tenth resistance R 10 are to+VCC, its output is connected with input, the 8th resistance R 8 and the tie point Q4 of the tenth resistance R 10 of the second schmitt inverter U2B respectively, and the output of the second schmitt inverter U2B is the output of lower pipe dead band delay circuit 60; The difference that the 4th comparator U1A output lagged behind for the 4th comparator U1A input time flip-flop transition is Dead Time Td, and the functional relation of Td and threshold V T H2 is VTH2=VCC*[1-exp (Td/t1)];
On one, manage clamping protective circuit 70, upper pipe clamping protective circuit 70 comprises the 3rd diode D3, the 4th diode D4 connecting successively from power supply+VCC, the 4th diode D4 ground connection, the tie point Q5 between its 3rd diode D3 and the 4th diode D4 is connected to the output of pipe dead band delay circuit 50;
Manage clamping protective circuit 80 once, this lower pipe clamping protective circuit 80 comprises the 5th diode D5, the 6th diode D6 connecting successively from power supply+VCC, the 6th diode D6 ground connection, the tie point Q6 between its 5th diode D5, the 6th diode D6 is connected to the output of lower pipe dead band delay circuit 60;
One lead-out terminal J2, this lead-out terminal comprises two-way pwm signal end, is respectively PWM1, PWM2, and wherein, PWM1 signal end connects upper pipe clamping protective circuit 70, and PWM2 signal end connects lower pipe clamping protective circuit 80.
As shown in Figure 2, be the input voltage waveform of the 3rd comparator U1D and the 4th comparator U1A, transverse axis is time t, and the longitudinal axis is input voltage amplitude V, and Vs is crest voltage.
Operation principle of the present invention is:
IGBT Drive Protecting Circuit of the present invention is to be placed in peripheral control unit (as DSP, control IC etc.) and isolate between optocoupler, isolation optocoupler connects, pipe IGBT, by peripheral control unit, inputted, the pulse-width signal PWM-A of lower pipe IGBT, PWM-B is to input terminal J1, and through upper pipe short pulse suppression circuit 10 of the present invention, lower pipe short pulse suppression circuit 20 carries out short pulse suppression, and upper pipe dead band delay circuit 50, the effect of lower pipe dead band delay circuit 60 produces Dead Time Td, through lead-out terminal J2, spread out of supreme, lower two pipe IGBT, make, during lower two pipe IGBT alternation switch, one pipe is opened with another pipe and is turn-offed and have in time certain dead band delay time Td, the effect of diode clamping circuit is simultaneously the PWM1 that can prevent output, PWM2 signal is too high or too low, strengthened interference free performance.
Concrete, the first capacitor C 1 of input, the second electric capacity are as filter capacitor, can the unnecessary ripple of filtering, the first resistance R 1 of input and the second resistance R 2 are for finely tuning input voltage, the first comparator U1C and the second comparator U1B are used for suppressing short pulse, the setting of passing threshold voltage VTH1, and comparator U1C, U1B can suppress the short pulse lower than VTH1, wherein VTH1 can value be 5V, 8V, 10V, 12V, and VTH1 value principle is the VCC of 0.7 ~ 0.8 times;
As shown in Figure 3, and in conjunction with Fig. 1, pulse-width signal PWM-A, the PWM-B processing without IGBT Drive Protecting Circuit of the present invention is that input is complementary, without dead band; When pwm signal is from terminal JI input, through R1, C1; R2, enters the positive input terminal of comparator U1 after C2 filtering, and the 7th, 9 pin.More than managing circuit is example, when PWM-A rising edge arrives, the first comparator U1C the 14th pin is output as open collector, comparator U1D input (the 10th pin) some current potential is by R5, the firstorder circuit time constant that C3 forms determines, regulate VTH2 value, can make comparator U1D output (the 13rd pin) lag behind comparator U1D input (the 10th pin) time flip-flop transition, this time T d is Dead Time (Dead time), and Dead Time Td and VTH2 functional relation are Vth2=VCC*[1-exp (Td/R5*C3)]; When PWM trailing edge arrives, the 14th pin is output as low level, comparator U1D input (the 10th pin) some current potential is pulled low to rapidly electronegative potential (Fig. 2), show that the dead band time delay of comparator U1D only acts on the rising edge of pwm signal, because the high level of rising edge is only the signal that triggers IGBT upper, lower tube switch;
As Fig. 1, comparator U1D and U1A are oppositely inputs, and after its dead band time-lag action, pwm signal is reverse, for output phase and comparator input phase are consistent, is provided with schmitt inverter U2A and U2B; If schmitt inverter U2A and U2B are not set certainly, and by comparator U1D and the input of U1A forward, are also the effect that can realize dead band time delay, this just belongs to another embodiment of this programme; But this programme arranges schmitt inverter U2A and U2B can carry out shaping to output waveform, can be so that waveform be more level and smooth.
The foregoing is only preferential execution mode of the present invention, the present invention is not limited to above-mentioned execution mode, as long as within the technical scheme that realizes the object of the invention with basic identical means all belongs to protection scope of the present invention.
Claims (10)
1. an IGBT Drive Protecting Circuit, is characterized in that comprising:
One input terminal (J1), this input terminal receives the two-way pwm signal of peripheral control unit output, and this two-way pwm signal is designated as PWM-A, PWM-B;
On one, manage short pulse suppression circuit (10), its input is connected with the PWM-A signal end of input terminal (J1);
Manage short pulse suppression circuit (20) once, its input is connected with the PWM-B signal end of input terminal (J1);
On one, manage firstorder circuit (30), it is connected to pipe short pulse suppression circuit (10) output, for time constant t1 is provided;
Manage firstorder circuit (40) once, it is connected to lower pipe short pulse suppression circuit (20) output, for time constant t2 is provided;
On one, manage dead band delay circuit (50), its input is connected to pipe short pulse suppression circuit (10) output;
Manage dead band delay circuit (60) once, its input is connected to lower pipe short pulse suppression circuit (20) output;
On one, manage clamping protective circuit (70), its input is connected to the output of pipe dead band delay circuit (50);
Manage clamping protective circuit (80) once, its input is connected to the output of lower pipe dead band delay circuit (60);
One lead-out terminal (J2), this lead-out terminal comprises two-way pwm signal end, is respectively PWM1, PWM2, and wherein, PWM1 signal end connects upper pipe clamping protective circuit (70), and PWM2 signal end connects lower pipe clamping protective circuit (80).
2. a kind of IGBT Drive Protecting Circuit according to claim 1, is characterized in that: described upper pipe short pulse suppression circuit (10) comprises the first electric capacity (C1), the first comparator (U1C), the 3rd resistance (R3), the first diode (D1); This first electric capacity (C1) one end connects PWM-A signal end, other end ground connection; The 3rd resistance (R3) and the first diode (D1) are connected between the positive input terminal and output of the first comparator (U1C), the positive input terminal of this first comparator (U1C) is also connected with PWM-A signal end, the negative input end of this first comparator (U1C) is threshold voltage input, and the output of this first comparator (U1C) is the output of upper pipe short pulse suppression circuit (10).
3. a kind of IGBT Drive Protecting Circuit according to claim 1, is characterized in that: described lower pipe short pulse suppression circuit (20) comprises the second electric capacity (C2), the second comparator (U1B), the 4th resistance (R4), the second diode (D2); This second electric capacity (C2) one end connects PWM-B signal end, other end ground connection; The 4th resistance (R4) and the second diode (D2) are connected between the positive input terminal and output of the second comparator (U1B), the positive input terminal of this second comparator (U1B) is also connected with PWM-B signal end, the negative input end of this second comparator (U1B) is threshold voltage input, and the output of this second comparator (U1B) is the output of lower pipe short pulse suppression circuit (20).
4. a kind of IGBT Drive Protecting Circuit according to claim 1; it is characterized in that: described upper pipe firstorder circuit (30) comprises the 5th resistance (R5), the 3rd electric capacity (C3) connecting successively from power input+VCC; the 3rd electric capacity (C3) ground connection; tie point Q1 between the 5th resistance (R5) and the 3rd electric capacity (C3) is connected with upper pipe short pulse suppression circuit (10) output, and time constant t1 equals the product of the 5th resistance (R5) and the 3rd electric capacity (C3).
5. a kind of IGBT Drive Protecting Circuit according to claim 4, is characterized in that: described upper pipe dead band delay circuit (50) comprises the 3rd comparator (U1D), the first schmitt inverter (U2A), the 7th resistance (R7), the 9th resistance (R9); The 3rd comparator (U1D) be input as+VCC of power supply and ground, the reverse input end of the 3rd comparator (U1D) is connected with upper pipe short pulse suppression circuit (10) output, its positive input is that threshold V T H2 input connect successively the 7th resistance (R7), the 9th resistance (R9) are to+VCC, its output is connected with the tie point Q3 of the 9th resistance (R9) with input, the 7th resistance (R7) of the first schmitt inverter (U2A) respectively, and the output of the first schmitt inverter (U2A) is the output of upper pipe dead band delay circuit (50); The difference that the 3rd comparator (U1D) output lagged behind for the 3rd comparator (U1D) input time flip-flop transition is Dead Time Td, and the functional relation of Td and threshold V T H2 is VTH2=VCC*[1-exp (Td/t1)].
6. a kind of IGBT Drive Protecting Circuit according to claim 1; it is characterized in that: described lower pipe firstorder circuit (40) comprises the 6th resistance (R6), the 4th electric capacity (C4) connecting successively from power input+VCC; the 4th electric capacity (C4) ground connection; tie point Q2 between the 6th resistance (R6) and the 4th electric capacity (C4) is connected with upper pipe short pulse suppression circuit (10) output, and time constant t2 equals the product of the 6th resistance (R6) and the 4th electric capacity (C4).
7. a kind of IGBT Drive Protecting Circuit according to claim 6, is characterized in that: described lower pipe dead band delay circuit (60) comprises the 4th comparator (U1A), the second schmitt inverter (U2B), the 8th resistance (R8), the tenth resistance (R10); The 4th comparator (U1A) be input as+VCC of power supply and ground, the reverse input end of the 4th comparator (U1A) is connected with lower pipe short pulse suppression circuit (20) output, its positive input is that threshold V T H2 input connect successively the 8th resistance (R8), the tenth resistance (R10) are to+VCC, its output is connected with the tie point Q4 of the tenth resistance (R10) with input, the 8th resistance (R8) of the second schmitt inverter (U2B) respectively, and the output of the second schmitt inverter (U2B) is the output of lower pipe dead band delay circuit (60); The difference that the 4th comparator (U1A) output lagged behind for the 4th comparator (U1A) input time flip-flop transition is Dead Time Td, and the functional relation of Td and threshold V T H2 is VTH2=VCC*[1-exp (Td/t1)].
8. a kind of IGBT Drive Protecting Circuit according to claim 1, it is characterized in that: described upper pipe clamping protective circuit (70) comprises the 3rd diode (D3), the 4th diode (D4) connecting successively from power supply+VCC, the 4th diode (D4) ground connection, the tie point Q5 between its 3rd diode (D3) and the 4th diode (D4) is connected to the output of pipe dead band delay circuit (50); Described lower pipe clamping protective circuit (80) comprises the 5th diode (D5), the 6th diode (D6) connecting successively from power supply+VCC; the 6th diode (D6) ground connection, the tie point Q6 between its 5th diode (D5), the 6th diode (D6) is connected to the output of lower pipe dead band delay circuit (60).
9. a kind of IGBT Drive Protecting Circuit according to claim 2, is characterized in that: between the positive input terminal of the first comparator (U1C) and PWM-A signal end, be connected with the first resistance (R1).
10. a kind of IGBT Drive Protecting Circuit according to claim 3, is characterized in that: between the positive input terminal of described the second comparator (U1B) and PWM-B signal end, be connected with the second resistance (R2).
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104678327A (en) * | 2015-03-24 | 2015-06-03 | 陕西夸克自控科技有限公司 | Pulse high-voltage load circuit and working method |
| CN106787641A (en) * | 2016-12-28 | 2017-05-31 | 湘潭大学 | A kind of expansible insulating power supply circuit of On-off signal for protective relaying device |
| CN109347467A (en) * | 2015-11-16 | 2019-02-15 | 许继集团有限公司 | Control method is connected in IGBT and IGBT turns off control method |
| WO2023059767A1 (en) * | 2021-10-06 | 2023-04-13 | Retela Leasing, Llc | Power converters using precise timing control |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5402083A (en) * | 1993-06-07 | 1995-03-28 | Alliedsignal Inc. | Shoot-through protection circuit for improved stability in a neutral-point clamped synthesizer |
| CN1917369A (en) * | 2006-08-30 | 2007-02-21 | 广州金升阳科技有限公司 | IGBT drive, and process method for driving signal |
| CN101677240A (en) * | 2008-09-18 | 2010-03-24 | 比亚迪股份有限公司 | Isolated gate bipolar transistor driving circuit |
| CN101754560A (en) * | 2008-12-12 | 2010-06-23 | 东软飞利浦医疗设备系统有限责任公司 | grid modulator |
| CN103199678A (en) * | 2013-04-17 | 2013-07-10 | 国电南瑞科技股份有限公司 | Compact type insulated gate bipolar transistor (IGBT) module driving unit |
| CN203233336U (en) * | 2013-04-08 | 2013-10-09 | 东南大学 | A pulse width modulation wave converting circuit for adjusting dead time, high level, and low level |
| CN103647437A (en) * | 2013-10-28 | 2014-03-19 | 青岛艾迪森科技有限公司 | High-voltage high-current IGBT driving system |
| CN103701439A (en) * | 2013-12-24 | 2014-04-02 | 深圳市汇川技术股份有限公司 | Single-input double-output pulse width modulation (PWM) signal producing circuit |
| CN203859677U (en) * | 2014-04-11 | 2014-10-01 | 广东明阳龙源电力电子有限公司 | IGBT drive protective circuit |
-
2014
- 2014-04-11 CN CN201410146987.8A patent/CN103944372B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5402083A (en) * | 1993-06-07 | 1995-03-28 | Alliedsignal Inc. | Shoot-through protection circuit for improved stability in a neutral-point clamped synthesizer |
| CN1917369A (en) * | 2006-08-30 | 2007-02-21 | 广州金升阳科技有限公司 | IGBT drive, and process method for driving signal |
| CN101677240A (en) * | 2008-09-18 | 2010-03-24 | 比亚迪股份有限公司 | Isolated gate bipolar transistor driving circuit |
| CN101754560A (en) * | 2008-12-12 | 2010-06-23 | 东软飞利浦医疗设备系统有限责任公司 | grid modulator |
| CN203233336U (en) * | 2013-04-08 | 2013-10-09 | 东南大学 | A pulse width modulation wave converting circuit for adjusting dead time, high level, and low level |
| CN103199678A (en) * | 2013-04-17 | 2013-07-10 | 国电南瑞科技股份有限公司 | Compact type insulated gate bipolar transistor (IGBT) module driving unit |
| CN103647437A (en) * | 2013-10-28 | 2014-03-19 | 青岛艾迪森科技有限公司 | High-voltage high-current IGBT driving system |
| CN103701439A (en) * | 2013-12-24 | 2014-04-02 | 深圳市汇川技术股份有限公司 | Single-input double-output pulse width modulation (PWM) signal producing circuit |
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| CN109347467B (en) * | 2015-11-16 | 2022-11-29 | 许继集团有限公司 | IGBT (insulated Gate Bipolar transistor) turn-on control method and IGBT turn-off control method |
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