CN103943495A - Height adjusting method of metal and N-type silicon Schottky contact-potential barrier - Google Patents

Height adjusting method of metal and N-type silicon Schottky contact-potential barrier Download PDF

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Publication number
CN103943495A
CN103943495A CN201410114231.5A CN201410114231A CN103943495A CN 103943495 A CN103943495 A CN 103943495A CN 201410114231 A CN201410114231 A CN 201410114231A CN 103943495 A CN103943495 A CN 103943495A
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China
Prior art keywords
film
metal
deposit
type silicon
potential barrier
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CN201410114231.5A
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Inventor
刘彦涛
黄福成
田振兴
郝雪东
王斌
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JILIN MAGIC SEMICONDUCTOR Co Ltd
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JILIN MAGIC SEMICONDUCTOR Co Ltd
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Priority to CN201410114231.5A priority Critical patent/CN103943495A/en
Publication of CN103943495A publication Critical patent/CN103943495A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes
    • H01L29/872Schottky diodes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47Schottky barrier electrodes

Abstract

The invention belongs to the technical field of manufacturing of chips of discrete semiconductor devices and discloses a height adjusting method of metal and an N-type silicon Schottky contact-potential barrier. No method for continuously adjusting and controlling the height of the Schottky potential barrier exists in the prior art. The height adjusting method of the metal and N-type silicon Schottky contact-potential barrier is characterized in that the formation process of the metal and N-type silicon Schottky contact-potential barrier comprises the following steps that an Ni film and a Pt film deposit on an N-epitaxial layer through a metal deposition window, and then Ni and Pt are alloyed; the mass ratio of Ni and Pt in the NiPt alloy is controlled by controlling the thicknesses of the Ni film and the Pt film; an Ni, Pt and Si metal silicide potential barrier layer is formed on the upper surface layer of the N-epitaxial layer while alloying is carried out, and NiPt alloy not participating in the metal silicide reaction is removed. The height of the NiPt alloy and the N-type silicon Schottky contact-potential barrier can be accurately determined between 0.75 eV and 0.84 eV by adjusting the mass ratio of the Ni and the Pt in the NiPt alloy, and therefore the required electrical property of a Schottky diode is obtained.

Description

The control method of metal and N-type silicon Schotty contact berrier height
Technical field
The present invention relates to the control method of a kind of metal and N-type silicon Schotty contact berrier height, the potential barrier forming is nickel Platinum Silicide, accurately regulate metal and N-type silicon Schotty contact berrier height by adjusting nickel platinum mass ratio, thereby obtain the device electrical properties of wishing, belong to discrete-semiconductor device chip fabrication techniques field.
Background technology
Schottky diode (SBD), compared with common P-N junction diode, has that forward conduction voltage drop is low, reverse recovery time is short and the advantage such as Antisurge current ability is strong, is used in high-speed and high-efficiency rectification circuit, microwave circuit and high speed integrated circuit.Schottky diode is taking metal as anodal, described metal is selected from Au, Ag, Al, Pt, Mo, Ni, Ti, taking N type semiconductor as negative pole, described semiconductor is Si, the metal-semiconductor device that utilizes the potential barrier with rectification characteristic forming on the two contact-making surface to make.
Schottky diode tube core structure and manufacturing process thereof are as follows, as shown in Figure 1:
Select N type semiconductor as substrate, namely N+ substrate, its reason is that electronics is larger than hole mobility, can obtain so good frequency characteristic.
In order to reduce the junction capacitance of Schottky diode, improve reverse breakdown voltage, do not make again series resistance excessive simultaneously, extension one deck high resistance film on N+ substrate, obtains N-type epitaxial loayer, namely N-epitaxial loayer.
Clean and thermal oxidation N-epitaxial loayer, form oxide layer 1.
Adopt photoetching process successively to offer P+ Implantation window and metal deposit window, and complete the making of P+ diffused guard ring and the deposit of front metal layer 2.
But photoetching meeting forms precipitous edge.In addition, the Si-SiO between N-epitaxial loayer and oxide layer 1 2there is the fixed charge of positively charged in interface, in addition in oxide layer 1 and oxide layer 1 surface exist as several and a lot of stain the movable cation producing by alkali metal ion as sodium ion, and, the fixed charge of described positively charged can go out negative electrical charge at the Si of N-epitaxial loayer surface induction, make N-epitaxial loayer occur being become by N-type the tendency of N+ type on Si surface, reduce barrier properties.These factors make to strengthen near the semiconductor depletion region narrowed width of periphery and electric field, cause there is around the corner excessive drain saturation current, namely turning effect, this turning effect, except producing soft opposite feature and low breakdown voltage, also causes inferior noise characteristic.This just need to make P+ diffused guard ring around the corner; Pass through evaporation or sputtering deposit front metal layer 2, metal layer on back 3 in vacuum system time, front metal layer 2 and the oxide layer 1 of periphery are suitably overlapped, form overlap, at this moment repaired in the following depletion region of Metal-oxide-semicondutor (MOS) electric capacity, precipitous edge be can improve, soft opposite feature and low breakdown voltage avoided producing.Certainly, overlap can not be large, otherwise additional electric capacity can reduce device high frequency characteristics.Finally obtain having the Schottky diode of ideal I-V characteristic.
In the time that metal contacts with semiconductor, namely on N-epitaxial loayer, after deposit front metal layer 2, just form barrier layer 4 at metal-semiconductor interface place, Schottky barrier herein can be controlled electric current conduction and determine capacitance characteristic.
Because schottky barrier height has material impact to the electrical properties of Schottky diode, requiring has specific barrier height between metal-semiconductor, but, there is no in the prior art the method for regulation and control schottky barrier height continuously.
Summary of the invention
Object of the present invention be just to provide a kind of can continuous setup and control the method for schottky barrier height, for this reason, we have invented the control method of a kind of metal and N-type silicon Schotty contact berrier height.
According to the present invention's method, at N+ substrate one side extension one deck N-epitaxial loayer, thermal oxidation N-epitaxial loayer, form oxide layer 1, employing photoetching process is offered P+ Implantation window and is completed the making of P+ diffused guard ring, adopt photoetching process to offer metal deposit window, forming after metal and N-type silicon Schotty contact berrier, deposit front metal layer 2 on barrier layer 4, and front metal layer 2 overlaps with the oxide layer 1 of periphery, in addition, at N+ substrate opposite side deposit metal layer on back 3, it is characterized in that, the forming process of described metal and N-type silicon Schotty contact berrier is as follows, by metal deposit window, deposit Ni film on N-epitaxial loayer, Pt film, make again Ni, Pt alloying wherein, and by Ni, Pt mass ratio in the THICKNESS CONTROL NiPt alloy of control Ni film, Pt film, in alloying, form Ni, Pt, Si metal silicide barrier layer 4 at N-epitaxial loayer upper epidermis, remove the NiPt alloy of not participating in metal silicide reaction.
Simple substance Ni and N-type silicon Schotty contact berrier height are 0.75eV, and simple substance Pt and N-type silicon Schotty contact berrier height are 0.84eV.Its technique effect of the present invention is, NiPt alloy and N-type silicon Schotty contact berrier height can be by adjusting Ni, Pt mass ratio in NiPt alloy, to accurately determining between 0.84eV, as shown in Figure 2, obtain thus required Schottky diode electrical properties at 0.75eV.
Brief description of the drawings
Fig. 1 is Schottky diode tube core structure schematic diagram.Fig. 2 is the graph of relation of Ni, Pt mass ratio in schottky barrier height and NiPt alloy, and this figure doubles as Figure of abstract.
Embodiment
Epitaxial wafer is made.Get N-type (111) silicon chip as N+ substrate, at silicon chip one side extension one deck N-epitaxial loayer, obtain epitaxial wafer.
Clean epitaxial wafer.First clean 10 minutes at 60 DEG C of temperature with SC1 solution, described its composition of SC1 solution and proportioning are NH 4oH:H 2o 2: H 2o=1:1:5(volume ratio), remove particle contaminant and part metals ionic impurity, clean with deionized water normal temperature afterwards.Again epitaxial wafer is immersed in to HF:H 2o=1:50(volume ratio) solution in 3 minutes, remove epitaxial wafer oxide on surface, be immersed in afterwards in deionized water 15 minutes.
Oxide layer growth.Epitaxial wafer after cleaning is put into diffusion furnace at once, at 1000 DEG C of temperature, in oxygen atmosphere, the oxide layer 1 of growing on N-epitaxial loayer.
Open P+ Implantation window.In oxide layer 1, coat photoresist, sets litho pattern by reticle, and photolithographic exposure forms mask, and the not concealed oxide layer 1 of hydrofluoric acid solution erosion removal, obtains P+ Implantation window.
P+ diffused guard ring is made.Use implanter that boron ion is injected in N-epitaxial loayer by P+ Implantation window; Then in diffusion furnace, in nitrogen and oxygen atmosphere, at 1050 DEG C of temperature, anneal, activate the boron ion being injected into, allow them enter alternative site in the boron atom of interstitial void position by annealing some, form Schottky P+ diffused guard ring.
Karat gold belongs to deposit window.Coat at epitaxial wafer upper surface photoresist, sets litho pattern by reticle, and photolithographic exposure forms mask, and the not concealed oxide layer 1 of hydrofluoric acid solution erosion removal, obtains metal deposit window.
Form metal and N-type silicon Schotty contact berrier.Chemical cleaning has had the epitaxial wafer of metal deposit window, removes particle contaminant, organic impurities contamination and metal ion and stains; Be placed on afterwards on sputtering unit, in high vacuum sputtering chamber, by metal deposit window deposit Ni film, Pt film on N-epitaxial loayer, the deposition sequence of Ni film, Pt film has two kinds, and the one, first deposit Ni film deposit Pt film again, the 2nd, first deposit Pt film deposit Ni film again, Ni film and Pt film gross thickness exist in scope, determine, as in high temperature alloy stove, make again Ni, Pt alloying in Ni film, the Pt film of institute's deposit, the protection of alloying process inflated with nitrogen, avoid Ni film, Pt film Yin Gaowen and oxidized, alloying time is determined within the scope of 45min~55min, as 50min, Ni and Pt merge generation NiPt alloy, Ni, Pt mass ratio Ni:Pt=1:9~9:1 in NiPt alloy, in alloying, Si in Ni, Pt and N-epitaxial loayer upper epidermis generates metal silicide, thereby forms Ni, Pt, Si metal silicide barrier layer 4 at N-epitaxial loayer upper epidermis; Remove the NiPt alloy of not participating in metal silicide reaction with chloroazotic acid.
The deposit of front metal layer 2, metal layer on back 3.Deposit front metal layer 2 on barrier layer 4, and front metal layer 2 overlaps with the oxide layer 1 of periphery, in addition, at N+ substrate opposite side deposit metal layer on back 3, obtains Schottky diode tube core.Its barrier height φ bn0.75eV between 0.84eV determine.
When requiring as required Schottky barrier diode height φ bnduring for 0.807eV, according to the φ of schottky barrier height shown in Fig. 2 bnwith the graph of relation of Ni, Pt content ratio in NiPt alloy, Ni, Pt mass ratio are 5:5, determine thus the thickness of Ni film, Pt film; Because the density of Ni is 8.9g/cm 3, the density of Pt is 21.4g/cm 3, the density of Pt is 2.4 times of density of Ni, therefore, in the time that Ni film thickness is 2.4 times of Pt film thickness, Ni, Pt quality Bizet equal 5:5, when Ni film and Pt film gross thickness are defined as time, the thickness that can calculate Ni film is the thickness of Pt film is

Claims (4)

1. the control method of a metal and N-type silicon Schotty contact berrier height, at N+ substrate one side extension one deck N-epitaxial loayer, thermal oxidation N-epitaxial loayer, form oxide layer (1), employing photoetching process is offered P+ Implantation window and is completed the making of P+ diffused guard ring, adopt photoetching process to offer metal deposit window, forming after metal and N-type silicon Schotty contact berrier, at the upper deposit front metal layer (2) of barrier layer (4), and front metal layer (2) overlaps with the oxide layer (1) of periphery, in addition, at N+ substrate opposite side deposit metal layer on back (3), it is characterized in that, the forming process of described metal and N-type silicon Schotty contact berrier is as follows, by metal deposit window, deposit Ni film on N-epitaxial loayer, Pt film, make again Ni, Pt alloying wherein, and by Ni, Pt mass ratio in the THICKNESS CONTROL NiPt alloy of control Ni film, Pt film, in alloying, form Ni, Pt, Si metal silicide barrier layer (4) at N-epitaxial loayer upper epidermis, remove the NiPt alloy of not participating in metal silicide reaction.
2. the control method of metal according to claim 1 and N-type silicon Schotty contact berrier height, is characterized in that, the deposition sequence of Ni film, Pt film has two kinds, the one, and first deposit Ni film deposit Pt film again, the 2nd, first deposit Pt film deposit Ni film again.
3. the control method of metal according to claim 1 and N-type silicon Schotty contact berrier height, is characterized in that, Ni film and Pt film gross thickness exist in scope, determine.
4. the control method of metal according to claim 1 and N-type silicon Schotty contact berrier height, it is characterized in that, in high temperature alloy stove, make Ni, Pt alloying in Ni film, the Pt film of institute's deposit, the protection of alloying process inflated with nitrogen, alloying time is determined within the scope of 45min~55min; Ni, Pt mass ratio Ni:Pt=1:9~9:1 in NiPt alloy.
CN201410114231.5A 2014-03-24 2014-03-24 Height adjusting method of metal and N-type silicon Schottky contact-potential barrier Pending CN103943495A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107785249A (en) * 2016-08-31 2018-03-09 台湾积体电路制造股份有限公司 The method for manufacturing semiconductor device
CN109585570A (en) * 2018-12-19 2019-04-05 吉林麦吉柯半导体有限公司 The manufacturing method of Schottky diode, NIPT95 alloy and Schottky diode
WO2019119959A1 (en) * 2017-12-21 2019-06-27 秦皇岛京河科学技术研究院有限公司 Preparation method for sic schottky diode and structure thereof
CN113054007A (en) * 2021-03-17 2021-06-29 西安微电子技术研究所 Schottky diode made of NiPt15 alloy and preparation method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4816879A (en) * 1982-12-08 1989-03-28 North American Philips Corporation, Signetics Division Schottky-type rectifier having controllable barrier height
US6531396B1 (en) * 1999-11-17 2003-03-11 Institute Of Materials Research And Engineering Method of fabricating a nickel/platinum monsilicide film
CN102456748A (en) * 2010-10-22 2012-05-16 上海芯石微电子有限公司 Schottky diode and manufacturing method thereof
CN102496571A (en) * 2011-12-19 2012-06-13 杭州士兰集成电路有限公司 Method and structure for manufacturing low barrier Schottky diode

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4816879A (en) * 1982-12-08 1989-03-28 North American Philips Corporation, Signetics Division Schottky-type rectifier having controllable barrier height
US6531396B1 (en) * 1999-11-17 2003-03-11 Institute Of Materials Research And Engineering Method of fabricating a nickel/platinum monsilicide film
CN102456748A (en) * 2010-10-22 2012-05-16 上海芯石微电子有限公司 Schottky diode and manufacturing method thereof
CN102496571A (en) * 2011-12-19 2012-06-13 杭州士兰集成电路有限公司 Method and structure for manufacturing low barrier Schottky diode

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107785249A (en) * 2016-08-31 2018-03-09 台湾积体电路制造股份有限公司 The method for manufacturing semiconductor device
WO2019119959A1 (en) * 2017-12-21 2019-06-27 秦皇岛京河科学技术研究院有限公司 Preparation method for sic schottky diode and structure thereof
CN109585570A (en) * 2018-12-19 2019-04-05 吉林麦吉柯半导体有限公司 The manufacturing method of Schottky diode, NIPT95 alloy and Schottky diode
CN113054007A (en) * 2021-03-17 2021-06-29 西安微电子技术研究所 Schottky diode made of NiPt15 alloy and preparation method thereof

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