CN103928331A - Metal oxide semiconductor (MOS) transistor forming method - Google Patents
Metal oxide semiconductor (MOS) transistor forming method Download PDFInfo
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- CN103928331A CN103928331A CN201310011744.9A CN201310011744A CN103928331A CN 103928331 A CN103928331 A CN 103928331A CN 201310011744 A CN201310011744 A CN 201310011744A CN 103928331 A CN103928331 A CN 103928331A
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- mos transistor
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- hydrogen peroxide
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- 238000000034 method Methods 0.000 title claims abstract description 77
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 229910044991 metal oxide Inorganic materials 0.000 title 1
- 150000004706 metal oxides Chemical class 0.000 title 1
- 239000010410 layer Substances 0.000 claims abstract description 118
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims abstract description 69
- 239000011229 interlayer Substances 0.000 claims abstract description 49
- 239000000758 substrate Substances 0.000 claims abstract description 32
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 29
- 239000011259 mixed solution Substances 0.000 claims abstract description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 46
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 29
- 230000015572 biosynthetic process Effects 0.000 claims description 28
- 238000005516 engineering process Methods 0.000 claims description 23
- 239000000243 solution Substances 0.000 claims description 21
- 239000000463 material Substances 0.000 claims description 20
- 239000000377 silicon dioxide Substances 0.000 claims description 20
- 230000003647 oxidation Effects 0.000 claims description 19
- 238000007254 oxidation reaction Methods 0.000 claims description 19
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 14
- 239000011241 protective layer Substances 0.000 claims description 11
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical group [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 9
- -1 tetramethyl hydroxylamine Chemical compound 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 239000007864 aqueous solution Substances 0.000 claims description 5
- 238000001039 wet etching Methods 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 abstract 2
- 229910021529 ammonia Inorganic materials 0.000 abstract 1
- 239000007769 metal material Substances 0.000 description 14
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 4
- 239000012895 dilution Substances 0.000 description 4
- 238000010790 dilution Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 241001212149 Cathetus Species 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000003701 mechanical milling Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- BRGOCSWOKBOIOJ-UHFFFAOYSA-N N.[O-2].[Hf+4] Chemical compound N.[O-2].[Hf+4] BRGOCSWOKBOIOJ-UHFFFAOYSA-N 0.000 description 1
- YNKZDZAIBIBPGW-UHFFFAOYSA-N N.[O-2].[Sr+2] Chemical compound N.[O-2].[Sr+2] YNKZDZAIBIBPGW-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- BOIGHUSRADNYQR-UHFFFAOYSA-N aluminum;lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Al+3].[La+3] BOIGHUSRADNYQR-UHFFFAOYSA-N 0.000 description 1
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- QOSATHPSBFQAML-UHFFFAOYSA-N hydrogen peroxide;hydrate Chemical compound O.OO QOSATHPSBFQAML-UHFFFAOYSA-N 0.000 description 1
- 230000003116 impacting effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 150000002978 peroxides Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
Abstract
An MOS transistor forming method comprises providing a semiconductor substrate; forming a dummy gate structure on the semiconductor substrate, and forming an interlayer dielectric layer on the semiconductor substrate on the two sides of the dummy gate structure, wherein the dummy gate structure comprises a dummy gate dielectric layer on the semiconductor substrate and a dummy gate on the dummy gate dielectric layer, and the upper surface of the dummy gate is flush with the upper surface of the interlayer dielectric layer; removing the dummy gate; removing the dummy gate dielectric layer through an ammonia, hydrogen peroxide and water mixed solution to form a groove; forming a gate structure in the groove, wherein the upper surface of the gate structure is flush with the upper surface of the interlayer dielectric layer. The MOS transistor formed by the method is good in performance and high in yield.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of MOS transistor.
Background technology
Along with the development of semiconductor technology, the characteristic size of MOS transistor is constantly dwindled, in MOS transistor, the thickness of gate dielectric layer also thins down by the principle of scaled down, when the thickness of described gate dielectric layer is thinned to after certain degree, its integrity problem, especially with the puncturing of time correlation, hot carrier's effect, gate electrode in impurity to problems such as the diffusions of substrate, will have a strong impact on stability and the reliability of device.Now, silicon oxide layer has reached its physics limit as gate dielectric layer, utilize the gate dielectric layer replace oxygen SiClx gate dielectric layer of high k material, can in the situation that keeping equivalent oxide thickness (EOT) constant, greatly increase its physical thickness, thereby reduce grid leakage current.
When MOS transistor that existing technique comprises high k material gate dielectric layer in formation, mainly comprise the steps: with reference to figure 1, Semiconductor substrate 100 is provided, in described Semiconductor substrate 100, be formed with pseudo-grid structure and be positioned at the interlayer dielectric layer 108 in pseudo-grid structure semiconductor substrates on two sides 100, described pseudo-grid structure comprise the pseudo-gate dielectric layer 102 of the silica being positioned in Semiconductor substrate 100, be positioned at the pseudo-grid 104 of polysilicon on pseudo-gate dielectric layer 102 and be positioned at pseudo-gate dielectric layer 102 and pseudo-grid 104 sidewalls on side wall 106; With reference to figure 2, remove pseudo-grid 104 described in Fig. 1; With reference to figure 3, remove pseudo-gate dielectric layer 102 described in Fig. 2 by the hydrofluoric acid solution of dilution, form groove 110; With reference to figure 4, at the gate dielectric layer 112 of the high k material of the interior formation of groove 110 described in Fig. 3 be positioned at the metal gates 114 on gate dielectric layer 112.
But, in the time that detecting, the MOS transistor that above-mentioned technique is formed finds, and the MOS transistor that existing technique forms easily lost efficacy, and rate of finished products is low.
The formation method of more MOS transistor please refer to the U.S. Patent application that application number is US2008149982A1.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of MOS transistor, improves performance and the rate of finished products of the MOS transistor that forms.
For addressing the above problem, the invention provides a kind of formation method of MOS transistor, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form pseudo-grid structure, and form interlayer dielectric layer in the Semiconductor substrate of pseudo-grid structure both sides, described pseudo-grid structure comprises the pseudo-gate dielectric layer being positioned in Semiconductor substrate and is positioned at the pseudo-grid on pseudo-gate dielectric layer, the upper surface of described pseudo-grid and the upper surface flush of described interlayer dielectric layer;
Remove described pseudo-grid;
Mixed solution by ammoniacal liquor, hydrogen peroxide and water is removed described pseudo-gate dielectric layer, forms groove;
In described groove, form grid structure, the upper surface of described grid structure and the upper surface flush of described interlayer dielectric layer.
Optionally, the temperature of the mixed solution of described ammoniacal liquor, hydrogen peroxide and water is 25 DEG C ~ 65 DEG C, and the volume ratio of ammoniacal liquor, hydrogen peroxide and water is 1:1 ~ 5:50 ~ 200.
Compared with prior art, technical solution of the present invention has the following advantages:
Mixed solution by ammoniacal liquor, hydrogen peroxide and water is removed described pseudo-gate dielectric layer, because the mixed solution of ammoniacal liquor, hydrogen peroxide and water is less to the etch rate of interlayer dielectric layer, in the pseudo-gate dielectric layer process of removal, can effectively avoid removing too much interlayer dielectric layer, and then in the forming process of grid structure, avoid at interlayer dielectric layer remained on surface metal material, prevent that the metal material that residues in dielectric layer surface from impacting the performance of MOS transistor, improved performance and the rate of finished products of the MOS transistor that forms.
Brief description of the drawings
Fig. 1 ~ Fig. 4 is the schematic diagram that forms MOS transistor in existing technique;
Fig. 5 is the schematic flow sheet of formation method one execution mode of MOS transistor of the present invention;
Fig. 6 ~ Figure 10 is the schematic diagram of formation method one embodiment of MOS transistor of the present invention;
Figure 11 is while removing by the mixed solution of ammoniacal liquor, hydrogen peroxide and water the silica forming by thermal oxidation technology, the graph of a relation of removal time and the silicon oxide thickness of removing;
Figure 12 is while removing by the mixed solution of ammoniacal liquor, hydrogen peroxide and water the silica forming by sub-aumospheric pressure cvd technique, the graph of a relation of removal time and the silicon oxide thickness of removing.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth in the following description a lot of details so that fully understand the present invention, implemented but the present invention can also adopt other to be different from alternate manner described here, therefore the present invention is not subject to the restriction of following public specific embodiment.
Just as described in the background section, the MOS transistor that existing technique forms easily lost efficacy, rate of finished products is low.
Inventor finds through research, the MOS transistor that existing technique forms easily lost efficacy, rate of finished products is low is mainly caused by following reason: in Fig. 1, the material of the pseudo-gate dielectric layer 102 of MOS transistor and the material of interlayer dielectric layer 108 are silica, remove described pseudo-gate dielectric layer 102 simultaneously at the hydrofluoric acid solution by dilution, also can consume the interlayer dielectric layer 108 of segment thickness.But because the formation method of pseudo-gate dielectric layer 102 and interlayer dielectric layer 108 is different, the method that forms pseudo-gate dielectric layer 102 is thermal oxidation technology, the method that forms interlayer dielectric layer 108 is chemical vapor deposition method, the hydrofluoric acid solution of dilution is not identical to pseudo-gate dielectric layer 102 and interlayer dielectric layer 108 etch rates yet, and it is about 1:13 to pseudo-gate dielectric layer 102 and interlayer dielectric layer 108 etch rate ratios.Therefore, although the thinner thickness of pseudo-gate dielectric layer 102, but due to dilution hydrofluoric acid solution to the etch rate of interlayer dielectric layer 108 much larger than the etch rate to pseudo-gate dielectric layer 102, while causing removing pseudo-gate dielectric layer 102, can remove thicker interlayer dielectric layer 108, make the upper surface of interlayer dielectric layer 108 in Fig. 3 lower than the top of side wall 106.After pseudo-grid 104 and pseudo-gate dielectric layer 102 are removed, while forming in Fig. 4 gate dielectric layer 112 and metal gates 114, be used to form the metal material of metal gates 114 in filling up Fig. 3 further groove 110, also cover the interlayer dielectric layer 108 of side wall 106 tops and side wall 106 both sides.Follow-up by chemical mechanical milling tech planarization material material, form after metal gates 114, interlayer dielectric layer 108 surfaces that are positioned at side wall 106 both sides are also covered by metal material 116, have affected the insulating properties of interlayer dielectric layer 108, cause that formed MOS transistor lost efficacy, rate of finished products is low.
Further study discovery through inventor, the solution being formed by ammoniacal liquor, hydrogen peroxide and water to the etch rate of the interlayer dielectric layer forming by chemical vapor deposition method with the etch rate of the pseudo-gate dielectric layer forming by thermal oxidation technology is more or less the same, and due to the thinner thickness of pseudo-gate dielectric layer, the time of removing pseudo-gate dielectric layer is completely shorter, removes pseudo-gate dielectric layer little on the impact of interlayer dielectric layer.Forming in grid structure process, can effectively avoid interlayer dielectric layer to be covered by metal material, and then improve performance and the rate of finished products of the MOS transistor that forms.
Be elaborated below in conjunction with specific embodiment.
With reference to figure 5, be the schematic flow sheet of formation method one execution mode of MOS transistor of the present invention, comprising:
Step S1, provides Semiconductor substrate;
Step S2, in described Semiconductor substrate, form pseudo-grid structure, and form interlayer dielectric layer in the Semiconductor substrate of pseudo-grid structure both sides, described pseudo-grid structure comprises the pseudo-gate dielectric layer being positioned in Semiconductor substrate and is positioned at the pseudo-grid on pseudo-gate dielectric layer, the upper surface of described pseudo-grid and the upper surface flush of described interlayer dielectric layer;
Step S3, removes described pseudo-grid;
Step S4, removes described pseudo-gate dielectric layer by the mixed solution of ammoniacal liquor, hydrogen peroxide and water, forms groove;
Step S5, forms protective layer at described bottom portion of groove;
Step S6 forms gate dielectric layer on described protective layer;
Step S7 forms metal material on described gate dielectric layer and interlayer dielectric layer;
Step S8, carries out flatening process to described metal material, to exposing described interlayer dielectric layer, forms grid.
With reference to figure 6 ~ Figure 12, by specific embodiment, the formation method of MOS transistor of the present invention is described further.
With reference to figure 6, provide Semiconductor substrate 200.
In the present embodiment, the material of described Semiconductor substrate 200 is monocrystalline silicon, SiGe, silicon-carbon or III-V compounds of group (such as gallium arsenic, indium phosphide and gallium nitride etc.).In described Semiconductor substrate 200, be also formed with fleet plough groove isolation structure (not shown), adjacent active area is isolated mutually.In Semiconductor substrate 200, also have well region (not shown), in well region, the doping conduction type of ion is relevant with the type of formed MOS transistor.In the time that formed MOS transistor is nmos pass transistor, in well region, the conduction type of doping ion is P type, as boron ion, boron difluoride ion etc.In the time that formed MOS transistor is PMOS transistor, in well region, the conduction type of doping ion is N-type, as phosphonium ion, arsenic ion etc.
Continue with reference to figure 6, in described Semiconductor substrate 200, form pseudo-grid structure, and form interlayer dielectric layer 208 in the Semiconductor substrate 200 of pseudo-grid structure both sides, described pseudo-grid structure comprises the pseudo-gate dielectric layer 202 that is positioned in Semiconductor substrate 200, be positioned at pseudo-grid 204 on pseudo-gate dielectric layer 202 and be positioned at pseudo-gate dielectric layer 202 and pseudo-grid 204 sidewalls on side wall 206, the upper surface flush of the upper surface of described pseudo-grid 204 and described interlayer dielectric layer 208.
In the present embodiment, the material of described pseudo-gate dielectric layer 202 is silica, and the method that forms described pseudo-gate dielectric layer 202 is thermal oxidation technology.In the time of the pseudo-grid 204 of follow-up removal, pseudo-gate dielectric layer 202 can protect described Semiconductor substrate 200 to avoid damage.
Described side wall 206 can be single layer structure, can be also laminated construction.The material of side wall 206 can be one or more combinations of silicon nitride, silicon oxynitride or silica.The material of described pseudo-grid 204 can be polysilicon.
The material of described interlayer dielectric layer 208 is silica, and the method that forms described interlayer dielectric layer 208 is chemical vapor deposition method, as based on ozone (O
3) and the sub-aumospheric pressure cvd of tetraethoxysilane (Tetraethyl Orthosilicate, referred to as TEOS) (Sub-atmospheric Chemical Vapor Deposition is called for short SACVD) technique.
With reference to figure 7, remove pseudo-grid 204 described in Fig. 6.
In the present embodiment, the method for removing described pseudo-grid 204 is wet etching, and the solution of described wet etching can be ammoniacal liquor or tetramethyl hydroxylamine solution.For example, can adopt mass percent is that 2.38% tetramethyl hydroxylamine solution is removed described pseudo-grid 204.
In pseudo-grid 204 processes of removal, pseudo-gate dielectric layer 202 can effectively be protected the Semiconductor substrate 200 that is positioned at its below, avoids wet-etching technology to cause damage to the channel region of MOS transistor, improves the performance of the MOS transistor that forms.
With reference to figure 8, by ammoniacal liquor (NH
4oH), hydrogen peroxide (H
2o
2) and water (H
2o) mixed solution is removed pseudo-gate dielectric layer 202 described in Fig. 7, forms groove 210.
In the present embodiment, mixed solution (the Standard Cleaning-1 of ammoniacal liquor, hydrogen peroxide and water, referred to as SC1 solution) temperature be 25 DEG C ~ 65 DEG C, in the mixed solution of ammoniacal liquor, hydrogen peroxide and water, the volume ratio of ammoniacal liquor, hydrogen peroxide and water is 1: 1 ~ 5:50 ~ 200.Because the mixed solution of ammoniacal liquor, hydrogen peroxide and water is more or less the same to the etch rate of pseudo-gate dielectric layer 202 and interlayer dielectric layer 208, and due to the thinner thickness of pseudo-gate dielectric layer 202, the time of removing pseudo-gate dielectric layer 202 is completely shorter, the thickness that consumes interlayer dielectric layer 208 is also thinner, removes pseudo-gate dielectric layer 202 little on the impact of interlayer dielectric layer 208.
With reference to figure 9, form protective layer 212 in the bottom of groove 210 described in Fig. 8.
In the present embodiment, the material of described protective layer 212 is silica.The method that forms protective layer 212 is wet process oxidation technology; to form the silicon oxide film of thinner thickness; gate dielectric layer isolation by Semiconductor substrate 200 with follow-up formation, avoids metallic atom in gate dielectric layer to enter the channel region of MOS transistor, and then improves the performance of the MOS transistor that forms.
Concrete, the solution of described wet process oxidation technology can be ozone (O
3) the aqueous solution, in the aqueous solution of described ozone, the mass concentration of ozone is 30ppm ~ 80ppm, the time of wet process oxidation technology is 30s ~ 180s.The aqueous solution 30s ~ 180s that sprays the ozone that mass concentration is 30ppm ~ 80ppm to Fig. 8 further groove 210 bottoms, changes into silica by Semiconductor substrate 200 Surface Oxygens of groove 210 bottoms, forms protective layer 212.
The solution of described wet process oxidation technology also can be the mixed solution that temperature is ammoniacal liquor, hydrogen peroxide and the water of 25 DEG C ~ 65 DEG C, and in the mixed solution of ammoniacal liquor, hydrogen peroxide and water, the volume ratio of ammoniacal liquor, hydrogen peroxide and water is 1:1 ~ 5:50 ~ 200.
It is the 120 DEG C ~ sulfuric acid of 180 DEG C and the mixed solution of hydrogen peroxide that the solution of described wet process oxidation technology also can be temperature.Adopt the mixed solution of sulfuric acid and hydrogen peroxide to carry out dioxysulfate water cleaning (Sulfuric Peroxide Method, referred to as SPM), form described protective layer 212.In the mixed solution of sulfuric acid and hydrogen peroxide, the volume ratio of sulfuric acid and hydrogen peroxide is 2 ~ 5:1, and the time of wet process oxidation technology is 30s ~ 300s.
Continue with reference to figure 9, on described protective layer 212, form gate dielectric layer 214.
In the present embodiment, the material of described gate dielectric layer 214 is high k material, as one or more in hafnium oxide, zirconia, lanthana, aluminium oxide, titanium oxide, strontium titanates, aluminium oxide lanthanum, yittrium oxide, nitrogen hafnium oxide, nitrogen zirconia, nitrogen lanthana, aluminum oxynitride, titanium oxynitrides, nitrogen strontium oxide strontia titanium, nitrogen lanthana aluminium, yttrium oxynitride.The method that forms described gate dielectric layer 214 is chemical vapor deposition method or atom layer deposition process.In other embodiments, described gate dielectric layer 214 can also be other high k materials.
Continue with reference to figure 9, on described gate dielectric layer 214 and interlayer dielectric layer 208, form metal material 216a.
In the present embodiment, the material of described metal material 216a can be aluminium or tungsten, and the method that forms described metal material 216a can be physical gas-phase deposition.
With reference to Figure 10, to metal material described in Fig. 9,216a carries out flatening process, to exposing described interlayer dielectric layer 208, forms grid 216b.
In the present embodiment, described flatening process can be chemical mechanical milling tech.
It should be noted that, although in the time removing pseudo-gate dielectric layer 202, can remove the interlayer dielectric layer 208 of segment thickness, but because the time of the pseudo-gate dielectric layer 202 of removal is shorter, the thinner thickness of removing interlayer dielectric layer 208, in the time carrying out flatening process, the metal material 216a being positioned on interlayer dielectric layer 208 can be completely removed, can effectively avoid interlayer dielectric layer 208 to be covered by metal material 216a, better performances, the rate of finished products of the MOS transistor that forms are high.
With reference to Figure 11, be 65 DEG C for adopting temperature, when the mixed solution that the volume ratio of ammoniacal liquor, hydrogen peroxide and water is 1:2:100 is removed the silica forming by thermal oxidation technology, the graph of a relation of removal time and the silicon oxide thickness of removing.As shown in Figure 11, in the time that the removal time is 5 minutes, 10 minutes and 15 minutes, the thickness of the silica of removing is 4.3 dusts, 6.2 dusts and 9.0 dusts, the removal time is similar to and meets Figure 11 cathetus 301 with the thickness of the silica of removing, the slope of straight line 301 is 0.472, and the removal speed of silica is that 0.472 dust is per minute.
With reference to Figure 12, it is 65 DEG C for adopting temperature, the volume ratio of ammoniacal liquor, hydrogen peroxide and water is the mixed solution of 1:2:100 while removing the silica that the sub-aumospheric pressure cvd technique based on ozone and tetraethoxysilane forms, the graph of a relation of removal time and the silicon oxide thickness of removing.As shown in Figure 12, in the time that the removal time is 5 minutes, 10 minutes, 15 minutes, the thickness of removing silica is 5.37 dusts, 10.50 dusts and 17.68 dusts, the removal time is similar to and meets Figure 12 cathetus 303 with the thickness of the silica of removing, the slope of straight line 303 is 1.231, and the removal speed of silica is that 1.231 dusts are per minute.
From Figure 11 and Figure 12, it is 1:2.6 with the ratio of the removal speed of the silica that sub-aumospheric pressure cvd technique is formed that the silica that the mixed solution of ammoniacal liquor, hydrogen peroxide and water forms thermal oxidation technology is removed speed, and it is much larger than 1:13.Therefore, while removing pseudo-gate dielectric layer 202 by the mixed solution of ammoniacal liquor, hydrogen peroxide and water, impact on interlayer dielectric layer 208 is less, and then can be above interlayer dielectric layer 208 kish material 216a, avoid the metal material 216a that residues in interlayer dielectric layer 208 tops to impact the performance of formed MOS transistor, improved performance and the rate of finished products of MOS transistor.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible variation and amendment to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.
Claims (15)
1. a formation method for MOS transistor, is characterized in that, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form pseudo-grid structure, and form interlayer dielectric layer in the Semiconductor substrate of pseudo-grid structure both sides, described pseudo-grid structure comprises the pseudo-gate dielectric layer being positioned in Semiconductor substrate and is positioned at the pseudo-grid on pseudo-gate dielectric layer, the upper surface of described pseudo-grid and the upper surface flush of described interlayer dielectric layer;
Remove described pseudo-grid;
Mixed solution by ammoniacal liquor, hydrogen peroxide and water is removed described pseudo-gate dielectric layer, forms groove;
In described groove, form grid structure, the upper surface of described grid structure and the upper surface flush of described interlayer dielectric layer.
2. the formation method of MOS transistor as claimed in claim 1, is characterized in that, the temperature of the mixed solution of described ammoniacal liquor, hydrogen peroxide and water is 25 DEG C ~ 65 DEG C, and the volume ratio of ammoniacal liquor, hydrogen peroxide and water is 1:1 ~ 5:50 ~ 200.
3. the formation method of MOS transistor as claimed in claim 1, is characterized in that, the method that forms described pseudo-gate dielectric layer is thermal oxidation technology.
4. the formation method of MOS transistor as claimed in claim 1, is characterized in that, the method that forms described interlayer dielectric layer is chemical vapor deposition method.
5. the formation method of MOS transistor as claimed in claim 1, is characterized in that, the material of described pseudo-grid is polysilicon, and the method for removing described pseudo-grid is wet etching.
6. the formation method of MOS transistor as claimed in claim 5, is characterized in that, the solution of described wet etching is ammoniacal liquor or tetramethyl hydroxylamine solution.
7. the formation method of MOS transistor as claimed in claim 1, is characterized in that, before forming grid structure, also comprises in described groove: protective layer is formed on the bottom at described groove.
8. the formation method of MOS transistor as claimed in claim 7, is characterized in that, the material of described protective layer is silica.
9. the formation method of MOS transistor as claimed in claim 8, is characterized in that, the method that forms protective layer in the bottom of described groove is wet process oxidation technology.
10. the formation method of MOS transistor as claimed in claim 9, is characterized in that, the aqueous solution that the solution of described wet process oxidation technology is ozone.
The formation method of 11. MOS transistor as claimed in claim 10, is characterized in that, in the aqueous solution of described ozone, the mass concentration of ozone is 30ppm ~ 80ppm, and the time of wet process oxidation technology is 30s ~ 180s.
The formation method of 12. MOS transistor as claimed in claim 9, is characterized in that, the solution of described wet process oxidation technology is the mixed solution of ammoniacal liquor, hydrogen peroxide and water.
The formation method of 13. MOS transistor as claimed in claim 12, is characterized in that, the temperature of the mixed solution of described ammoniacal liquor, hydrogen peroxide and water is 25 DEG C ~ 65 DEG C, and the volume ratio of ammoniacal liquor, hydrogen peroxide and water is 1:1 ~ 5:50 ~ 200.
The formation method of 14. MOS transistor as claimed in claim 9, is characterized in that, the solution of described wet process oxidation technology is the mixed solution of sulfuric acid and hydrogen peroxide.
The formation method of 15. MOS transistor as claimed in claim 14, is characterized in that, the temperature of the mixed solution of described sulfuric acid and hydrogen peroxide is 120 DEG C ~ 180 DEG C, and the volume ratio of sulfuric acid and hydrogen peroxide is 2 ~ 5:1, and the time of wet process oxidation technology is 30s ~ 300s.
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001274381A (en) * | 2000-03-27 | 2001-10-05 | Toshiba Corp | Manufacturing method for semiconductor device |
CN1349247A (en) * | 2000-10-13 | 2002-05-15 | 海力士半导体有限公司 | Method for forming metallic grid |
US20070042583A1 (en) * | 2005-08-16 | 2007-02-22 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
CN102104070A (en) * | 2009-12-21 | 2011-06-22 | 中国科学院微电子研究所 | Semiconductor structure and forming method thereof |
CN102569164A (en) * | 2010-12-14 | 2012-07-11 | 瑞萨电子株式会社 | Semiconductor integrated circuit device |
-
2013
- 2013-01-11 CN CN201310011744.9A patent/CN103928331B/en active Active
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001274381A (en) * | 2000-03-27 | 2001-10-05 | Toshiba Corp | Manufacturing method for semiconductor device |
CN1349247A (en) * | 2000-10-13 | 2002-05-15 | 海力士半导体有限公司 | Method for forming metallic grid |
US20070042583A1 (en) * | 2005-08-16 | 2007-02-22 | Samsung Electronics Co., Ltd. | Semiconductor device and method of manufacturing the same |
CN102104070A (en) * | 2009-12-21 | 2011-06-22 | 中国科学院微电子研究所 | Semiconductor structure and forming method thereof |
CN102569164A (en) * | 2010-12-14 | 2012-07-11 | 瑞萨电子株式会社 | Semiconductor integrated circuit device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105990114A (en) * | 2015-01-30 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | Method of forming semiconductor device |
CN105990114B (en) * | 2015-01-30 | 2019-04-26 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
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