CN103904542A - Laser driver double closed loop control method capable of being used for burst mode - Google Patents
Laser driver double closed loop control method capable of being used for burst mode Download PDFInfo
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Abstract
The invention provides a laser driver double closed loop control method capable of being used for a burst mode. A method for comparing a high-speed current mirror and a high-speed current comparator is adopted, and first luminous power P1 is detected when a laser normally emits light, a modulation current is high and transmission data are 1; a sampling keeping method is adopted, and average luminous power Pa is detected when the laser normally emits the light; the high-speed current mirror outputs two control ends, one control end and a voltage V_Pa_set of the set average luminous power form a negative feedback used for controlling and driving a bias current Ibias in the current of the laser, and a first closed loop system is formed; the other control end and a current I_P1_set of the set first luminous power P1 form a negative feedback used for controlling and driving a modulation current Imod in the current of the laser, and a second closed-loop system is formed; by means of the first closed-loop system and the second closed-loop system, the bias current Ibias and the modulation current Imod can be automatically regulated, and therefore the stable first luminous power P1 and the stable average luminous power Pa can be obtained.
Description
Technical field
The present invention relates to optical communication field, relate in particular to a kind of control method of laser driver.
Background technology
In optical communication, the index of laser on power mainly contains following 4:
P0, laser is normally luminous, and modulated current is low, represents that transmission data are the power of 0 o'clock;
P1, laser is normally luminous, and modulated current is high, represents that transmission data are the power of 1 o'clock;
Pa, the normal average light power when luminous of laser, Pa=(P1+P0)/2;
R
e, extinction ratio, the numerical value of sign eye opening, r
e=10log (P1/P0).
Above 4 amounts are correlated with, as long as determined wherein two, have also determined for another two.In optical communication transmitting procedure, system requirements keeps constant transmitting average light power and extinction ratio, and two closed loop design of laser driver also will keep the stable of these two amounts by two negative feedback structures just.The more difficult detection of extinction ratio needs to detect Pa in the design of two closed loops, P1, two values in P0.And P1, P0 is signal at a high speed in transient state, is the high speed signal of 1.25Gbps in GPON/EPON system, therefore testing circuit need to be the circuit of a high speed.The luminous situation of detection laser is all to be undertaken by the image current of the diode backlight of laser.At present the junction capacitance of conventional this diode of laser is that 3-20pF. back facet current also only has hundreds of uA conventionally, and so little electric current has again so large electric capacity, and it is more difficult reducing this high speed signal.
Existing pair of closed loop be designed with several method.Having one is to adopt a trans-impedance amplifier, directly PD electric current is zoomed into voltage signal.The voltage signal that the electric current of hundreds of uA will be zoomed into hundreds of mV, could facilitate the processing of circuit below, therefore need more than 1K across resistance.But be difficult to input capacitance 20pF left and right of design, bandwidth hundreds of MHZ, the again trans-impedance amplifier of the linearity fine (guaranteeing to set the accuracy of luminous power and little light ratio).
Summary of the invention
Technical problem underlying to be solved by this invention is to provide a kind of control method of laser driver, adopt the method for high speed current mirror and high speed current comparator to detect P1 signal, the method that the sampling that Pa signal adopts keeps, determine P1 and Pa by degenerative method, thereby can determine P0 and r
e.
Less important technical problem to be solved by this invention is to provide a kind of circuit that uses said method design.
In order to solve above-mentioned technical problem, the invention provides a kind of two closed loop control methods of laser driver that can be used for burst mode: adopt the method for high speed current mirror and high speed current comparator, detection laser normally luminous, modulated current is that height, transmission data are the first luminous power P1 of 1 o'clock; The method that adopts sampling to keep, the normal average light power Pa when luminous of detection laser;
Two control ends of described high speed current mirror output, the voltage V_Pa_set of and the average light power set forms a negative feedback, is used for controlling the bias current Ibias in the electric current of drive laser, forms the first closed-loop system; Another and the electric current I _ P1_set of the first luminous power P1 setting form a negative feedback, are used for controlling the modulated current Imod in the electric current of drive laser, formation the second closed-loop system; By described the first closed-loop system and the second closed-loop system, can realize the described bias current Ibias of automatic adjusting and modulated current Imod, thereby can obtain stable described the first luminous power P1 and described average light power Pa.
The two closed control circuits of laser driver that can be used for burst mode, mainly comprise:
Photodiode PD, the negative pole of described photodiode PD is connected with input voltage Vdd;
Mirror image laser LD, the positive pole of described mirror image laser LD is connected with the negative pole of described photodiode PD;
The first K switch 1, one end of described the first K switch 1 is connected with the negative pole of described mirror image laser LD, and the other end of described the first K switch 1 is connected with one end of second switch K2; Described the first switch is controlled by enabling control signal BEN;
Second switch K2, described second switch K2 is controlled by data input signal DATA;
High speed current mirror Icurrent_source, one end of described high speed current mirror Icurrent_source is connected with the positive pole of described photodiode PD; The other end ground connection of described high speed current mirror Icurrent_source; The first output of described high speed current mirror Icurrent_source is connected with the first input end of comparison controller comp; The second output of described high speed current mirror Icurrent_source is connected with the first input end of high speed current comparator current comp;
Comparison controller comp, the second input of described comparison controller comp is connected with the voltage V_Pa_set of the average light power of setting; The output of described comparison controller is connected with the grid of the first transistor M1;
The first transistor M1, the source ground of described the first transistor M1, the drain electrode of described the first transistor M1 is connected with the other end of described the first K switch 1;
High speed current comparator current comp, the second input of described high speed current comparator current comp is connected with electric current I _ P1_set of the first luminous power P1 of setting; The output of described high speed current comparator current comp is connected with the input of digital processing and analog-to-digital conversion module DSP & DAC;
Digital processing and analog-to-digital conversion module DSP & DAC, the output of described digital processing and analog-to-digital conversion module DSP & DAC is connected with the grid of transistor seconds M2;
Transistor seconds M2, the source ground of described transistor seconds M2, the drain electrode of described transistor seconds M2 is connected with the other end of described second switch K2;
Described high speed current mirror Icurrent_source mainly comprises:
The 3rd transistor M3, the drain electrode of described the 3rd transistor M3 is connected with the positive pole of described photodiode PD; The grid of described the 3rd transistor M3 is connected with the drain electrode of described the 3rd transistor M3;
The first current source I1, one end of described the first current source I1 is connected with the drain electrode of described the 3rd transistor M3, and the other end of described the first current source I1 is connected with described input voltage Vdd;
The 4th transistor M4, the grid of described the 4th transistor M4 is connected with the positive pole of described photodiode PD; The drain electrode of described the 4th transistor M4 is connected with the source electrode of described the 3rd transistor M3; Described the 4th transistorized source electrode is connected with one end of the second current source I2, the other end ground connection of described the second current source I2;
The 5th transistor M5, the grid of described the 5th transistor M5 is connected with the grid of described the 3rd transistor M3, the positive pole of described photodiode PD; The source electrode of described the 5th transistor M5 is connected with the source electrode of described the 3rd transistor M3; The drain electrode of described the 5th transistor M5 is connected with one end of the 3rd current source I3, and the other end of described the 3rd current source I3 is connected with described input voltage Vdd;
The 6th transistor M6, the grid of described the 6th transistor M6 is connected with the source electrode of described the 4th transistor M4; The source ground of described the 6th transistor M6; The drain electrode of described the 6th transistor M6 is connected with the source electrode of described the 5th transistor M5, one end of the 4th current source I4; The other end of described the 4th current source I4 is connected with described input voltage Vdd;
The 7th transistor M7, the source electrode of described the 7th transistor M7 is connected with described input voltage Vdd; The drain electrode of described the 7th transistor M7 is connected with the drain electrode of described the 5th transistor M5; The grid of described the 7th transistor M7 is connected with the drain electrode of described the 7th transistor M7;
The 8th transistor M8, the grid of described the 8th transistor M8 is connected with the grid of described the 7th transistor M7; The source electrode of described the 8th transistor M8 is connected with described input voltage Vdd;
The 3rd K switch 3, one end of described the 3rd K switch 3 is connected with the drain electrode of described the 8th transistor M8; The other end of described the 3rd switch is connected with one end of the second resistance R 2; The other end of described the second resistance R 2 is connected with the first input end of described comparison controller comp; Described the 3rd K switch 3 is controlled by the described control signal BEN that enables;
The first resistance R 1, one end of described the first resistance R 1 is connected with the drain electrode of described the 8th transistor M8; The other end ground connection of the first resistance R 1.
The first capacitor C 1, one end of described the first capacitor C 1 is connected with the other end of described the second resistance R 2; The other end ground connection of described the first capacitor C 1;
The 9th transistor M9, the grid of described the 9th transistor M9 is connected with the positive pole of described photodiode PD; The source electrode of described the 9th transistor M9 is connected with the source electrode of described the 5th transistor M5; The drain electrode of described the 9th transistor M9 is connected with one end of the 5th current source I5, the first input end of described high speed current comparator current comp; The other end of described the 5th current source I5 is connected with described input voltage Vdd.
As preferably: the concrete structure of described digital processing and analog-to-digital conversion module DSP & DAC is:
D-latch, described D-latch is controlled by the described control signal BEN that enables; Described D-latch is connected with described input voltage Vdd; The input end of clock of described D-latch is connected with the output of described high speed current comparator current comp;
NOR-operation device NOR, the first input end of described NOR-operation device NOR is connected with the output of described D-latch; The second input of described NOR-operation device is connected with the output of described high speed current comparator current comp;
8 calculator counter, described 8 calculator counter are controlled by the described control signal BEN that enables; The input of described 8 calculators is connected with the output of described NOR-operation device NOR; The input end of clock of described 8 calculators is connected with clock signal clk;
8 DAC, the input of described 8 DAC is connected with the output of described 8 calculator counter.The output of described 8 DAC is connected with the grid of described transistor seconds M2.
Compared to prior art, the present invention possesses following beneficial effect:
1. the control mode of the two closed loops of pair optical communication laser, compares the control mode of single closed loop or the control mode of two open loops, has saved the trouble of doing temperature look-up table, can greatly enhance productivity.
2. the control mode of the two closed loops of pair optical communication laser, compare the control mode of single closed loop or the control mode of two open loops, owing to having adopted the mode of automated closed-loop control, avoid the inaccurate problem of temperature look-up table of bringing due to laser ageing, can in longer life time, accurately control average light power and the extinction ratio of laser.
Accompanying drawing explanation
Fig. 1 is preferred embodiment of the present invention integrated circuit figure;
Fig. 2 is preferred embodiment of the present invention current mirror partial circuit figure;
Fig. 3 is preferred embodiment of the present invention DSP & DAC partial circuit figure;
Embodiment
Below the present invention will be further described in conjunction with the accompanying drawings and embodiments.
The two closed control circuits of laser driver that can be used for burst mode, is characterized in that: mainly comprise:
Photodiode PD, the negative pole of described photodiode PD is connected with input voltage Vdd;
Mirror image laser LD, the positive pole of described mirror image laser LD is connected with the negative pole of described photodiode PD;
The first K switch 1, one end of described the first K switch 1 is connected with the negative pole of described mirror image laser LD, and the other end of described the first K switch 1 is connected with one end of second switch K2; Described the first switch is controlled by enabling control signal BEN;
Second switch K2, described second switch K2 is controlled by data input signal DATA;
High speed current mirror Icurrent_source, one end of described high speed current mirror Icurrent_source is connected with the positive pole of described photodiode PD; The other end ground connection of described high speed current mirror Icurrent_source; The first output of described high speed current mirror Icurrent_source is connected with the first input end of comparison controller comp; The second output of described high speed current mirror Icurrent_source is connected with the first input end of high speed current comparator current comp;
Comparison controller comp, the second input of described comparison controller comp is connected with the voltage V_Pa_set of the average light power of setting; The output of described comparison controller is connected with the grid of the first transistor M1;
The first transistor M1, the source ground of described the first transistor M1, the drain electrode of described the first transistor M1 is connected with the other end of described the first K switch 1;
High speed current comparator current comp, the second input of described high speed current comparator current comp is connected with electric current I _ P1_set of the first luminous power P1 of setting; The output of described high speed current comparator current comp is connected with the input of digital processing and analog-to-digital conversion module DSP & DAC;
Digital processing and analog-to-digital conversion module DSP & DAC, the output of described DSP & DAC is connected with the grid of transistor seconds M2;
Transistor seconds M2, the source ground of described transistor seconds M2, the drain electrode of described transistor seconds M2 is connected with the other end of described second switch K2;
Described high speed current mirror Icurrent_source mainly comprises:
The 3rd transistor M3, the drain electrode of described the 3rd transistor M3 is connected with the positive pole of described photodiode PD; The grid of described the 3rd transistor M3 is connected with the drain electrode of described the 3rd transistor M3;
The first current source I1, one end of described the first current source I1 is connected with the drain electrode of described the 3rd transistor M3, and the other end of described the first current source I1 is connected with described input voltage Vdd;
The 4th transistor M4, the grid of described the 4th transistor M4 is connected with the positive pole of described photodiode PD; The drain electrode of described the 4th transistor M4 is connected with the source electrode of described the 3rd transistor M3; Described the 4th transistorized source electrode is connected with one end of the second current source I2, the other end ground connection of described the second current source I2;
The 5th transistor M5, the grid of described the 5th transistor M5 is connected with the grid of described the 3rd transistor M3, the positive pole of described photodiode PD; The source electrode of described the 5th transistor M5 is connected with the source electrode of described the 3rd transistor M3; The drain electrode of described the 5th transistor M5 is connected with one end of the 3rd current source I3, and the other end of described the 3rd current source I3 is connected with described input voltage Vdd;
The 6th transistor M6, the grid of described the 6th transistor M6 is connected with the source electrode of described the 4th transistor M4; The source ground of described the 6th transistor M6; The drain electrode of described the 6th transistor M6 is connected with the source electrode of described the 5th transistor M5, one end of the 4th current source I4; The other end of described the 4th current source I4 is connected with described input voltage Vdd;
The 7th transistor M7, the source electrode of described the 7th transistor M7 is connected with described input voltage Vdd; The drain electrode of described the 7th transistor M7 is connected with the drain electrode of described the 5th transistor M5; The grid of described the 7th transistor M7 is connected with the drain electrode of described the 7th transistor M7;
The 8th transistor M8, the grid of described the 8th transistor M8 is connected with the grid of described the 7th transistor M7; The source electrode of described the 8th transistor M8 is connected with described input voltage Vdd;
The 3rd K switch 3, one end of described the 3rd K switch 3 is connected with the drain electrode of described the 8th transistor M8; The other end of described the 3rd switch is connected with one end of the second resistance R 2; The other end of described the second resistance R 2 is connected with the first input end of described comparison controller comp; Described the 3rd K switch 3 is controlled by the described control signal BEN that enables;
The first resistance R 1, one end of described the first resistance R 1 is connected with the drain electrode of described the 8th transistor M8; The other end ground connection of described the first resistance R 1.
The first capacitor C 1, one end of described the first capacitor C 1 is connected with the other end of described the second resistance R 2; The other end ground connection of described the first capacitor C 1;
The 9th transistor M9, the grid of described the 9th transistor M9 is connected with the positive pole of described photodiode PD; The source electrode of described the 9th transistor M9 is connected with the source electrode of described the 5th transistor M5; The drain electrode of described the 9th transistor M9 is connected with one end of the 5th current source I5, the first input end of described high speed current comparator current comp; The other end of described the 5th current source I5 is connected with described input voltage Vdd.
Described the 3rd transistor M3, the 4th transistor M4 have formed a voltage negative feedback arrangement, in the time that the cathode voltage Vpd of described photodiode PD raises, described the 4th transistor M4 is a sign-changing amplifier part, and the drain voltage V1 of described the 4th transistor M4 is reduced; In the time that the drain voltage V1 of described the 4th transistor M4 reduces, the diode connection of described the 3rd transistor M3 can drag down the cathode voltage Vpd of described photodiode PD, thereby makes the cathode voltage Vpd of described photodiode PD in a stable value; Make electric current not need the parasitic capacitance of this point to discharge and recharge, thereby can make the image current structure of described the 3rd transistor M3, the 5th transistor M5, the 9th transistor M9 reach the bandwidth of hundreds of MHZ, the electric current that flows through described the 3rd transistor M3 is intactly mirrored to described the 5th transistor M5, the 9th transistor M9.
In the system of a burst, the luminous of laser controlled by the described control signal BEN that enables, the image current of described the 5th transistor M4 after the mirror image circuit of described the 8th transistor M8 and the 7th transistor M7, keeps and filter circuit through a sampling again, obtains a voltage V_Pa..Described sampling hold circuit be also by described be can control signal BEN control.Described voltage V_Pa has reflected the filtered average current of described photodiode PD, will be used for controlling the setting of average light power Pa.
The high speed electric current that described the 9th transistor M9 obtains, and the electric current I of the first luminous power P1 of described setting _ P1_set flows into a high speed current comparator current comp.When the current ratio of described the 9th transistor M9 is stated electric current I _ P1_set hour of the first luminous power P1 of setting, a low level P1_det of described high speed current comparator current comp output, when the current ratio of described the 9th transistor M9 is stated the electric current I _ P1_set of the first luminous power P1 of setting when large, a high level P1_det of described high speed current comparator current comp output.
With further reference to Fig. 3, the concrete structure of described digital processing and analog-to-digital conversion module DSP & DAC is:
D-latch, described D-latch is controlled by the described control signal BEN that enables; Described D-latch is connected with described input voltage Vdd; The input end of clock of described D-latch is connected with the output of described high speed current comparator current comp;
NOR-operation device NOR, the first input end of described NOR-operation device NOR is connected with the output of described D-latch; The second input of described NOR-operation device is connected with the output of described high speed current comparator current comp;
8 calculator counter, described 8 calculator counter are controlled by the described control signal BEN that enables; The input of described 8 calculators is connected with the output of described NOR-operation device NOR; The input end of clock of described 8 calculators is connected with clock signal clk;
8 DAC, the input of described 8 DAC is connected with the output of described 8 calculator counter.The output of described 8 DAC is connected with the grid of described transistor seconds M2.
Described D-latch is in the time that the rising edge of each clock signal clk arrives, and Reset end provides a load pulse signal, described D-latch is resetted, output low level.In the time that described high level P1_det arrives, described D-latch output high level.The output of described D-latch and described P1_det electric current carry out NOR-operation and control described 8 calculators, and output high level hour counter adds 1, and output low level hour counter subtracts 1.Thereby make described 8 DAC control described modulation Imod electric current output, when high level, output current reduces, and when low level, output current increases.
The above, be only preferred embodiment of the present invention, not technical scope of the present invention imposed any restrictions, therefore any trickle modification that every foundation technical spirit of the present invention is done above example, equivalent variations and modification, all still belong in the scope of technical solution of the present invention.
Claims (3)
1. the two closed loop control methods of laser driver that can be used for burst mode, is characterized in that: adopt the method for high speed current mirror and high speed current comparator, detection laser normally luminous, modulated current is that height, transmission data are the first luminous power P1 of 1 o'clock; The method that adopts sampling to keep, the normal average light power Pa when luminous of detection laser;
Two control ends of described high speed current mirror output, the voltage V_Pa_set of and the average light power set forms a negative feedback, is used for controlling the bias current Ibias in the electric current of drive laser, forms the first closed-loop system; Another and the electric current I _ P1_set of the first luminous power P1 setting form a negative feedback, are used for controlling the modulated current Imod in the electric current of drive laser, formation the second closed-loop system; By described the first closed-loop system and the second closed-loop system, can realize the described bias current Ibias of automatic adjusting and modulated current Imod, thereby can obtain stable described the first luminous power P1 and described average light power Pa.
2. the two closed control circuits of laser driver that can be used for burst mode, is characterized in that: mainly comprise:
Photodiode PD, the negative pole of described photodiode PD is connected with input voltage Vdd;
Mirror image laser LD, the positive pole of described mirror image laser LD is connected with the negative pole of described photodiode PD;
The first K switch 1, one end of described the first K switch 1 is connected with the negative pole of described mirror image laser LD, and the other end of described the first K switch 1 is connected with one end of second switch K2; Described the first switch is controlled by enabling control signal BEN;
Second switch K2, described second switch K2 is controlled by data input signal DATA;
High speed current mirror Icurrent_source, one end of described high speed current mirror Icurrent_source is connected with the positive pole of described photodiode PD; The other end ground connection of described high speed current mirror Icurrent_source; The first output of described high speed current mirror Icurrent_source is connected with the first input end of comparison controller comp; The second output of described high speed current mirror Icurrent_source is connected with the first input end of high speed current comparator current comp;
Comparison controller comp, the second input of described comparison controller comp is connected with the voltage V_Pa_set of the average light power of setting; The output of described comparison controller is connected with the grid of the first transistor M1;
The first transistor M1, the source ground of described the first transistor M1, the drain electrode of described the first transistor M1 is connected with the other end of described the first K switch 1;
High speed current comparator current comp, the second input of described high speed current comparator current comp is connected with electric current I _ P1_set of the first luminous power P1 of setting; The output of described high speed current comparator current comp is connected with the input of DSP & DAC module;
Digital processing and analog-to-digital conversion module DSP & DAC, the output of described digital processing and analog-to-digital conversion module DSP & DAC is connected with the grid of transistor seconds M2;
Transistor seconds M2, the source ground of described transistor seconds M2, the drain electrode of described transistor seconds M2 is connected with the other end of described second switch K2;
Described high speed current mirror Icurrent_source mainly comprises:
The 3rd transistor M3, the drain electrode of described the 3rd transistor M3 is connected with the positive pole of described photodiode PD; The grid of described the 3rd transistor M3 is connected with the drain electrode of described the 3rd transistor M3;
The first current source I1, one end of described the first current source I1 is connected with the drain electrode of described the 3rd transistor M3, and the other end of described the first current source I1 is connected with described input voltage Vdd;
The 4th transistor M4, the grid of described the 4th transistor M4 is connected with the positive pole of described photodiode PD; The drain electrode of described the 4th transistor M4 is connected with the source electrode of described the 3rd transistor M3; Described the 4th transistorized source electrode is connected with one end of the second current source I2, the other end ground connection of described the second current source I2;
The 5th transistor M5, the grid of described the 5th transistor M5 is connected with the grid of described the 3rd transistor M3, the positive pole of described photodiode PD; The source electrode of described the 5th transistor M5 is connected with the source electrode of described the 3rd transistor M3; The drain electrode of described the 5th transistor M5 is connected with one end of the 3rd current source I3, and the other end of described the 3rd current source I3 is connected with described input voltage Vdd;
The 6th transistor M6, the grid of described the 6th transistor M6 is connected with the source electrode of described the 4th transistor M4; The source ground of described the 6th transistor M6; The drain electrode of described the 6th transistor M6 is connected with the source electrode of described the 5th transistor M5, one end of the 4th current source I4; The other end of described the 4th current source I4 is connected with described input voltage Vdd;
The 7th transistor M7, the source electrode of described the 7th transistor M7 is connected with described input voltage Vdd; The drain electrode of described the 7th transistor M7 is connected with the drain electrode of described the 5th transistor M5; The grid of described the 7th transistor M7 is connected with the drain electrode of described the 7th transistor M7;
The 8th transistor M8, the grid of described the 8th transistor M8 is connected with the grid of described the 7th transistor M7; The source electrode of described the 8th transistor M8 is connected with described input voltage Vdd;
The 3rd K switch 3, one end of described the 3rd K switch 3 is connected with the drain electrode of described the 8th transistor M8; The other end of described the 3rd switch is connected with one end of the second resistance R 2; The other end of described the second resistance R 2 is connected with the first input end of described comparison controller comp; Described the 3rd K switch 3 is controlled by the described control signal BEN that enables;
The first resistance R 1, one end of described the first resistance R 1 is connected with the drain electrode of described the 8th transistor M8; The other end ground connection of the first resistance R 1.
The first capacitor C 1, one end of described the first capacitor C 1 is connected with the other end of described the second resistance R 2; The other end ground connection of described the first capacitor C 1;
The 9th transistor M9, the grid of described the 9th transistor M9 is connected with the positive pole of described photodiode PD; The source electrode of described the 9th transistor M9 is connected with the source electrode of described the 5th transistor M5; The drain electrode of described the 9th transistor M9 is connected with one end of the 5th current source I5, the first input end of described high speed current comparator current comp; The other end of described the 5th current source I5 is connected with described input voltage Vdd.
3. a kind of two closed control circuits of laser driver that can be used for burst mode according to claim 2, is characterized in that: the concrete structure of described digital processing and analog-to-digital conversion module DSP & DAC is:
D-latch, described D-latch is controlled by the described control signal BEN that enables; Described D-latch is connected with described input voltage Vdd; The input end of clock of described D-latch is connected with the output of described high speed current comparator current comp;
NOR-operation device NOR, the first input end of described NOR-operation device NOR is connected with the output of described D-latch; The second input of described NOR-operation device is connected with the output of described high speed current comparator current comp;
8 calculator counter, described 8 calculator counter are controlled by the described control signal BEN that enables; The input of described 8 calculators is connected with the output of described NOR-operation device NOR; The input end of clock of described 8 calculators is connected with clock signal clk;
8 DAC, the input of described 8 DAC is connected with the output of described 8 calculator counter.The output of described 8 DAC is connected with the grid of described transistor seconds M2.
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| CN106155688A (en) * | 2016-07-05 | 2016-11-23 | 江苏奥雷光电有限公司 | A kind of linear deflection algorithm with lower limit being applicable to optical module production |
| CN106340805A (en) * | 2016-07-18 | 2017-01-18 | 厦门优迅高速芯片有限公司 | Double-closed loop control circuit of laser driver |
| CN110890921A (en) * | 2018-09-07 | 2020-03-17 | 瑞昱半导体股份有限公司 | Laser diode control circuit with rectifier in feedback control loop |
| CN115435897A (en) * | 2022-07-14 | 2022-12-06 | 厦门优迅高速芯片有限公司 | Optical module double-closed-loop verification data processing method and related equipment |
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| CN106155688A (en) * | 2016-07-05 | 2016-11-23 | 江苏奥雷光电有限公司 | A kind of linear deflection algorithm with lower limit being applicable to optical module production |
| CN106340805A (en) * | 2016-07-18 | 2017-01-18 | 厦门优迅高速芯片有限公司 | Double-closed loop control circuit of laser driver |
| CN106340805B (en) * | 2016-07-18 | 2023-08-29 | 厦门优迅高速芯片有限公司 | Double closed-loop control circuit of laser driver |
| CN110890921A (en) * | 2018-09-07 | 2020-03-17 | 瑞昱半导体股份有限公司 | Laser diode control circuit with rectifier in feedback control loop |
| CN110890921B (en) * | 2018-09-07 | 2021-04-27 | 瑞昱半导体股份有限公司 | Laser diode control circuit with rectifier in feedback control loop |
| CN115435897A (en) * | 2022-07-14 | 2022-12-06 | 厦门优迅高速芯片有限公司 | Optical module double-closed-loop verification data processing method and related equipment |
| CN115435897B (en) * | 2022-07-14 | 2024-01-09 | 厦门优迅高速芯片有限公司 | Optical module double closed loop verification data processing method and related equipment |
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