CN103903981A - Deep trench annealing method - Google Patents
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- CN103903981A CN103903981A CN201410161259.4A CN201410161259A CN103903981A CN 103903981 A CN103903981 A CN 103903981A CN 201410161259 A CN201410161259 A CN 201410161259A CN 103903981 A CN103903981 A CN 103903981A
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- 238000000034 method Methods 0.000 title claims abstract description 104
- 238000000137 annealing Methods 0.000 title claims abstract description 63
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 54
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 52
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 50
- 239000010703 silicon Substances 0.000 claims abstract description 50
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 41
- 239000001301 oxygen Substances 0.000 claims abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000011261 inert gas Substances 0.000 claims abstract description 22
- 239000007789 gas Substances 0.000 claims abstract description 20
- 229910001873 dinitrogen Inorganic materials 0.000 claims abstract description 12
- 230000005516 deep trap Effects 0.000 claims description 42
- 229910052757 nitrogen Inorganic materials 0.000 claims description 20
- 238000006243 chemical reaction Methods 0.000 claims description 16
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 9
- 239000003595 mist Substances 0.000 claims description 9
- 229910052786 argon Inorganic materials 0.000 claims description 6
- 230000035484 reaction time Effects 0.000 claims description 5
- 238000010884 ion-beam technique Methods 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 36
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 16
- 239000002245 particle Substances 0.000 abstract description 9
- 239000000377 silicon dioxide Substances 0.000 abstract description 7
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 3
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 229910052814 silicon oxide Inorganic materials 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 239000010409 thin film Substances 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 229910003978 SiClx Inorganic materials 0.000 description 5
- 238000005468 ion implantation Methods 0.000 description 4
- 239000012528 membrane Substances 0.000 description 3
- 238000002389 environmental scanning electron microscopy Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229940090044 injection Drugs 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 101100373011 Drosophila melanogaster wapl gene Proteins 0.000 description 1
- 206010024769 Local reaction Diseases 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 210000004483 pasc Anatomy 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- -1 under hot conditions Chemical compound 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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Abstract
The invention provides a deep trench annealing method. According to the method, annealing is conducted to the active region of a silicon substrate through replenishing a process cavity with less oxygen and a lot of inert gas such as mixed gas of the oxygen and pure nitrogen gas, the problem that the Si3N4 particle defect is prone to forming at the lattice damage position of the silicon substrate due to the fact that the pure nitrogen gas is used as the reactive gas in a traditional deep trench thermal annealing process is solved, and the lattice damage defect of the silicon substrate caused by the deep trench process is eliminated; the active region defect caused by the gaseous silicon oxide formed in the traditional deep trench thermal annealing process is also eliminated; in addition, the less oxygen is added to help generate a SiO2 thin film on the surface of the silicon substrate to release some stress, and the degree of warping of the silicon substrate in the thermal processing process is reduced, so that the defect of the active region can be eliminated and yield of products can be improved by the adoption of the deep trench annealing method.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of deep trap method for annealing for active area.
Background technology
In cmos semiconductor device manufacturing process, the region of doing active device on silicon substrate is called active area, that is to say some well region, adopts the isolation technologies such as STI, the region keeping apart.Active area is mainly for MOS circuit, and different doping can form N or P type active area.
Take P type active area as example, refer to Fig. 1-3.Fig. 1 is the structural representation of the reaction chamber that adopts of traditional deep trap thermal anneal process, wherein arrow represents gas flow, the silicon substrate cross section structure schematic diagram that Fig. 2 adopts for traditional dark N trap ion implantation technology, Fig. 3 is corresponding silicon substrate cross section structure schematic diagram after traditional dark N trap ion implantation technology completes.In Fig. 2,1 represents dark N trap, and arrow represents to inject ion direction.In Fig. 3,1 represents dark N trap, and 2 represent P type trap.In order to isolate P type trap and silicon substrate, suppress the electric leakage of part P type trap and prevent the impact of silicon substrate noise on device, dark N-type trap technique is introduced into into, namely forms a darker N-type trap in the peripheral more depths of P type trap by the doping of superenergy, is called dark N-type trap.Because dark N-type trap technique needs high-octane Implantation, can form many especially lattice damages in P type active area.In like manner, also there is identical problem for N-type active area.
In order to eliminate these lattice damages and to activate the element of well region doping, conventionally, after dry method and wet method are removed photoresist, can carry out immediately deep trap annealing process, refer to Fig. 4, Fig. 4 is the cross section structure schematic diagram of the traditional corresponding silicon substrate of dark N trap annealing process.Traditional deep trap annealing process is pure nitrogen gas rapid thermal annealing or pure nitrogen gas boiler tube thermal annealing.Through after follow-up a series of technical process, after double grid (Dual Gate) etching, can produce some damage defects in active area.
If this is owing to only having nitrogen in traditional deep trap annealing process, and deep trap annealing process is necessary for high-temperature technology, because the local crystal orientation of lattice damage is various, so the density of Si atom also vary, like this at the larger local N of Si atomic density
2just easily generate Si in the local reaction that has damage with Si
3n
4, become particle shape defect, be attached to the surface of substrate, and easy-clear not.In subsequent technique, just grow and do not become continuous film where in this defect, finally after double grid etching, see this defect being exaggerated, the i.e. damage defect of said active area.Refer to Fig. 5 and Fig. 6, Fig. 5 is the cross section structure schematic diagram of the silicon substrate of grid structure after etched after traditional deep trap annealing process, and Fig. 6 is Si
3n
4the ESEM picture of the pattern with damage defect that particle defects forms in successive process, in Fig. 6, represents defect area in dotted line frame, can see at defect area and not form continuous film.In Fig. 5, the black macular area in the active area forming is damage defect, and the black spots district is here positioned at surfaces of active regions, and the oxide-film that is positioned at top, black macular area forms depression.
In tradition deep trap annealing process, under hot conditions, Si
3n
4granuloplastic reaction equation is:
On the other hand, under hot conditions, the SiO of Si and silicon substrate itself
2also can react and generate the silica of gaseous state, cause the defect of active area.Reaction equation is as follows:
In addition,, because deep trap technique intermediate ion injection process inevitably can produce stress in silicon substrate, in high-temperature thermal annealing process, these stress will cause silicon substrate generation warpage.
Tradition deep trap annealing process causes the defect of above-mentioned active area by directly having influence on the service behaviour of device, even causes device cisco unity malfunction.Along with device size further dwindles, the defect of active area is more and more obvious on the impact of yield.Therefore, be badly in need of improving existing deep trap annealing process, thereby reduce the defect of active area, improve the performance of device.
Summary of the invention
In order to overcome the problems referred to above, the present invention aims to provide a kind of deep trap method for annealing for active area, thereby reduces the defect of active area, improves device performance.
The invention provides a kind of deep trap method for annealing, comprise in process cavity and pass into reacting gas and heating silicon substrate, described in it, reacting gas is made up of oxygen and inert gas, and wherein, the ratio of described oxygen and described inert gas is not more than 20%.
Preferably, the ratio of described oxygen and described inert gas is not more than 13%.
Preferably, the flow of described oxygen is 1-2.6SLM.
Preferably, described inert gas is pure nitrogen gas.
Preferably, described inert gas is the mist of nitrogen and argon gas.
Preferably, the heating rate adopting is 75-220 ℃/sec.
Preferably, the reaction temperature adopting is 1000-1200 ℃.
Preferably, the reaction time adopting is 5-60sec.
Preferably, described process cavity is rapid thermal anneal process chamber or boiler tube annealing process chamber.
Preferably, adopting described rapid thermal anneal process chamber to carry out described deep trap method for annealing comprises: adopt pulse laser short annealing, ion beam short annealing, continuous wave laser short annealing or incoherent wideband light source short annealing.
Deep trap method for annealing of the present invention, by a small amount of oxygen and a large amount of inert gas are carried out to annealing in process such as the mist of pure nitrogen gas or nitrogen and argon gas passes into process cavity to silicon substrate, solve in traditional deep trap thermal anneal process and easily formed Si as reacting gas at the lattice damage place of silicon substrate with pure nitrogen gas
3n
4the problem of particle defects, thus the lattice damage that silicon substrate causes due to deep trap technique eliminated; Meanwhile, a small amount of oxygen can suppress silicon substrate and silicon dioxide forms the reaction of gaseous oxygen SiClx, forms thereby eliminated the active area defect that gaseous oxygen SiClx causes in traditional deep trap thermal anneal process; In addition, can also make surface of silicon generate SiO adding of a small amount of oxygen
2film and discharge some stress, thus effectively reduce the degree of silicon substrate warpage in heat treatment, thus, adopt deep trap method for annealing of the present invention, can eliminate the defect of active area, improve product yield.
Accompanying drawing explanation
Fig. 1 is the structural representation of the reaction chamber that adopts of traditional deep trap thermal anneal process, and wherein arrow represents gas flow
The silicon substrate cross section structure schematic diagram that Fig. 2 adopts for traditional dark N trap ion implantation technology
Fig. 3 is corresponding silicon substrate cross section structure schematic diagram after traditional dark N trap ion implantation technology completes
Fig. 4 is the cross section structure schematic diagram of the traditional corresponding silicon substrate of dark N trap annealing process
Fig. 5 is the structural representation of the silicon substrate of double-gate structure after etched after traditional deep trap annealing process
Fig. 6 is Si
3n
4the ESEM picture of the pattern with damage defect that particle defects forms in successive process
Fig. 7 is the schematic flow sheet of the deep trap method for annealing of a preferred embodiment of the present invention
Embodiment
For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art is also encompassed in protection scope of the present invention.
As previously mentioned, in traditional deep trap annealing process, adopt pure nitrogen gas, under hot conditions, silicon substrate is carried out to annealing in process, the position reaction of the lattice damage easily forming in silicon substrate generates Si
3n
4, become particle shape defect, be attached to the surface of substrate, and easy-clear not.In subsequent technique, just grow and do not become continuous film where in this defect, thereby cause the damage defect of active area; And in hot environment, the silicon dioxide in silicon atom and silicon substrate easily forms gaseous oxygen SiClx, thereby further cause active area defect.Therefore, the present invention improves traditional deep trap annealing process, change using original employing pure nitrogen gas as reacting gas as the mist of a small amount of oxygen and a large amount of inert gases into, such as, can adopt the mist of oxygen and nitrogen, can also adopt the mist of oxygen, nitrogen and other inert gases, such as oxygen, nitrogen and argon gas etc.
Traditional deep trap annealing process adopts rapid thermal anneal process or boiler tube thermal anneal process in its corresponding process cavity, to carry out respectively, deep trap method for annealing of the present invention can also carry out in the process cavity of traditional deep trap annealing process, such as carrying out in rapid thermal anneal process chamber or in boiler tube thermal anneal process chamber.
In a preferred embodiment of the present invention, in boiler tube thermal anneal process chamber, carry out, because of the boiler tube thermal annealing time longer, can eliminate more completely lattice damage defect, thereby reduce active area defect.
In another preferred embodiment of the present invention, the deep trap method for annealing that adopts rapid thermal anneal process chamber to carry out comprises: adopt pulse laser short annealing, ion beam short annealing, continuous wave laser short annealing or incoherent wideband light source short annealing.
Certainly,, for coordinating the present invention to adopt the mist of oxygen and inert gas, the process cavity adopting can have multiple air inlet pipelines, is used for connecting different gas; Process cavity itself also can have an air inlet pipeline, passes into this air inlet pipeline medium after gas with various is mixed, and the present invention is not restricted this.
Below in conjunction with specific embodiments and the drawings 6, deep trap method for annealing of the present invention is described in further detail.Fig. 6 is the schematic flow sheet of the deep trap method for annealing of a preferred embodiment of the present invention.
Refer to Fig. 6, the deep trap method for annealing of a preferred embodiment of the present invention, comprising: in process cavity, pass into reacting gas and heating silicon substrate; In the present invention, reacting gas is made up of oxygen and inert gas.In the present embodiment, the inert gas of employing is pure nitrogen gas.In another preferred embodiment of the present invention, the inert gas of employing can be the mist of nitrogen and argon gas.Certainly,, in the present invention, the inert gas of employing can also be nitrogen, argon gas and other inert gas.
Concrete, in the present embodiment, adopting boiler tube thermal anneal process chamber, deep trap method for annealing comprises the following steps:
Step S01: after silicon substrate is carried out to deep trap technique, pass into oxygen and nitrogen in process cavity;
Here, those of ordinary skill in the art can learn the detailed process of silicon substrate being carried out to deep trap technique, repeats no more here; Before passing into oxygen and nitrogen, also can comprise and the processing step of guaranteeing deep trap annealing process atmosphere such as vacuumize, this also, for those of ordinary skills can know, here repeats no more; In the present invention, the ratio of oxygen and inert gas is not more than 20%, and in the present embodiment, the ratio of oxygen and inert gas is not more than 13%.This is also the definition of the present invention to a small amount of oxygen, and oxygen is too much unsuitable, otherwise the requirement that can run counter to deep trap annealing process, in the quality that a large amount of silicon substrate oxidations is reduced to silicon substrate and the device that forms.Due to the mist of the present embodiment employing oxygen and nitrogen, therefore, the ratio of oxygen and nitrogen is not more than 13%.
It should be noted that, why in nitrogen, add a small amount of oxygen, because the reaction temperature of nitrogen and silicon is high, the reaction temperature of oxygen and silicon is low, so, the silicon atom that injects the lattice damage place causing due to aforementioned deep trap technique intermediate ion under the same conditions will be preferentially and the oxygen generation silica membrane that reacts, and concrete reaction equation is:
thereby stop nitrogen and pasc reaction to generate Si3N4 particle defects, 3Si+2N
2≠ Si
3n
4(particle); The silica membrane generating can also discharge the stress of surface of silicon, reduces the problem of the warpage of silicon substrate in thermal annealing process; In addition, the existence of a small amount of oxygen, has also stoped the active area defect of silicon and silicon dioxde reaction generation gaseous oxygen SiClx, Si+SiO
2≠ 2SiO(gaseous state).
In the present embodiment, the flow of oxygen is 1-2.6SLM, is preferably 2.6SLM, can go out according to the ratio-dependent of the oxygen in the present embodiment and nitrogen the flow of nitrogen, repeats no more here.
Step S02: silicon chip is heated to certain reaction temperature with certain heating rate;
Here, concrete, the heating rate that the present embodiment adopts is 75-220 ℃/sec, is preferably 75 ℃/sec; The reaction temperature that the present embodiment adopts is 1000-1200 ° ℃ and is preferably 1050 ℃.
Step S03: the reaction time certain to silicon substrate continuous heating;
Here, concrete, the reaction time that the present embodiment adopts is 5-60sec, is preferably 20sec.
Step S04: reaching after the reaction time, powered-down, makes silicon substrate naturally cool to room temperature.
In sum, of the present invention deep trap method for annealing is carried out in active area, improve the process that traditional deep trap annealing process adopts pure nitrogen gas at high temperature silicon substrate to be heat-treated, in thermal annealing process, introduce a small amount of oxygen, utilize oxygen and silicon can react at a lower temperature and generate the principle of silicon dioxide, effectively suppressed to react with nitrogen and generate Si at lattice damage place silicon atom
3n
4particle defects, thus the follow-up problem that can not form continuous film avoided, eliminate the damage defect of active area; Also effectively eliminate the active area defect that silicon and silicon dioxde reaction generate gaseous oxygen SiClx; In eliminating active area defect, the silica membrane generating at lattice damage place can discharge the stress at this place to a certain extent, thereby effectively avoids the problem of the warpage that silicon substrate produces in thermal annealing process.
Although the present invention discloses as above with preferred embodiment; right described embodiment only gives an example for convenience of explanation; not in order to limit the present invention; those skilled in the art can do some changes and retouching without departing from the spirit and scope of the present invention, and the protection range that the present invention advocates should be as the criterion with described in claims.
Claims (10)
1. a deep trap method for annealing, comprises in process cavity and passes into reacting gas and heating silicon substrate, it is characterized in that, described reacting gas is made up of oxygen and inert gas, and wherein, the ratio of described oxygen and described inert gas is not more than 20%.
2. method according to claim 1, is characterized in that, the ratio of described oxygen and described inert gas is not more than 13%.
3. method according to claim 1, is characterized in that, the flow of described oxygen is 1-2.6SLM.
4. method according to claim 1, is characterized in that, described inert gas is pure nitrogen gas.
5. method according to claim 1, is characterized in that, described inert gas is the mist of nitrogen and argon gas.
6. method according to claim 1, is characterized in that, the heating rate adopting is 75-220 ℃/sec.
7. method according to claim 1, is characterized in that, the reaction temperature adopting is 1000-1200 ℃.
8. method according to claim 1, is characterized in that, the reaction time adopting is 5-60sec.
9. method according to claim 1, is characterized in that, described process cavity is rapid thermal anneal process chamber or boiler tube annealing process chamber.
10. method according to claim 9, it is characterized in that, adopt described rapid thermal anneal process chamber to carry out described deep trap method for annealing and comprise: adopt pulse laser short annealing, ion beam short annealing, continuous wave laser short annealing or incoherent wideband light source short annealing.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5015593A (en) * | 1989-05-15 | 1991-05-14 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
| EP0924751A2 (en) * | 1997-12-18 | 1999-06-23 | Texas Instruments Inc. | Well diffusion |
| US6268298B1 (en) * | 1998-03-10 | 2001-07-31 | Denso Corporation | Method of manufacturing semiconductor device |
| US6806138B1 (en) * | 2004-01-21 | 2004-10-19 | International Business Machines Corporation | Integration scheme for enhancing capacitance of trench capacitors |
| CN1317746C (en) * | 2002-07-16 | 2007-05-23 | 海力士半导体有限公司 | Method for mfg. semiconductor chip |
| US20080176384A1 (en) * | 2007-01-18 | 2008-07-24 | Kyung-Seok Ko | Methods of forming impurity regions in semiconductor devices |
-
2014
- 2014-04-22 CN CN201410161259.4A patent/CN103903981A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5015593A (en) * | 1989-05-15 | 1991-05-14 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
| EP0924751A2 (en) * | 1997-12-18 | 1999-06-23 | Texas Instruments Inc. | Well diffusion |
| US6268298B1 (en) * | 1998-03-10 | 2001-07-31 | Denso Corporation | Method of manufacturing semiconductor device |
| CN1317746C (en) * | 2002-07-16 | 2007-05-23 | 海力士半导体有限公司 | Method for mfg. semiconductor chip |
| US6806138B1 (en) * | 2004-01-21 | 2004-10-19 | International Business Machines Corporation | Integration scheme for enhancing capacitance of trench capacitors |
| US20080176384A1 (en) * | 2007-01-18 | 2008-07-24 | Kyung-Seok Ko | Methods of forming impurity regions in semiconductor devices |
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