CN103903646B - A kind of low two-port SRAM writing power consumption - Google Patents
A kind of low two-port SRAM writing power consumption Download PDFInfo
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Abstract
The present invention provides a kind of low two-port SRAM writing power consumption, writes anticipation comparator and the previous cycle is write data and currently writes data and compare, if it is different, then be set to effectively by write bit line equalizing signal, the most invalid；When occurring that continuous print writes " 0 " or one writing operation, owing to the data kept on bit line are identical with needing the data write, writing anticipation comparator and be set to by write bit line equalizing signal invalid, therefore bit line does not overturns；When the double data difference write, writing anticipation comparator, to put write bit line equalizing signal effective, electric charge on write bit line and write bit line are anti-is redistributed, write bit line and write bit line are instead equalized to intermediate level, then write bit line equalizing signal is invalid, writing enable effectively, write driver is by level anti-driven to new to bit line and bit line.The present invention is compared with traditional two-port SRAM based on write bit line balancing technique, when writing Data flipping rate and being 50%, and write bit line upset lower power consumption 50%.
Description
[technical field]
The present invention relates to SRAM field, particularly to a kind of low two-port SRAM writing power consumption.
[background technology]
Predicting according to ITRS (ITRS), the area of SRAM is by increasing, by 2015,
More than the 94% of whole SOC(system on a chip) (SOC) area will be accounted for.Therefore, the power consumption of SRAM, will directly influence
The power consumption of whole SOC.
Referring to shown in Fig. 1, Fig. 1 is the two-port SRAM data path using write bit line balancing technique.This typical case
Data path includes bit line precharge and equalizing circuit, memory element, and write driver.
Precharge is made up of PMOS transistor 105 with equalizing circuit.The phase inverter 101,104 that memory element is coupled by pair of cross
And NMOS transfer tube 102,103 is constituted.Write driver is made up of phase inverter 110 and tristate inverter 108,109.
When the write operation of two-port SRAM, effectively, write bit line equalizes write bit line equalizing signal (EQ_N) 118
Device PMOS transistor 105 is opened, and (WBLB) 113 anti-to write bit line (WBL) 112 and write bit line equalizes, storage
Redistribute at write bit line electric capacity (CWBL) 106 and write bit line stiffness (CWBLB) 107, thus by write bit line (WBL)
112 and write bit line instead (WBLB) 113 equalize to intermediate level.When equalization operation completes, write bit line equalizing signal (EQ_N)
118 is invalid, and write enable signal (WE) 119 effectively, write by the static state being made up of phase inverter 110 and tristate inverter 108,109
Write bit line (WBL) 112 and write bit line anti-(WBLB) 113, according to writing data (D) 120, will be driven to power supply by driver
VDD or ground VSS.Hereafter, write word line (WWL) 111 is effectively, anti-(WBLB) according to write bit line (WBL) 112 and write bit line
Level on 113, constitutes storage to the phase inverter 101,104 coupled by pair of cross and NMOS transfer tube 102,103 single
Unit carries out write operation.
Due to write operation each time will first by write bit line (WBL) 112 and write bit line anti-(WBLB) 113 equilibrium, then by
The static write driver of phase inverter 110 and tristate inverter 108,109 composition, will be to write bit line (WBL) according to writing data (D) 120
112 and write bit line instead (WBLB) 113 drive to corresponding level, it is assumed that the load capacitance on write bit line is CBL, write each time
During operation, the average inversion energy on bit line is 0.5CBLVDD2, and unrelated with the probability writing Data flipping.Occur even writing data
Time " 0 " or " 1 " that continues, the value that anti-(WBLB) 113 of write bit line (WBL) 112 and write bit line keeps with will write
When data (D) 121 are identical with writing anti-(DB) 120 of data, passive actuator drives the operation of write bit line to consume meaningless power consumption.
Therefore, designing certain and write anticipation circuit, the upset power consumption reducing write bit line in this case is highly significant.
[summary of the invention]
It is an object of the invention to propose a kind of low two-port SRAM writing power consumption, this circuit is when write operation, by upper
One cycle write data and current period writes the equalization operation that data are compared to decide whether to carry out write bit line.
To achieve these goals, the present invention adopts the following technical scheme that
A kind of low two-port SRAM writing power consumption, including decoder, storage array, control circuit and Pre-decoder,
Write bit line equalizer, static write driver and write anticipation comparator；
Decoder connects storage array by a plurality of wordline, and decoder connects control circuit with pre-also by a plurality of pre-decoder outputs
Decoder；
Storage array connects write bit line equalizer, static write driver by a plurality of write bit line and writes anticipation comparator；
Control circuit and Pre-decoder are by local clock and write enable and be connected write bit line equalizer, static state write driver and write anticipation
Comparator.
The present invention is further improved by: when writing enable and being effective, and the output of static write driver directly drives bit line；Write bit
Line equalizer when write bit line equalizing signal is effective to write bit line with write bit line is counter carries out electric voltage equalization, make them reach identical centre
Level；Write anticipation comparator the previous cycle is write data and currently writes data and compare, if it is different, then by write bit line equilibrium letter
Number it is set to effectively, the most invalid；When occurring that continuous print writes " 0 " or one writing operation, the data that bit line keeps are write with needs
The data entered are identical, write anticipation comparator and are set to by write bit line equalizing signal invalid, and bit line does not overturns；Write when double
During data difference, writing anticipation comparator, to put write bit line equalizing signal effective, write bit line and write bit line anti-on electric charge redistribute, write
Bit line and write bit line are instead equalized to intermediate level, and then write bit line equalizing signal is invalid, write enable effectively, and static write driver will
Bit line and anti-driven to the new level of bit line.
The present invention is further improved by: at the rising edge of external clock, and control circuit and decoder produce local clock and writing and make
Energy；At the rising edge of local clock, write bit line equalizer, static write driver and write the work of anticipation comparator, when continuous print occurs
When writing " 0 " or one writing operation, the data that write bit line keeps are identical with needing the data write, write bit line equalizer, quiet
State write driver and write anticipation comparator and will write data and receive on write bit line；When the double data difference write, write bit line is protected
The data held differ with the data needing write, write bit line equalizer, static write driver and write anticipation comparator to write bit line first
Equalize, then will write data cube computation to write bit line；Write word line decoding result according to decoder, on bit line, data are written into
Corresponding memory element in storage array.
The present invention is further improved by: when write operation, if write data are equal with the value kept on bit line, bit line is not sent out
Raw upset；If write data are contrary with the value kept on bit line, bit line overturns.
The present invention is further improved by: write bit line equalizer, static write driver and write anticipation comparator include chain of inverters and
NAND gate composition pulse-generating circuit or door, the first latch, XOR gate, d type flip flop, the second latch, phase inverter,
First tristate inverter, the second tristate inverter, write bit line electric capacity, write bit line stiffness and PMOS transistor；
Local clock connects the second input and the input of chain of inverters of NAND gate, writes and enables the first input connecting NAND gate
End, the outfan of chain of inverters connects the 3rd input of NAND gate；The outfan of NAND gate connects or the first input end of door；
Clock connects Enable Pin EN of the first latch, the clock end CK of d type flip flop and Enable Pin EN of the second latch；
The data input pin D of write data cube computation the second latch；The second of the data output end Q connection XOR gate of the second latch is defeated
Enter end, the data input pin D of d type flip flop, the input of phase inverter and the input of the second tristate inverter；
The outfan Q of d type flip flop connects the first input end of XOR gate, and the outfan of XOR gate connects the data of the first latch
Input D；The outfan Q of the first latch connects or the second input of door, or the outfan of door connects PMOS transistor
Grid；
The outfan of phase inverter connects the input of the first tristate inverter, and the outfan of the first tristate inverter connects write bit line electricity
Hold one end and the drain electrode of PMOS transistor, another termination VSS of write bit line electric capacity；The outfan of the second tristate inverter connects
Write bit line stiffness one end and the source electrode of PMOS transistor；Another termination VSS of write bit line stiffness.
The present invention is further improved by: when or door output write bit line equalizing signal be low level time, write bit line equalizer by
PMOS transistor is opened, and is stored in write bit line electric capacity and write bit line stiffness electric charge is redistributed, make write bit line and write bit line anti-
Reach an identical intermediate level；When write bit line equalizing signal is high level, write bit line equalizer is closed by PMOS transistor
Disconnected.
The present invention is further improved by: data are latched at the high level of clock by data latches, produces and stable writes data；
Writing data, to obtain writing data after reverser is anti-phase anti-；Write data and write data instead respectively through the second tristate inverter and the one or three
State phase inverter is connected to that write bit line is anti-and write bit line；When write bit line equalizing signal is high level, writes data and write the anti-warp respectively of data
Cross the second tristate inverter and the first tristate inverter drives write bit line anti-and write bit line；When write bit line equalizing signal is high level,
Second tristate inverter and the first tristate inverter are high-impedance state.
The present invention is further improved by: when clock is high level, and are write data by a upper cycle for latch and current period is write
The result of data XOR is latching to comparative result；At the rising edge of clock, d type flip flop by this cycle write data latch in a upper cycle
Write in data；At the rising edge of local clock, the pulse-generating circuit being made up of chain of inverters and NAND gate produces undersuing；
The pulse width of undersuing is determined by the time delay of chain of inverters；Undersuing and comparative result phase or obtain write bit line equilibrium letter
Number.
A kind of low two-port SRAM writing power consumption, described two-port SRAM, when write operation, is write pre-
Sentence circuit the previous cycle is write data and currently writes data and compare, if it is different, then write bit line equalizing signal is set to effectively,
Equalize write bit line and write bit line are counter；If identical, it is invalid to be set to by write bit line equalizing signal, write bit line and write bit line is counter does not has
There is any upset.
Relative to prior art, the invention have the advantages that when occurring that continuous print writes " 0 " or one writing operation, due to position
The data kept on line are identical with needing the data write, and write anticipation circuit and are set to by write bit line equalizing signal invalid, write bit line does not has
There is any upset, thus save power consumption.Write data upset probability be the situation of 50%, the present invention compared with traditional design,
The upset lower power consumption 50% of write bit line.
[accompanying drawing explanation]
Fig. 1 is the two-port SRAM data path schematic diagram using write bit line balancing technique.
Fig. 2 is the two-port SRAM schematic diagram implemented according to the present invention.
Fig. 3 is write bit line equalizer, static write driver and the design principle figure writing anticipation comparator.
Fig. 4 is the oscillogram of main signal in the present invention.
[detailed description of the invention]
Below in conjunction with the accompanying drawings embodiments of the present invention are described further.
As in figure 2 it is shown, Fig. 2 is the two-port SRAM example that anticipation circuit is write in the employing implemented according to the present invention.
This two-port SRAM includes decoder 201, storage array 202, control circuit and Pre-decoder 204, write bit line
Equalizer, static write driver and write anticipation comparator 205.
Decoder 201 connects storage array 202 by a plurality of wordline (WL) 206, and decoder 201 is also by a plurality of pre-decode
Device output (PRE_DEC) 208 connects control circuit and Pre-decoder 204；Control circuit and Pre-decoder 204 are also connected with ground
Location signal ADD, chip selection signal CEN, write enable WEN and clock signal clk.
Storage array 202 connects write bit line equalizer, static write driver also by a plurality of write bit line (WBL) 207 and writes pre-
Sentence comparator 205；
Control circuit and Pre-decoder 204 are also by local clock (LCLK) 209 and write enable (WEN_INT) 210 and be connected
Write bit line equalizer, static write driver and write anticipation comparator 205.
Its specific works principle is as follows:
At the rising edge of external clock (CLK) 213, control circuit and decoder 204 produce local clock 209 (LCLK)
With write enable 210 (WE_INT).At the rising edge of local clock 209 (LCLK), write bit line equalizer, static state write driving
Device and write anticipation comparator 205 and work, when occurring that continuous print writes " 0 " or one writing operation, due to write bit line (WBL)
The data kept on 207 are identical with data (D) 212 needing write, write bit line equalizer, static state write driver and write anticipation
Comparator 205 will be write data (D) 212 and be connected on write bit line (WBL) 207.When the double data difference write,
Data owing to keeping on write bit line (WBL) 207 differ with the data (D) 212 needing write, write bit line equalizer,
Static write driver and write anticipation comparator 205 and first equalize write bit line (WBL) 207, then will write data (D) 212 company
Receive on write bit line (WBL) 207.Write word line 206 (WL) decoding result according to decoder 201, bit line 207 (WBL)
Upper data are written in storage array corresponding memory element in 202.
When write operation, if write data 212 (D) value that keep upper with bit line 207 (WBL) is equal, then bit line 207
(WBL) not overturning, inversion energy is 0；If write data 212 (D) holding upper with bit line 207 (WBL)
Value is contrary, then bit line 207 (WBL) overturns, and inversion energy is 0.5CBLVDD2.If write data 212 (D)
Upset probability be 50%, then during write operation, the meansigma methods of the inversion energy of bit line is 0.25CBLVDD2, with traditional based on
The write bit line of the design of write bit line balancing technique averagely overturns power consumption 0.5CBLVDD2Compare, decline 50%.
Referring to Fig. 3, Fig. 3 is write bit line equalizer, static write driver and the design principle writing anticipation comparator 205, its by
Write bit line equalizer, static write driver and write anticipation comparator composition.
Write bit line equalizer, static write driver and write anticipation comparator 205 and include chain of inverters 301～303 and NAND gate 304
The pulse-generating circuit of composition or door the 305, first latch 306, XOR gate 307, d type flip flop the 308, second latch
309, phase inverter the 310, first tristate inverter the 311, second tristate inverter 312, write bit line electric capacity (CWBL)313、
Write bit line stiffness (CWBLB) 314 and PMOS transistor 315.
Local clock (LCLK) 209 connects the second input and the input of chain of inverters 301～303 of NAND gate 304, writes
Enabling (WEN_INT) 210 and connect the first input end of NAND gate 304, the outfan of chain of inverters 301～303 connects with non-
3rd input of door 304；The outfan of NAND gate 304 connects or the first input end of door 305.
Clock (CLK) connects Enable Pin EN of the first latch 306, the clock end CK of d type flip flop 308 and second and latches
Enable Pin EN of device 309；Write data (D) connects the data input pin D of the second latch 309；Second latch 309
Data output end Q connect the second input of XOR gate 307, the data input pin D of d type flip flop 308, phase inverter 310
Input and the input of the second tristate inverter 312.
The outfan Q of d type flip flop 308 connects the first input end of XOR gate 307, and the outfan of XOR gate 307 connects first
The data input pin D of latch 306；The outfan Q of the first latch 306 connects or the second input of door 305, or door
The outfan of 305 connects the grid of PMOS transistor 315.
The outfan of phase inverter 310 connects the input of the first tristate inverter 311, the outfan of the first tristate inverter 311
Connect write bit line electric capacity (CWBL) 313 one end and the drain electrode of PMOS transistor 315, write bit line electric capacity (CWBL) 313
Another terminates VSS；The outfan of the second tristate inverter 312 connects write bit line stiffness (CWBLB) 314 one end and PMOS
The source electrode of transistor 315；Write bit line stiffness (CWBLB) 314 another termination VSS.
Write bit line equalizer is made up of PMOS transistor 315.When write bit line equalizing signal (EQ_N) 319 is low level,
Write bit line equalizer is opened by PMOS transistor 315, is stored in write bit line electric capacity (CWBL) 313 and write bit line stiffness
(CWBLB) 314 electric charges will redistribute so that write bit line (WBL) reach with write bit line anti-(WBLB) one identical
Intermediate level.When write bit line equalizing signal (EQ_N) 319 is high level, write bit line equalizer is by PMOS transistor
315 turn off.
Static write driver is by data latches 309, phase inverter the 310, first tristate inverter 311 and the second tristate inverter
312 are constituted.Data 212 (D) are latched at the high level of clock (CLK) 213 by data latches 309, produce stable
Write data (WD) 326.Write data (WD) 326 to obtain writing anti-(WDB) 327 of data after reverser 310 is anti-phase.
Write data (WD) 326 and write anti-(WDB) 327 of data respectively through the second tristate inverter 312 and the first tristate inverter
311 are connected to anti-(WBLB) 329 of write bit line and write bit line (WBL) 328.When write bit line equalizing signal (EQ_N) 319
During for high level, write data (WD) 326 and write anti-(WDB) 327 of data respectively through the second tristate inverter 312 and the
One tristate inverter 311 drives write bit line anti-(WBLB) and write bit line (WBL).As write bit line equalizing signal (EQ_N)
319 when being high level, and the second tristate inverter 312 and the first tristate inverter 311 are high-impedance state.
Write anticipation comparator by d type flip flop 308, XOR gate 307, latch 306 or door 305 and by chain of inverters 301～303
Constitute with the pulse-generating circuit of NAND gate composition.When clock (CLK) 213 is high level, latch 306 is by a upper cycle
Write data (LD) 324 and current period is write the result (COMP_INT) 323 of data (WD) 326 XOR and is latching to compare
In result (COMP) 320.At the rising edge of clock (CLK) 213, this cycle write data latch is existed by d type flip flop 308
A upper cycle is write in data (LD) 324.At the rising edge of local clock (LCLK) 209, by chain of inverters 301～303
The pulse-generating circuit constituted with NAND gate produces undersuing (EQ_N_INT) 318.Undersuing (EQ_N_INT)
The pulse width of 318 is determined by the time delay of chain of inverters 301～303.Undersuing (EQ_N_INT) 318 and compare knot
Really (COMP) 320 phase or obtain write bit line equalizing signal (EQ_N) 319.
When write operation, when this cycle write data (WD) 326 and a upper cycle write data (LD) 324 identical time, write bit line
Equalizing signal (EQ_N) 319 is high level, and write bit line equalizer is turned off by PMOS transistor 315；Write data (WD)
326 drive write bit with writing anti-(WDB) 327 of data respectively through the second tristate inverter 312 and the first tristate inverter 311
Line anti-(WBLB) and write bit line (WBL).
When write operation, when this cycle write data (WD) 326 write from a upper cycle data (LD) 324 different time, write bit line
Equalizing signal (EQ_N) 319 is low level, and write bit line equalizer is opened by PMOS transistor 315, is stored in write bit line
Electric capacity (CWBL) 313 and anti-(the C of write bit lineWBLB) 314 electric charges will be redistributed, so that write bit line (WBL) and write bit
Line anti-(WBLB) reaches an identical intermediate level；Second tristate inverter 312 and the first tristate inverter 311 are high resistant
State.
Referring to Fig. 4, Fig. 4 is the oscillogram of main signal in the present invention.At the rising edge of local clock (LCLK), by scheming
In 3 chain of inverters 301～303 and the pulse-generating circuit that constitutes of NAND gate produce undersuing (EQ_N_INT) 318.Negative
The pulse width of pulse signal (EQ_N_INT) 318 is determined by the time delay of chain of inverters 301～303.At clock (CLK)
During for high level, a upper cycle is write data (LD) 324 by latch 306 and current period writes data (WD) 326 XOR
Result (COMP_INT) 323 is latching on comparative result (COMP) 320.At the rising edge of clock (CLK), D touches
Send out device 308 to be write in data (LD) 324 in a upper cycle by this cycle write data latch.
As shown in the waveform in first clock (CLK) cycle in Fig. 4, and refering to Fig. 3.A upper cycle writes data (LD) 324
Data (WD) 326 is identical with writing this week, and comparative result (COMP) 320 is high.Undersuing (EQ_N_INT)
318 with comparative result (COMP) 320 phase or obtain write bit line equalizing signal (EQ_N) 319 for high level.Write bit line (WBL)
Any upset is there is not with write bit line anti-(WBLB).
As shown in the waveform in second clock (CLK) cycle in Fig. 4, and refering to Fig. 3.A upper cycle writes data (LD) 324
Writing data (WD) 326 from this week different, comparative result (COMP) 320 is low.Undersuing (EQ_N_INT)
318 with comparative result (COMP) 320 phase or to obtain write bit line equalizing signal (EQ_N) 319 be a undersuing.?
The trailing edge of write bit line equalizing signal (EQ_N), write bit line (WBL) and write bit line anti-(WBLB) start equilibrium, write bit
Line (WBL) and write bit line anti-(WBLB) are equalized to intermediate level；At the rising edge of write bit line equalizing signal (EQ_N),
Write data (WD) 326 and write anti-(WDB) 327 of data respectively through the second tristate inverter 312 and the first tristate inverter
311 drive write bit line anti-(WBLB) and write bit line (WBL), write bit line (WBL) and write bit line anti-(WBLB) respectively
It is driven to corresponding level.
Claims (9)
1. the one kind low two-port SRAM writing power consumption, it is characterised in that include decoder, storage array, control
Circuit and Pre-decoder, write bit line equalizer, static write driver and write anticipation comparator；
Decoder connects storage array by a plurality of wordline (WL), and decoder is also by a plurality of pre-decoder outputs (PRE_DEC)
Connect control circuit and Pre-decoder；
Storage array connects write bit line equalizer, static write driver by a plurality of write bit line (WBL) and writes anticipation comparator；
Control circuit and Pre-decoder by local clock (LCLK) and write enable (WEN_INT) be connected write bit line equalizer,
Static write driver and write anticipation comparator.
A kind of low two-port SRAM writing power consumption the most according to claim 1, it is characterised in that make when writing
When energy (WEN_INT) is effective, the output of static write driver directly drives bit line；Write bit line equalizer is at write bit line equilibrium letter
Time number effective, write bit line is carried out electric voltage equalization with write bit line is counter, make them reach identical intermediate level；Write anticipation comparator by front
One cycle was write data and currently write data and compare, if it is different, then be set to effectively by write bit line equalizing signal, the most invalid；
When occurring that continuous print writes " 0 " or one writing operation, the data that bit line keeps are identical with the data needing write, write anticipation ratio
It is invalid to be set to by write bit line equalizing signal compared with device, and bit line does not overturns；When the double data difference write, write anticipation and compare
It is effective that write bit line equalizing signal put by device, write bit line and write bit line anti-on electric charge redistribute, write bit line and write bit line instead equalized to
Intermediate level, then write bit line equalizing signal is invalid, writes enable effectively, and static write driver is by anti-driven to new to bit line and bit line
Level.
A kind of low two-port SRAM writing power consumption the most according to claim 1, it is characterised in that in outside
The rising edge of clock (CLK), control circuit produces local clock (LCLK) with decoder and writes enable (WE_INT)；?
The rising edge of local clock (LCLK), write bit line equalizer, static write driver and write the work of anticipation comparator, when occurring even
Continuous when writing " 0 " or one writing operation, the upper data kept of write bit line (WBL) with to need the data (D) write identical,
Write bit line equalizer, static write driver and write anticipation comparator and will write data (D) and be connected on write bit line (WBL)；When continuously
During the data difference write for twice, the upper data kept of write bit line (WBL) differ with the data (D) needing write, write bit line
Equalizer, static write driver and write anticipation comparator and first equalize write bit line (WBL), then will write data (D) and be connected to
On write bit line (WBL)；Write word line (WL) decoding result according to decoder, the upper data of bit line (WBL) are written into storage
Corresponding memory element in array.
A kind of low two-port SRAM writing power consumption the most according to claim 3, it is characterised in that writing behaviour
When making, if write data (D) value that keep upper with bit line (WBL) is equal, bit line (WBL) does not overturns；If
Write data (D) value that keep upper with bit line (WBL) is contrary, and bit line (WBL) overturns.
A kind of low two-port SRAM writing power consumption the most according to claim 1, it is characterised in that write bit line
Equalizer, static write driver and write pulse-generating circuit that anticipation comparator includes that chain of inverters and NAND gate (304) form,
Or it is door (305), the first latch (306), XOR gate (307), d type flip flop (308), the second latch (309), anti-
Phase device (310), the first tristate inverter (311), the second tristate inverter (312), write bit line electric capacity (CWBL), write bit line
Stiffness (CWBLB) and PMOS transistor (315)；
Local clock (LCLK) connects the second input and the input of chain of inverters of NAND gate (304), writes enable
(WEN_INT) connecting the first input end of NAND gate (304), the outfan of chain of inverters connects the of NAND gate (304)
Three inputs；The outfan of NAND gate (304) connects or the first input end of door (305)；
Clock (CLK) connects Enable Pin EN of the first latch (306), the clock end CK of d type flip flop (308) and
Enable Pin EN of two latch (309)；Write data (D) connects the data input pin D of the second latch (309)；The
The data output end Q of two latch (309) connects the second input of XOR gate (307), the number of d type flip flop (308)
According to input D, the input of phase inverter (310) and the input of the second tristate inverter (312)；
The outfan Q of d type flip flop (308) connects the first input end of XOR gate (307), the output of XOR gate (307)
End connects the data input pin D of the first latch (306)；The outfan Q of the first latch (306) connects or door
(305) the second input, or the grid of outfan connection PMOS transistor (315) of door (305)；
The outfan of phase inverter (310) connects the input of the first tristate inverter (311), the first tristate inverter (311)
Outfan connect write bit line electric capacity (CWBL) one end and the drain electrode of PMOS transistor (315), write bit line electric capacity (CWBL)
Another termination VSS；The outfan of the second tristate inverter (312) connects write bit line stiffness (CWBLB) one end and PMOS
The source electrode of transistor (315)；Write bit line stiffness (CWBLB) another termination VSS.
A kind of low two-port SRAM writing power consumption the most according to claim 5, it is characterised in that when or door
(305), when the write bit line equalizing signal (EQ_N) exported is low level, write bit line equalizer is by PMOS transistor (315)
Open, be stored in write bit line electric capacity (CWBL) and write bit line stiffness (CWBLB) electric charge redistributes, and makes write bit line (WBL)
An identical intermediate level is reached with write bit line anti-(WBLB)；When write bit line equalizing signal (EQ_N) is high level,
Write bit line equalizer is turned off by PMOS transistor (315).
A kind of low two-port SRAM writing power consumption the most according to claim 6, it is characterised in that data (D)
Latched at the high level of clock (CLK) by data latches (309), produce and stable write data (WD)；Write data (WD)
After reverser (310) is anti-phase, obtain writing data anti-(WDB)；Write data (WD) and write data anti-(WDB) respectively
It is connected to write bit line anti-(WBLB) and write bit line through the second tristate inverter (312) and the first tristate inverter (311)
(WBL)；When write bit line equalizing signal (EQ_N) is high level, writes data (WD) and write data anti-(WDB) point
Do not drive write bit line anti-(WBLB) and write bit line through the second tristate inverter (312) and the first tristate inverter (311)
(WBL)；When write bit line equalizing signal (EQ_N) is high level, the second tristate inverter (312) and the first tri-state are anti-phase
Device (311) is high-impedance state.
A kind of low two-port SRAM writing power consumption the most according to claim 6, it is characterised in that at clock
(CLK) when being high level, latch (306) a upper cycle is write data (LD) and current period to write data (WD) different
Or result (COMP_INT) be latching to comparative result (COMP)；At the rising edge of clock (CLK), d type flip flop (308)
This cycle write data latch was write in data (LD) in a upper cycle；At the rising edge of local clock (LCLK), by phase inverter
The pulse-generating circuit that chain and NAND gate are constituted produces undersuing (EQ_N_INT)；Undersuing (EQ_N_INT)
Pulse width by chain of inverters time delay determine；Undersuing (EQ_N_INT) and comparative result (COMP) mutually or obtain
To write bit line equalizing signal (EQ_N).
9. the one kind low two-port SRAM writing power consumption, it is characterised in that described two-port SRAM exists
During write operation, write anticipation circuit and the previous cycle is write data and currently writes data and compare, if it is different, then write bit line is equalized
Signal is set to effectively, equalizes write bit line and write bit line are counter；If identical, it is invalid to be set to by write bit line equalizing signal, write bit
Line and write bit line is counter does not has any upset.
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